JP3691966B2 - Manufacturing method of semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for manufacturing a semiconductor device having a MOS (Metal Oxide Semiconductor) transistor, and more particularly to a method for manufacturing a semiconductor device suitable for manufacturing a DRAM (Dynamic Random Access Memory).
[0002]
[Prior art]
FIG. 7A is a cross-sectional view showing an example of a DRAM memory cell, and FIG. 7B is a circuit diagram of the memory cell.
A gate 54 is formed on the p-type silicon semiconductor substrate 51 via a gate oxide film 53. The side and upper portions of the gate 54 are covered with an insulating film 56. A pair of impurity regions (source / drain) 52 into which n-type impurities are introduced are formed in the surface layer of the semiconductor substrate 51 on both sides of the gate 54. The gate 54 and the pair of impurity regions 52 constitute a MOS transistor T shown in FIG. Note that the gate 54 extends in the direction perpendicular to the paper surface of FIG. 7A and forms the word line W shown in FIG. 7B.
[0003]
One of the pair of impurity regions 52 is connected to the lower layer electrode 57. This lower layer electrode 57 is formed so as to extend from above one impurity region 52 onto an insulating film 56 covering the gate 54. A dielectric film 58 and an upper layer electrode 59 are formed on the lower layer electrode 57. These electrodes 57 and 59 and the dielectric film 58 constitute a capacitor C shown in FIG.
[0004]
On the entire upper surface of the substrate 51, an interlayer insulating film 60 covering the capacitor C and the like is formed. A wiring 61 is formed on the interlayer insulating film 60, and the wiring 61 is connected to the other impurity region 52 through a contact hole formed in the interlayer insulating film 60. The wiring 61 corresponds to the bit line B in FIG.
As described above, the memory cell of the DRAM is composed of one MOS transistor T and one capacitor C. Therefore, it is easy to increase the density, and it is possible to realize a small memory with a low bit cost. The presence / absence of charge accumulated in the capacitor C is stored corresponding to data “0” and “1”.
[0005]
[Problems to be solved by the invention]
By the way, in the DRAM, data is stored by the electric charge accumulated in the capacitor C, but the electric charge accumulated in the capacitor C is caused by a leak (junction leak) from a pn junction (pn junction between the impurity region 52 and the substrate 51). Gradually lost. For this reason, in the DRAM, a refresh operation is performed in which data is read and written again at regular time intervals. However, if the junction leak increases, data is lost before refreshing, resulting in malfunction.
[0006]
In recent years, further higher integration of semiconductor devices has been promoted, and further miniaturization of MOS transistors constituting DRAMs is required. However, with the miniaturization of MOS transistors, the pn junction becomes shallower and the impurity concentration of the substrate also increases, so that the junction leakage tends to increase.
Note that in order to reduce junction leakage, it is conceivable to reduce the concentration of impurities implanted into the substrate 51. However, since the impurity concentration in the channel portion is reduced, a semiconductor device having desired transistor characteristics can be manufactured. Can not. In particular, in the case of a miniaturized semiconductor device, it is necessary to increase the impurity concentration of the channel portion in order to increase the threshold value.
[0007]
An object of the present invention is to provide a semiconductor device manufacturing method that can suppress an increase in junction leakage and obtain desired transistor characteristics even if the MOS transistor is miniaturized in a semiconductor device having a MOS transistor.
[0008]
[Means for Solving the Problems]
The above-described problems include a step of introducing a first conductivity type impurity into a semiconductor substrate, a step of forming a gate insulating film and a gate on the semiconductor substrate, and an element on the surface of the semiconductor substrate exposed on both sides of the gate. A step of damaging the surface layer of the substrate by ion implantation, and thermally oxidizing the surface of the semiconductor substrate exposed on both sides of the gate to form an oxide film on the substrate surface, which is introduced into the semiconductor substrate in the oxide film And a step of taking in the first conductivity type impurity and a step of introducing a second conductivity type impurity into the surface layer of the semiconductor substrate on both sides of the gate to form a source / drain. This is solved by the manufacturing method .
[0010]
The operation will be described below.
In the present invention, the peak value of the impurity concentration distribution of the impurity in the source / drain portion is lower than the peak value of the impurity concentration distribution in the channel depth direction of impurities (for example, boron) contained in the channel portion of the MOS transistor. Is set. For this reason, the impurity concentration on the low concentration side in the pn junction is reduced, and junction leakage is reduced.
[0011]
In the method of the present invention, first, a first conductivity type impurity is first introduced into the semiconductor substrate. The introduction of the first conductivity type impurity determines the impurity concentration of the channel portion. Then, after forming a gate insulating film and a gate, the substrate surface exposed on both sides of the gate is thermally oxidized to form oxide films on both sides of the gate. Impurities diffuse in the substrate by the heat applied at this time, and the impurities are taken into the oxide film as the oxide film is formed. As a result, the impurity concentration below the oxide film decreases, and the impurity concentration in the source / drain formation region becomes lower than the peak value of the impurity concentration distribution in the channel portion. Thereafter, a second conductivity type impurity is introduced on both sides of the gate to form a source / drain.
[0012]
Since the MOS transistor manufactured in this way has a low concentration of impurities (first conductivity type impurities) on the low concentration side at the pn junction between the source / drain and the substrate, junction leakage is reduced. Further, since the first conductivity type impurity concentration in the channel portion is relatively high, desired transistor characteristics (threshold value) can be obtained.
In addition, B (boron) can be used as the first conductivity type impurity. In this case, by setting the ion implantation energy to 10 keV or less, the peak of the B concentration distribution in the depth direction can be set near the substrate surface, and ions can be efficiently implanted into the substrate. In addition, before forming the oxide film, an inactive element such as Si, N, Ar, Ge or the like is ion-implanted into the semiconductor substrate to damage the surface layer of the substrate. Is preferred. As a result, the impurities are easily diffused during the formation of the oxide film, and the concentration of the impurities below the oxide film can be further reduced.
[0013]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.
(First embodiment)
FIG. 1 is a sectional view showing a semiconductor device (MOS transistor) according to an embodiment of the present invention.
[0014]
A pair of source / drain 12 is formed on the surface layer of the p-type semiconductor substrate 11 so as to be separated from each other. A gate 14 is formed between the pair of source / drain 12, that is, on the channel portion, with a gate oxide film 13 interposed therebetween. Side walls 15 made of silicon oxide or silicon nitride are formed on both sides of the gate 14.
[0015]
In the present embodiment, B (boron) is introduced into the semiconductor substrate 11 as a p-type impurity, and As (arsenic) is introduced into the source / drain 12 as an n-type impurity.
2A and 2B are diagrams showing impurity concentration distributions in the directions indicated by arrows X and Y in FIG. However, in FIGS. 2A and 2B, the horizontal axis indicates the depth in the arrow X direction and the arrow Y direction with the surface of the semiconductor substrate 11 as the origin. As shown in FIGS. 2 (a) and 2 (b), in the MOS transistor of the present embodiment, if the peak value of the B concentration distribution in the depth direction (arrow X portion) in the channel portion is N, The peak value of the B concentration distribution in the depth direction (arrow Y portion) in the drain portion is set lower than N. Therefore, the concentration of the p-type impurity (B) in the pn junction, that is, in the vicinity of the boundary between the n-type source / drain 12 is reduced, and junction leakage is reduced. On the other hand, since the B concentration in the channel portion is relatively high, desired transistor characteristics can be obtained.
[0016]
Hereinafter, a method for manufacturing the MOS transistor of this embodiment will be described.
3 and 4 are cross-sectional views showing the method of manufacturing the MOS transistor of this embodiment in the order of steps.
First, as shown in FIG. 3A, B ions are implanted into the entire upper surface of the silicon semiconductor substrate 11 in order to obtain a desired impurity concentration in the channel portion of the MOS transistor. The ion implantation conditions are, for example, an implantation energy of 10 keV and an implantation amount of 1.0 × 10 ¹³ cm ⁻² . In this case, since the implantation energy is low, the peak of the impurity concentration distribution of B is located near the substrate surface as shown in FIG.
[0017]
Next, as shown in FIG. 3B, the surface of the substrate 11 is thermally oxidized to form a gate oxide film 13 having a thickness of 4 nm. Then, a polysilicon film 14a is formed on the gate oxide film 13 by a CVD method or the like.
Next, as shown in FIG. 3C, the polysilicon film 14a is patterned using a photolithography technique to form the gate 14. Then, As is ion-implanted as an n-type impurity into the surface of the substrate 11 using the gate 14 as a mask, low-concentration impurity regions 12 a are formed in a self-aligned manner on the substrate surface layer on both sides of the gate 14. As conditions at the time of ion implantation at this time, for example, the implantation energy is 10 keV and the implantation amount is 5.0 × 10 ¹³ cm ⁻² .
[0018]
Thereafter, a silicon nitride film is formed to a thickness of 60 nm on the entire upper surface of the substrate 11, and anisotropic etching is performed to leave the silicon nitride film only on both sides of the gate 14, thereby forming the sidewalls 15. Thereafter, a portion of the gate oxide film 13 not covered with the gate 14 and the sidewall 15 is removed by etching, so that the surface of the substrate 11 is exposed. Note that the sidewall 15 may be formed of silicon oxide. However, the formation of silicon nitride as described above makes it difficult for device characteristics to change.
[0019]
Next, as shown in FIG. 4, the substrate surface exposed on both sides of the gate 14, that is, the surface of the low-concentration impurity region 12a is thermally oxidized to form an oxide film 16 having a thickness of about 15 nm. At this time, impurities are diffused under the oxide film 16 and taken into the oxide film 16, and as a result, the impurity concentration under the oxide film 16 is lowered.
Next, heat treatment is performed to activate the impurity region 12b. By this activation heat treatment, the impurity regions 12a and 12b become the source and drain, and a MOS transistor is formed.
[0020]
Thereafter, as in the prior art, SiO ₂ is deposited on the entire upper surface of the substrate 11 to form an interlayer insulating film, and contact holes are selectively formed in the interlayer insulating film. Then, a metal film is formed on the entire upper surface of the substrate 11, and the metal film is patterned to form wiring. In this case, the oxide film 16 may be removed as necessary. In this way, a semiconductor device having a MOS transistor is completed.
[0021]
In the present embodiment, the oxide film 16 is formed by thermally oxidizing the substrate surfaces on both sides of the gate 14 in the step shown in FIG. At this time, since the peak of the B impurity concentration distribution is near the substrate surface, the impurities are taken into the oxide film 16 and the peak value of the B impurity concentration distribution is reduced. As a result, the peak value of the B impurity concentration distribution in the source / drain portion is smaller than the peak value of the B impurity concentration distribution in the channel portion (see FIGS. 2A and 2B). Therefore, the concentration of the p-type impurity in the vicinity of the n-type source / drain boundary is lowered, and junction leakage is reduced. On the other hand, since the p-type impurity concentration in the channel portion is relatively high, characteristics such as a threshold value can be set as desired characteristics.
[0022]
Therefore, by forming a DRAM memory cell using the MOS transistor of the present embodiment, data loss due to junction leakage is avoided and the reliability of the DRAM is improved.
Note that if the peak of the channel impurity (B) is too close to the substrate surface, impurities may be taken into the gate oxide film 13 when the gate oxide film 13 is formed and the impurity concentration may be reduced. Accordingly, the gate oxide film 13 tends to be formed very thin, so that the amount of impurities taken into the gate oxide film 13 is extremely small and can be substantially ignored.
[0023]
FIG. 5 is a graph showing the relationship between the implantation energy of B and the surface concentration of the channel when the horizontal axis represents the implantation energy and the vertical axis represents the channel surface concentration (impurity concentration), and the dose is constant. . As can be seen from FIG. 5, the channel surface concentration increases when the implantation energy is lowered, but the change in channel surface concentration is small even when the implantation energy is 10 keV or less. From this, it can be said that it is efficient that the implantation energy of B is 10 keV or less.
[0024]
(Second Embodiment)
FIG. 6 is a diagram showing a method of manufacturing a semiconductor device (MOS transistor) according to the second embodiment of the present invention.
First, as shown in FIG. 6A, as in the first embodiment, B is ion-implanted over the entire upper surface of the semiconductor substrate 11, and then a gate oxide film 13, a gate 14, Sidewalls 15 and low-concentration impurity regions 12a are formed. Then, even if the silicon substrate 11 is implanted, such as Si, Ar, N, or Ge, the surface of the substrate 11 is ion-implanted with an inert element to damage the exposed portion of the surface of the substrate 11. Here, it is assumed that Si is ion-implanted.
[0025]
Next, as shown in FIG. 6B, the surface of the substrate on both sides of the gate 14 is thermally oxidized to form an oxide film 16. At this time, the impurity (B) in the vicinity of the surface of the semiconductor substrate 11 is diffused by heat, and B is taken into the oxide film 16 as the oxide film 16 is formed, and the concentration of B below the oxide film 16 decreases. To do. In the present embodiment, Si is ion-implanted into the surface layer of the low-concentration impurity region 12a before the oxide film 16 is formed, so that damage is more easily diffused in the substrate 11. Compared with the first embodiment, the impurity concentration of B below the oxide film 16 is further reduced.
[0026]
Thereafter, As is ion-implanted into the surface layer of the substrate 11 to form a high concentration impurity region 12b, and heat treatment for activation is performed. Then, an interlayer insulating film, wiring and the like are formed. In this way, the MOS transistor is completed.
In this embodiment, elements such as Si, Ar, N, or Ge are ion-implanted into the surface of the substrate 11 before the oxide film 10 is formed, thereby damaging the surface layer of the substrate 11 exposed on both sides of the gate 14. Therefore, the peak value of the impurity concentration of B in the depth direction in the source / drain portion can be further reduced as compared with the first embodiment. Thereby, there is an advantage that junction leakage is further reduced as compared with the first embodiment.
[0027]
【The invention's effect】
As described above, according to the present invention, the impurity concentration of the impurity in the depth direction of the source / drain portion compared to the peak value of the impurity concentration distribution in the depth direction of the channel portion according to the present invention. Since the peak value of the distribution is set low, the concentration of the low-concentration side impurities at the pn junction is low, and junction leakage is reduced. Further, since the impurity concentration in the channel portion is relatively high, desired transistor characteristics can be obtained. Thereby, high density and high reliability of a semiconductor device such as a DRAM are achieved.
[0028]
In the method of the present invention, the first conductivity type impurity is introduced into the semiconductor substrate to form the gate insulating film and the gate, and then the surface of the semiconductor substrate exposed on both sides of the gate is thermally oxidized to form the oxide film. As a result, the impurity concentration below the oxide film is reduced, and the impurity concentration distribution of the first conductivity type impurity in the depth direction of the channel portion and the impurity concentration distribution of the first conductivity type impurity in the depth direction of the source / drain portion are Therefore, desired transistor characteristics can be obtained, and junction leakage is reduced.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view showing a semiconductor device (MOS transistor) according to an embodiment of the present invention.
2A and 2B are diagrams showing impurity concentration distributions in directions indicated by arrows X and Y in FIG.
FIG. 3 is a sectional view (No. 1) showing a method of manufacturing a MOS transistor according to the present embodiment in the order of steps;
FIG. 4 is a sectional view (No. 2) showing the method of manufacturing the MOS transistor of this embodiment in the order of steps.
FIG. 5 is a graph showing the relationship between the implantation energy of B and the surface concentration of the channel when the dose is constant.
FIG. 6 is a diagram illustrating a method of manufacturing a semiconductor device (MOS transistor) according to a second embodiment of the present invention.
FIG. 7A is a cross-sectional view showing an example of a DRAM memory cell, and FIG. 7B is a circuit diagram of the memory cell.
[Explanation of symbols]
11, 51 semiconductor substrate,
12,52 source / drain,
12a low concentration impurity region,
12b high concentration impurity region,
13, 53 gate oxide film,
14,54 gates,
15 side walls,
16 oxide film,
57 Lower electrode,
58 dielectric film,
59 Upper layer electrode.

Claims (4)

Introducing a first conductivity type impurity into the semiconductor substrate;
Forming a gate insulating film and a gate on the semiconductor substrate;
Damaging the substrate surface by ion-implanting elements into the surface of the semiconductor substrate exposed on both sides of the gate;
Thermally oxidizing the surface of the semiconductor substrate exposed on both sides of the gate to form an oxide film on the substrate surface, and incorporating the first conductivity type impurity introduced into the semiconductor substrate into the oxide film;
Forming a source / drain by introducing a second conductivity type impurity into the surface layer of the semiconductor substrate on both sides of the gate;
A method of manufacturing a semiconductor device, wherein the steps are performed in order. 2. The method of manufacturing a semiconductor device according to claim 1 , wherein the first conductivity type impurity is boron. 3. The method of manufacturing a semiconductor device according to claim 2 , wherein the boron is ion-implanted into the semiconductor substrate with an implantation energy of 10 keV or less. 2. The semiconductor device according to claim 1 , wherein an element to be ion-implanted for damaging the surface layer of the substrate is any one element selected from the group consisting of Si, N, Ar, and Ge. Manufacturing method.

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