JP2000031482A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device and a manufacturing method thereof, whereby in a semiconductor device having an MOS transistor, if the MOS transistor is made fine, the junction leak increase can be suppressed. SOLUTION: B ions are implanted at energy of 10 keV or less on the entire upper surface of a substrate 11, a gate oxide film 13, a gate 14 and a sidewall 15 are formed on the substrate 11, As ions are implanted at both sides of the gate 14 to form impurity regions 12a, and the surfaces of the impurity regions 12a are thermally oxidized to form oxide films 16, while B diffuses in the substrate 11 and are taken in the oxide films 16 to reduce the B concn. below that of the oxide films 16.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a MOS (Metal Ox
The present invention relates to a semiconductor device having a transistor and a method of manufacturing the same, and particularly to a DRAM (Dynamic Rand).
and a method for manufacturing the same.

[0002]

2. Description of the Related Art FIG. 7A is a sectional view showing an example of a DRAM memory cell, and FIG. 7B is a circuit diagram of the memory cell. On the p-type silicon semiconductor substrate 51, a gate 54 is formed via a gate oxide film 53.
The side and upper part of the gate 54 are covered with an insulating film 56. On the surface layer of the semiconductor substrate 51 on both sides of the gate 54,
A pair of impurity regions (source / drain) 52 into which an n-type impurity is introduced are formed. By the gate 54 and the pair of impurity regions 52, the MO shown in FIG.
An S transistor T is configured. The gate 54
7A extend in a direction perpendicular to the paper surface of FIG.
The word line W shown in FIG.

One of a pair of impurity regions 52 is connected to a lower electrode 57. The lower electrode 57 extends from above one of the impurity regions 52 to above the insulating film 56 covering the gate 54. On the lower electrode 57, a dielectric film 58 and an upper electrode 59 are formed. By these electrodes 57 and 59 and the dielectric film 58, FIG.
The capacitor C shown in FIG.

[0004] On the entire upper surface of the substrate 51, an interlayer insulating film 60 covering the capacitor C and the like is formed. A wiring 61 is formed on the interlayer insulating film 60, and the wiring 61 is connected to the other impurity region 52 via a contact hole formed in the interlayer insulating film 60. This wiring 61
Corresponds to the bit line B in FIG. in this way,
The memory cell of the DRAM is constituted by one MOS transistor T and one capacitor C. Therefore, it is easy to achieve high density, and a small-sized memory with low bit cost can be realized. The presence or absence of the electric charge stored in the capacitor C is stored in correspondence with the data “0” and “1”.

[0005]

By the way, in the DRAM, data is stored by the electric charge stored in the capacitor C, and the electric charge stored in the capacitor C is transferred to the pn junction (the pn junction between the impurity region 52 and the substrate 51). )) (Junction leak). For this reason, the DRAM performs a refresh operation of reading data at regular intervals and writing data again. However, if the junction leak increases, data is lost before refreshing, resulting in malfunction.

In recent years, higher integration of semiconductor devices has been promoted, and further miniaturization of MOS transistors constituting DRAM has been required. However, the pn junction becomes shallower with the miniaturization of the MOS transistor, and the impurity concentration of the substrate becomes higher, so that the junction leakage tends to increase. In order to reduce junction leakage, the substrate 5
Although it is conceivable to lower the concentration of the impurity to be implanted into the transistor 1, the impurity concentration in the channel portion becomes lower, so that a semiconductor device having desired transistor characteristics cannot be manufactured. Especially in the case of miniaturized semiconductor devices,
In order to increase the threshold, it is necessary to increase the impurity concentration in the channel portion.

An object of the present invention is to provide a semiconductor device having a MOS transistor, which can suppress an increase in junction leakage even if the MOS transistor is miniaturized and can obtain desired transistor characteristics, and a method of manufacturing the same. That is.

[0008]

SUMMARY OF THE INVENTION The above-mentioned problem is solved by a MOS transistor.
In a semiconductor device having a transistor, the MOS
The peak value of the impurity concentration distribution of the impurity in the depth direction of the source / drain portion is lower than the peak value of the impurity concentration distribution of the impurity contained in the channel portion of the transistor in the depth direction of the channel portion. The problem is solved by the following semiconductor device.

[0009] The above-mentioned problems include a step of introducing a first conductivity type impurity into a semiconductor substrate, a step of forming a gate insulating film and a gate on the semiconductor substrate, and a step of forming a gate insulating film and a gate on both sides of the gate. A step of thermally oxidizing the surface to form an oxide film on the substrate surface and incorporating the first conductivity type impurity introduced into the semiconductor substrate into the oxide film; and forming a second conductivity type impurity on the surface of the semiconductor substrate on both sides of the gate. Forming a source / drain by introducing an impurity.

Hereinafter, the operation will be described. In the present invention, the peak value of the impurity concentration distribution in the source / drain portion is lower than the peak value of the impurity concentration distribution in the channel depth direction of the impurity (for example, boron) contained in the channel portion of the MOS transistor. Is set. For this reason, the impurity concentration on the low concentration side at the pn junction becomes low, and the junction leakage is reduced.

In the method of the present invention, first, a first conductivity type impurity is introduced into a semiconductor substrate. The introduction of the first conductivity type impurity determines the impurity concentration of the channel portion. After forming a gate insulating film and a gate, the surface of the substrate exposed on both sides of the gate is thermally oxidized to form oxide films on both sides of the gate. At this time, the heat diffuses the impurities in the substrate, and the impurities are taken into the oxide film as the oxide film is formed. Accordingly, the impurity concentration below the oxide film decreases, and the impurity concentration in the source / drain formation region becomes lower than the peak value of the impurity concentration distribution in the channel portion. Thereafter, a source / drain is formed by introducing a second conductivity type impurity on both sides of the gate.

In the MOS transistor manufactured as described above, since the concentration of the low-concentration impurity (first conductivity type impurity) at the pn junction between the source / drain and the substrate is low, the junction leakage is reduced. Also, the first of the channel section
Since the conductivity type impurity concentration is relatively high, desired transistor characteristics (threshold) can be obtained. In addition, B (boron) can be used as the first conductivity type impurity.
In this case, by setting the ion implantation energy to 10 keV or less, the peak of the B concentration distribution in the depth direction can be set near the substrate surface, and the ions can be efficiently implanted into the substrate. Before the formation of the oxide film, S
It is preferable that an inert element such as i, N, Ar, and Ge be ion-implanted even if it is ion-implanted into a semiconductor substrate to damage a surface layer of the substrate. This facilitates the diffusion of impurities during the formation of the oxide film, so that the concentration of impurities below the oxide film can be further reduced.

[0013]

Embodiments of the present invention will be described below with reference to the accompanying drawings. (First Embodiment) FIG. 1 is a sectional view showing a semiconductor device (MOS transistor) according to an embodiment of the present invention.

On the surface layer of the p-type semiconductor substrate 11, a pair of source / drain 12 is formed apart from each other. A gate 14 is formed between the pair of source / drain 12, that is, above the channel portion, with a gate oxide film 13 interposed therebetween. Side walls 15 made of silicon oxide or silicon nitride are formed on both sides of the gate 14.

In the present embodiment, the semiconductor substrate 11
Has B (boron) introduced as a p-type impurity,
As (arsenic) is introduced into the source / drain 12 as an n-type impurity. FIGS. 2A and 2B are diagrams showing impurity concentration distributions in the directions indicated by arrows X and Y in FIG. However, in FIGS. 2A and 2B, the horizontal axis indicates the depth in the arrow X direction and the arrow Y direction with the surface of the semiconductor substrate 11 as the origin. As shown in FIG.
As shown in (b), in the MOS transistor according to the present embodiment, the depth direction in the channel portion (portion indicated by arrow X)
Assuming that the peak value of the B concentration distribution is N, the peak value of the B concentration distribution in the depth direction (the portion indicated by the arrow Y) in the source / drain portion is set lower than N. Therefore, pn
The concentration of the p-type impurity (B) in the junction, that is, in the vicinity of the boundary between the n-type source / drain 12 is reduced, and the junction leakage is reduced. On the other hand, since the B concentration in the channel portion is relatively high, desired transistor characteristics can be obtained.

Hereinafter, a method of manufacturing the MOS transistor according to the present embodiment will be described. 3 and 4 are sectional views showing a method of manufacturing the MOS transistor according to the present embodiment in the order of steps. First, as shown in FIG. 3A, B ions are implanted into the entire upper surface of the silicon semiconductor substrate 11 in order to make the impurity concentration in the channel portion of the MOS transistor a desired concentration. Conditions for the ion implantation include, for example, an implantation energy of 10 keV and an implantation amount of 1.0 × 10 ¹³ cm.
^-2 . In this case, since the implantation energy is low, FIG.
As shown in (a), the peak of the impurity concentration distribution of B is located near the substrate surface.

Next, as shown in FIG.
Surface is thermally oxidized to form a gate oxide film 1 having a thickness of 4 nm.
Form 3 Then, a polysilicon film 14a is formed on the gate oxide film 13 by a CVD method or the like. Next, as shown in FIG. 3C, the polysilicon film 14a is patterned by using the photolithography technique,
4 is formed. Using the gate 14 as a mask, As is ion-implanted into the surface of the substrate 11 as an n-type impurity.
2a is formed in a self-aligned manner. Conditions for the ion implantation at this time include, for example, an implantation energy of 10 keV,
The injection amount is 5.0 × 10 ¹³ cm ⁻² .

Thereafter, a silicon nitride film is formed on the entire upper surface of the substrate 11 to a thickness of 60 nm, and is subjected to anisotropic etching to leave the silicon nitride film only on both sides of the gate 14, thereby forming a sidewall 15. I do. Thereafter, portions of the gate oxide film 13 that are not covered with the gate 14 and the sidewalls 15 are removed by etching to expose the surface of the substrate 11. Note that the sidewall 15 may be formed of silicon oxide. However, by forming the device from silicon nitride as described above, device characteristics hardly fluctuate.

Next, as shown in FIG. 4, the substrate surface exposed on both sides of the gate 14, that is, the low-concentration impurity region 12 is formed.
a surface is thermally oxidized to form an oxide film 1 having a thickness of about 15 nm.
6 is formed. At this time, the impurities diffuse below the oxide film 16 and are taken into the oxide film 16, and as a result, the impurity concentration below the oxide film 16 decreases. Next, heat treatment is performed to activate the impurity regions 12b. By this activation heat treatment, the impurity regions 12a and 12b become the source / drain, and a MOS transistor is formed.

Thereafter, as in the prior art, SiO ₂ is deposited on the entire upper surface of the substrate 11 to form an interlayer insulating film, and contact holes are selectively formed in the interlayer insulating film. Then, a metal film is formed on the entire upper surface of the substrate 11, and the metal film is patterned to form a wiring. In this case, the oxide film 16 may be removed as needed. Thus, M
A semiconductor device having an OS transistor is completed.

In the present embodiment, in the step shown in FIG. 4, an oxide film 16 is formed by thermally oxidizing the substrate surface on both sides of the gate 14. At this time, since the peak of the B impurity concentration distribution is near the substrate surface, the impurities are taken into the oxide film 16 and the peak value of the B impurity concentration distribution decreases. Thus, the peak value of the B impurity concentration distribution in the source / drain portion is smaller than the peak value of the B impurity concentration distribution in the channel portion (FIG. 2).
(See (a) and (b)). Therefore, the concentration of the p-type impurity in the vicinity of the boundary between the n-type source and drain is reduced, and the junction leakage is reduced. On the other hand, since the p-type impurity concentration of the channel portion is relatively high, characteristics such as a threshold value can be set to desired characteristics.

Therefore, by configuring a memory cell of a DRAM using the MOS transistor of the present embodiment, data loss due to junction leakage is avoided, and
The reliability of the RAM is improved. If the peak of the channel impurity (B) is too close to the substrate surface, the gate oxide film 1
There is a possibility that impurities may be taken into the gate oxide film 13 at the time of forming the gate oxide film 3 and the impurity concentration may decrease. However, with the recent miniaturization of elements, the gate oxide film 13 tends to be formed extremely thin. The amount of impurities taken into oxide film 13 is extremely small and can be substantially ignored.

FIG. 5 shows the relationship between the implantation energy of B and the surface concentration of the channel when the dose is constant, with the implantation energy on the horizontal axis and the surface concentration (impurity concentration) on the channel on the vertical axis. FIG. As can be seen from FIG. 5, the channel surface concentration increases as the implantation energy decreases, but the change in the channel surface concentration decreases even when the implantation energy is reduced to 10 keV or less. From this,
It can be said that it is efficient to set the implantation energy of B to 10 keV or less.

(Second Embodiment) FIG. 6 shows a second embodiment of the present invention.
FIG. 10 is a diagram illustrating the method of manufacturing the semiconductor device (MOS transistor) according to the embodiment. First, as shown in FIG. 6A, B ions are implanted into the entire upper surface of the semiconductor substrate 11 in the same manner as in the first embodiment, and then the gate oxide film 13, the gate 14, The side wall 15 and the low concentration impurity region 12a are formed. Then, the silicon substrate 1 such as Si, Ar, N or Ge is formed on the surface of the substrate 11.
Even if 1 is implanted, an inert element is ion-implanted to damage the exposed surface of the substrate 11. Here, it is assumed that Si is ion-implanted.

Next, as shown in FIG.
The substrate surface on both sides of the substrate 4 is thermally oxidized to form an oxide film 16. At this time, the impurity (B) near the surface of the semiconductor substrate 11 is diffused by heat, and B is taken into the oxide film 16 with the formation of the oxide film 16, and the concentration of B below the oxide film 16 decreases. I do. In the present embodiment, before the oxide film 16 is formed, Si is ion-implanted into the surface layer of the low-concentration impurity region 12a to damage the impurity. The impurity concentration of B below oxide film 16 is further reduced as compared with the embodiment.

Thereafter, As is ion-implanted into the surface layer of the substrate 11 to form the high-concentration impurity regions 12b, and a heat treatment for activation is performed. Then, an interlayer insulating film, a wiring, and the like are formed. Thus, a MOS transistor is completed. In the present embodiment, before the oxide film 10 is formed, an element such as Si, Ar, N, or Ge is ion-implanted into the surface of the substrate 11 to damage the surface layer of the substrate 11 exposed on both sides of the gate 14. Therefore, the peak value of the impurity concentration of B in the depth direction in the source / drain portions can be further reduced as compared with the first embodiment. Thereby, there is an advantage that the junction leak is further reduced as compared with the first embodiment.

[0027]

As described above, according to the present invention,
As for the impurities contained in the channel portion, the peak value of the impurity concentration distribution of the impurity in the depth direction of the source / drain portion is set lower than the peak value of the impurity concentration distribution in the depth direction of the channel portion. The low-concentration side impurity concentration at the pn junction is low, and junction leakage is reduced. Further, since the impurity concentration in the channel portion is relatively high, desired transistor characteristics can be obtained. Thereby, high density and high reliability of a semiconductor device such as a DRAM are achieved.

In the method of the present invention, a first conductivity type impurity is introduced into a semiconductor substrate to form a gate insulating film and a gate, and then the surface of the semiconductor substrate exposed on both sides of the gate is thermally oxidized to form an oxide film. Form. Thereby, the impurity concentration below the oxide film is reduced, and the impurity concentration distribution of the first conductivity type impurity in the depth direction of the channel portion and the impurity concentration distribution of the first conductivity type impurity in the depth direction of the source / drain portions are reduced. Are different from each other, desired transistor characteristics can be obtained, and junction leakage is reduced.

[Brief description of the drawings]

FIG. 1 is a semiconductor device (MO) according to an embodiment of the present invention;
FIG. 4 is a cross-sectional view illustrating an S transistor).

FIGS. 2A and 2B show arrows X and Y in FIG.
FIG. 5 is a diagram showing an impurity concentration distribution in a direction indicated by.

FIG. 3 is a sectional view (No. 1) showing a method for manufacturing the MOS transistor according to the present embodiment in the order of steps.

FIG. 4 is a cross-sectional view (No. 2) illustrating the method of manufacturing the MOS transistor according to the present embodiment in the order of steps.

FIG. 5 is a diagram showing the relationship between B implantation energy and channel surface concentration when the dose is constant.

FIG. 6 is a diagram illustrating a method of manufacturing a semiconductor device (MOS transistor) according to a second embodiment of the present invention.

FIG. 7A is a cross-sectional view showing an example of a memory cell of a DRAM, and FIG. 7B is a circuit diagram of the same memory cell.

[Explanation of symbols]

 11, 51 semiconductor substrate, 12, 52 source / drain, 12a low concentration impurity region, 12b high concentration impurity region, 13, 53 gate oxide film, 14, 54 gate, 15 sidewall, 16 oxide film, 57 lower electrode, 58 Dielectric film, 59 Upper electrode.

Claims (6)

[Claims] 1. A semiconductor device having a MOS transistor, wherein a peak of an impurity concentration distribution of an impurity contained in a channel portion of the MOS transistor in a depth direction of the channel portion is larger in a depth direction of the source / drain portion. A semiconductor device, wherein a peak value of an impurity concentration distribution of the impurity is low. A step of introducing a first conductivity type impurity into the semiconductor substrate; a step of forming a gate insulating film and a gate on the semiconductor substrate; and a step of heating a surface of the semiconductor substrate exposed on both sides of the gate. Oxidizing to form an oxide film on the substrate surface and incorporating the first conductivity type impurity introduced into the semiconductor substrate into the oxide film; and introducing a second conductivity type impurity into the semiconductor substrate surface layer on both sides of the gate. Forming a source / drain by performing the method. 3. The method according to claim 2, wherein the first conductivity type impurity is boron. 4. The method according to claim 3, wherein the boron is ion-implanted into the semiconductor substrate at an implantation energy of 10 keV or less. 5. The semiconductor device according to claim 2, wherein before forming the oxide film, an element is ion-implanted into a surface of the substrate exposed on both sides of the gate to damage a surface layer of the substrate. Production method. 6. The element to be ion-implanted is Si, N,
The method according to claim 5, wherein the element is any one element selected from the group consisting of Ar and Ge.