JPH025436A - Manufacture of field-effect transistor - Google Patents

Abstract

PURPOSE:To form a thin diffused layer on the sidewall of a groove and to reduce an area exclusively used for a transistor on a substrate by forming high concentration source, drain diffused layer in the bottom of the groove, and then ion implanting the sidewall of the groove in a state that an ion beam has a predetermined angle with respect to the substrate. CONSTITUTION:After an isolating oxide film is formed on a P-type silicon substrate 1, a polysilicon gate electrode 3 is formed of positive resist 2. Then, with the resist 2 as a mask as it is a groove 4 is formed on the substrate by anisotropic dry etching. Thereafter, an ion implantation is so conducted that the substrate becomes substantially perpendicular to an arsenic ion beam to form a high concentration N-type diffused layer 5, an ion implantation is so conducted that an ion beam has an angle of 60 deg. to the surface of the substrate to form a thin diffused layer 6. Thus, a thin diffused layer formed on the sidewall of the groove is formed with satisfactorily uniform concentration, and since the formed transistor is formed with the region of the thin diffused layer substantially perpendicularly thereto, an area exclusively used on the substrate can be extremely decreased.

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Field of Application) The present invention is directed to a microscopic device formed on a semi-quadratic substrate.
The present invention relates to a method of manufacturing a field effect transistor having a (Lightly Doped Drain) structure.

(Prior Art) A field effect transistor, which is one of the active elements fabricated on a semiconductor substrate, uses polysilicon or a high melting point metal material for the gate electrode, and has drain and source diffusion layers formed in a self-aligned manner. Most common. In a field effect transistor with this structure, when it is necessary to increase the withstand voltage between the drain and source, a dense diffusion layer is formed at a certain distance from the effective gate part, and inside it is self-aligned with the gate. A so-called LDD structure in which a thin diffusion layer is formed is being used.

(Problems to be Solved by the Invention) As described in Section 2, in conventional field effect transistors having an LDD structure, it is necessary to form a thin diffusion layer over a certain distance from the gate. This increases the area occupied by the device, which hinders higher integration. Furthermore, in the manufacturing process, in order to create a space for the thin diffusion layer, it is necessary to take measures such as forming a spacer of some kind of material on the side wall of the gate, which adds a fairly complicated process.

(Means for Solving the Problems) In order to solve the above problems, the present invention forms a gate electrode using polysilicon or a high melting point metal material, and then etches the gate electrode into a semiconductor substrate portion that will become a source and a drain. After forming a groove in a self-aligned manner with respect to the electrode and isolation oxide film and forming a dense source/drain diffusion layer at the bottom of the groove, ions are placed on the sidewall of the groove with the substrate at a certain angle to the ion beam. By injecting
By making improvements to form a thin diffusion layer on the side walls of the groove,
A field effect transistor having an LDD structure was manufactured.

(Function) In the method for manufacturing a field effect transistor of the present invention,
A thin diffusion layer formed on the side wall of the groove is formed with good concentration uniformity. In the resulting transistor, the area of the thin diffusion layer is formed almost vertically, so the area occupied on the substrate is extremely small. In addition, the grooves formed in the substrate are formed in a self-aligned manner with respect to the gate electrode and the isolation oxide film.
The process is extremely simple.

(Example) Next, the present invention will be described in detail by way of an example with reference to the drawings. 1 to 3 are cross-sectional views showing the process flow. In the embodiment, an N-type field effect transistor is shown. First, as shown in FIG. 1, after forming an isolation oxide film on a P-type silicon substrate 1 using a well-known selective oxidation method,
A gate oxide film with a thickness of 1 nm is formed, and then polysilicon with a thickness of about 400 nm is deposited, and a polysilicon gate electrode 3 is formed using a positive resist 2. Next, using the positive resist 2 as a mask, grooves 4 are formed in the substrate by anisotropic dry etching as shown in FIG. After this, ion implantation is performed so that the substrate and the arsenic ion beam are almost perpendicular to form a dense N-type diffusion layer 5, and then ion implantation is performed so that the ion beam is at an angle of 60'' with the substrate surface. A thin diffusion layer 6 is formed.After this, a 800 nm BPSG film 7 shown in FIG. was 12-mm, and the depth of the groove was about 0.3-mm.

(Effects of the Invention) According to the above embodiment, the area was reduced by about 30% compared to a field effect transistor having a spacer provided on the sidewall of the gate polysilicon. Furthermore, since the thin diffusion layer is formed by ion implantation, the characteristics are extremely stable and there are few variations.

[Brief explanation of the drawing]

FIG. 1, FIG. 2, and FIG. 3 are diagrams sequentially showing the steps of the method for manufacturing a field effect transistor of the present invention. 1... P-type silicon substrate, 2... positive resist, 3... polysilicon gate electrode, 4...
Groove formed in silicon substrate, 5...Dense N-type diffusion layer, 6...Thin N-type diffusion layer, 7...BP
SG film, 8...aluminum wiring. Figure 2 Home resist Figure 2

Claims (1)

[Claims] A step of forming an element isolation region on a semiconductor substrate by selective oxidation, a step of forming a gate electrode of polysilicon or a high melting point metal material, and a step of forming an element isolation region on the substrate in a self-aligned manner with respect to the gate electrode and the element isolation region. a step of forming a groove;
By forming a highly concentrated diffusion layer having a conductivity type opposite to that of the substrate at the bottom of the groove by ion implantation, and by performing ion implantation on the side wall of the groove with the substrate tilted with respect to the ion beam, the concentration can be increased. A method for manufacturing a field effect transistor, comprising the step of forming a low diffusion layer.