JPH02265250A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To reduce a leakage current of a source-drain diffusion layer by a method wherein an insulating film on an element formation region other than a side face of a gate electrode is removed by a wet etching operation at a final stage to form a sidewall. CONSTITUTION:A gate insulating film 4a is formed on the surface of an element formation region; a polycrystalline silicon film is deposited on the surface including it; a gate electrode 5 is formed selectively; its surface is oxidized thermally; an oxide film 4b is formed. Then, impurity ions are implanted by making use of the gate electrode 5 and a field insulating film 3 as a mask; a low-concentration diffusion region 6 of an opposite conductivity type is formed in the element formation region; an insulating film 7 is deposited on the surface including the gate electrode 5; a polycrystalline silicon film 8 is formed on it. The polycrystalline silicon film 8 is left only on side faces of the gate electrode 5 by an anisotropic etching operation; the polycrystalline silicon film 8 in other parts is removed; the insulating film 7 other than side-walls is removed by a wet etching operation; a high-concentration diffusion layer 9, of the opposite conductivity type, which is connected to the low-concentration diffusion layer 6 is formed in the element formation region. Thereby, a leakage current is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for manufacturing a semiconductor device having an insulated gate field effect transistor.

[Conventional technology]

Insulated gate field effect transistor (hereinafter referred to as MOSFET)
In order to avoid characteristic fluctuations and punch-through caused by hot electrons that occur with the miniaturization and high integration of semiconductor devices, a mask layer formed on the sidewalls of the gate electrode is used to partially reduce the impurity concentration in the diffusion region. There is a method of relaxing the electric field in the train region by changing the

The conventional manufacturing method for semiconductor devices is to form a low concentration diffusion layer by ion-implanting low concentration impurities in a self-aligned manner using a gate electrode covered with a thermal oxide film and a field oxide film as masks, and then to form a low concentration diffusion layer. An insulating film is deposited on the surface including the gate electrode by the CVD method, and this is anisotropically etched to form side walls, leaving the insulating film only on the side surfaces of the gate electrode, and removing the insulating film on other parts. Next, using the gate electrode having this side wall as a mask, high concentration impurity ions are implanted to form a high concentration diffusion layer connected to the low concentration diffusion layer.

[Problem to be solved by the invention]

In the conventional semiconductor device manufacturing method described above, the etching rate for anisotropic etching is the same for the insulating film provided in advance on the side surface of the gate electrode and the insulating film deposited subsequently. Due to the non-uniformity of the etching rate, the shape of the mask sidewalls formed is not uniform, and in the worst case, the film grown on the sidewalls is also etched, resulting in no sidewalls being formed.

In addition, reactive ion etching is generally used as the above-mentioned anisotropic etching, but in the final stage of etching, the surface of the source/drain region is exposed to an etching atmosphere and the surface is etched. There is a drawback that leakage current in the source/train region increases due to contamination, defects, etc.

[Means to solve the problem]

The method for manufacturing a semiconductor device of the present invention includes: (A) selectively providing a field insulating film for element thickness on the main surface of a semiconductor substrate of one conductivity type to demarcate an element formation region; A step of forming a gate insulating film, depositing a polycrystalline silicon film on the surface including the gate insulating film, selectively etching it to form a gate electrode, and thermally oxidizing the surface of the gate electrode to form an oxide film. A step of ion-implanting a low concentration impurity using the gate electrode and the field insulating film as a mask to form a low concentration diffusion layer of an opposite conductivity type in the element formation region; A step of oxidizing the surface including the gate electrode. (E) depositing an insulating film having an etching rate different from that of the insulating film, and forming a polycrystalline silicon film on the insulating film; (E) leaving the polycrystalline silicon film only on the side surfaces of the gate electrode by anisotropic etching; Provide a side wall with ~,
a step of removing the polycrystalline silicon film from other portions, etching the insulating film by wet etching (C) (D) (B) (F) using the sidewalls as a mask to remove the insulating film from areas other than the sidewalls; removing step, <G) implanting impurity ions using the gate electrode including the sidewalls and the field insulating film as a mask to form a high concentration diffusion layer of an opposite conductivity type connected to the low concentration diffusion layer in the element formation region; It consists of the steps of:

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIGS. 1A to 1F are cross-sectional views of a semiconductor chip shown in order of steps for explaining a first embodiment of the present invention.

First, as shown in FIG. 1(a), a p-type silicon substrate 1
A channel stopper 2 of a p-type impurity diffusion layer and a field oxide film 3 are selectively formed on the surface of the wafer to define an element formation region. Next, the surface of the element formation region is thermally oxidized to form a thin oxide film (gate oxide film) 4a with a thickness of 30 nm.
After depositing a polycrystalline silicon film with n-type impurities diffused over the entire surface, a gate electrode 5 is selectively formed using photolithography technology and a dry etching method, and the surface of this gate electrode 5 and element formation are performed using a thermal oxidation method. A thin oxide film 4b with a thickness of 20 nm is formed on the surface of the region. Next, ions are implanted at a dose of about I x 10 "cry" to form an n- type diffusion layer 6.

Next, as shown in FIG. 1(b), a silicon oxide film 7 is deposited to a thickness of 0.1 μm over the entire surface by the CVD method, and a polycrystalline silicon film 8 is deposited to a thickness of 0.1 μm on top of the silicon oxide film 7 by the CVD method.
Deposited to a thickness of .

Next, as shown in FIG. 1(c), by anisotropic etching, the polycrystalline silicon film 8 is left only on the side surfaces of the gate electrode 5, and the other portions of the polycrystalline silicon film 8 are removed. At this time, the surface of the silicon oxide film 7 immediately below the polycrystalline silicon film 8 is also slightly etched, but there is no problem.

Next, as shown in FIG. 1(d), the silicon oxide film 7 is removed by wet etching using buffered hydrofluoric acid. At this time, since the polycrystalline silicon film 8 remaining on the side surface of the gate electrode 5 is not etched, the width of the side wall including the silicon oxide film 7 is sufficiently aligned. Further, during wet etching, a thin oxide film 4b is formed on the upper surface of the genit electrode 5 and the n-type diffusion layer 6 by utilizing the difference in etching rate between the oxide film 4b formed by thermal oxidation method and the silicon oxide film 7 formed by CVD method. It is desirable to leave it. Next, an n+ type scattering layer 9 is formed by ion-implanting arsenic.

Next, as shown in FIG. 1(c), the polycrystalline silicon M8 remaining on the side surfaces of the gate electrode 5 is oxidized at about 900° C. to form an oxide film 10. At this time, the active layer and the indentation of the n+ type scattering layer are also performed at the same time.

Next, as shown in FIG. 1(f), an interlayer insulating film 11 is deposited over the entire surface to form contact openings, and an aluminum film is deposited on the surface including the openings and selectively etched. A wiring 12 is formed which is connected to the multilayer scattering layer and extends over the interlayer insulation IPA. Further, at this time, in order to reduce the level difference on the side wall of the gate electrode 5, it is more effective to lightly etch the oxide film 10 by wet etching.

Furthermore, since the oxide film 4b is also etched at the same time, n+
It is preferable to re-oxidize the scattering layer to form an oxide film of about 20 nm. FIG. 2 is a cross-sectional view of a semiconductor chip showing a second embodiment of the present invention.

As shown in the figure, after going through the same steps as in the first embodiment described in FIGS. Then, a titanium film is deposited on the entire surface by sputtering. Next, 600℃
A titanium silicide film 1 is formed in a self-aligned manner on the surface of the gate electrode 5 and the surface of the n+ type scattering layer 9.
After forming No. 3, the unreacted titanium film is removed. Thereafter, a semiconductor device is constructed through the same steps as in the first embodiment.

Here, in FIG. 1(d) of the first embodiment, it is desirable to leave a thin layer of oxide M4b on the gate electrode 5 and the n+ type scattering layer 9, but in the second embodiment, the oxide film 4b It is not necessary to leave the titanium silicide film 13, and then arsenic ions may be implanted to form the n'' diffusion layer 9.

〔Effect of the invention〕

As explained above, the present invention removes the insulating film on the element formation region other than the side surface of the gate electrode by wet etching in the final stage of the conventional reactive ion etching in forming the sidewalls. Source/drain diffusion layers with low leakage current can be formed without damaging the surface of the region.

Furthermore, in the wet etching, since the present invention uses a polycrystalline silicon film having a lower etching rate than the insulating film on the side surface of the gate electrode, it is necessary to control the thickness of the insulating film located below the polycrystalline silicon film. This has the effect that the width of the sidewall can be formed with high accuracy, the characteristics of the MOSFET can be sufficiently controlled, and a method of manufacturing a semiconductor device with high degree of integration and high reliability can be realized.

[Brief explanation of drawings]

FIGS. 1(a) to (f) are cross-sectional views of a semiconductor chip shown in order of steps for explaining a first embodiment of the present invention, and FIG. 2 is a cross-sectional view for explaining a second embodiment of the present invention. FIG. 2 is a cross-sectional view of a semiconductor chip of FIG. 1...p-type silicon substrate, 2...channel stopper,
3...Field oxide film, 4a...Gate oxide film,
4b...1 oxide film, 5...gate electrode, 6...n
- type diffusion layer, 7... silicon oxide film, 8... polycrystalline silicon film, 9... n+ type scattering layer 10... oxide film, 11... interlayer insulating film, 12... Wiring, 13...Titanium silicide film. Agent Patent Attorney Uchihara Uchihara

Claims (1)

[Claims] (A) selectively providing a field insulating film for element isolation on the main surface of a semiconductor substrate of one conductivity type to demarcate an element formation region;
forming a gate insulating film on the surface of the element formation region; (B) depositing a polycrystalline silicon film on the surface including the gate insulating film and selectively etching it to form a gate electrode; a step of thermally oxidizing the surface to form an oxide film; (c) using the gate electrode and the field insulating film as masks, ion-implanting low concentration impurities to form a low concentration diffusion layer of the opposite conductivity type in the element formation region; (D) depositing an insulating film having an etching rate different from the oxide film on the surface including the gate electrode, and forming a polycrystalline silicon film on the insulating film; (E) anisotropic etching. (F) etching the insulating film by wet etching using the sidewall as a mask; (F) etching the insulating film by wet etching using the sidewall as a mask; (G) implanting impurity ions using the gate electrode including the side walls and the field insulating film as a mask, and connecting the element forming region to the low concentration diffusion layer; A method for manufacturing a semiconductor device, comprising the steps of: forming a highly doped diffusion layer of opposite conductivity type.