JP2887902B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of forming a source / drain diffusion layer of a MOS device.

2. Description of the Related Art Large-capacity, high-density integrated circuits that continue to evolve at remarkable speeds are required to be further miniaturized as the degree of integration is increased.

[0003] It is an object of the present invention to satisfy the needs of such fields.

[0004]

2. Description of the Related Art FIG. 4 is an explanatory view of a conventional example. In the figure, 26 is a silicon (Si) substrate, 27 is a field silicon dioxide (SiO ₂ ) film, 28 is a gate SiO ₂ film, 29 is a low concentration source / drain diffusion layer, 30 is a gate electrode, and 31 is a side wall Si.
An O ₂ film, 32 is a source / drain diffusion layer, 33 is an SiO ₂ film, and 34 is a source / drain electrode.

A conventional representative LDD (Light Doped Drai)
n) FIG. 4 shows the structure of the MOS transistor. Conventional LD
In the DMOS transistor, the source / drain layers 32 were formed by directly implanting ions into the Si substrate 26 to dope semiconductor impurities and then diffusing the impurities into the Si substrate 26 by a subsequent heat treatment.

However, in this method, when the source / drain diffusion layer 32 is shallowed in accordance with further miniaturization of the element, the leakage of the junction due to damage to the Si substrate 26 such as generation of crystal defects during ion implantation. Was a problem.

Further, the openings of the electrode contact portions of the source / drain layers 32 need to be aligned with respect to the gate electrode 30 and the field oxide film 27, and the accuracy thereof has been a problem.

[0008]

Therefore, miniaturization has been difficult due to the two problems of shallower source / drain layers and the limitation of the alignment accuracy of the current lithography technology.

The present invention has been made in view of the above points, and is provided for the purpose of solving these problems and realizing miniaturization of a MOS transistor.

[0010]

FIG. 1 is a diagram illustrating the principle of the present invention. In the figure, 1 is a semiconductor substrate, 2 is a first conductive layer, 3 is an opening, 4 is an oxidation-resistant film, 5 is a low concentration source / drain diffusion layer, 6 is an ion-resistant film, 7 is an impurity, 8 Is an insulating film, 9 is a source / drain diffusion layer, 10 is a gate insulating film, and 11 is a second conductive layer (gate electrode).

In order to solve the above-mentioned problems of the prior art, the following steps are performed. That is, the first problem is solved by introducing a semiconductor impurity into a first conductive layer such as a poly-Si film without using an ion implantation method and utilizing an oxidation-resistant film to form a shallow source-drain diffusion. Form a layer.

In order to solve the second problem, a gate oxide film or a gate electrode is formed by self-alignment using an oxidation-resistant film and a first conductive layer. That is, an object of the present invention is to form a shallow source / drain diffusion layer and a gate electrode by self-alignment.
1A, a first conductive layer 2 containing an impurity of the opposite conductivity type is formed on a semiconductor substrate 1 of one conductivity type, and the first conductive layer 2 is etched to form the semiconductor substrate. 1 and a step of forming an opening 3 reaching the surface layer, and as shown in FIG.
Heat-treating the semiconductor substrate 1 to form a low-concentration source / drain diffusion layer 5 in the semiconductor substrate 1; and, as shown in FIG. The oxidation-resistant coating 4 is formed only on the bottom of the opening 3.
1D, a part of the surface of the first conductive layer 2 is isotropically etched to form the first conductive layer 2 and the oxidation resistant coating 4 as shown in FIG. 1E, a step of providing a gap therebetween, and as shown in FIG.
As shown in (f), the ion-resistant coating 6 is anisotropically etched to bury the ion-resistant coating 6 only in the opening 3, and then, using the ion-resistant coating 6 as a mask,
A step of implanting an impurity 7 of a conductivity type opposite to that of the semiconductor substrate 1 into the first conductive layer 2 by ion implantation, and FIG.
As shown in (g), after the ionic resistant coating 6 on the semiconductor substrate 1 is removed, the surfaces of the semiconductor substrate 1 and the first conductive layer 2 are thermally oxidized to form an insulating film 8. At the same time, a step of diffusing impurities of a conductivity type opposite to that of the semiconductor substrate 1 from the first conductive layer 2 to form a source / drain diffusion layer 9 having a higher concentration than the source / drain diffusion layer 5; As shown in (h), after removing the oxidation-resistant film 4, a gate insulating film 10 is formed in the opening 3 of the semiconductor substrate 1, and then a second conductive film is formed on the semiconductor substrate 1. Forming a layer 11 and patterning the second conductive layer 11 to form a gate electrode in a region including the opening 3.

[0013]

As described above, the use of the manufacturing method of the present invention has the following advantages as compared with the conventional LDDMOS transistor manufacturing method.

Since the formation of the source / drain electrodes and the formation of the window of the gate electrode are formed by self-alignment, the problem of the alignment accuracy of the photolithography technique is eliminated.
Further miniaturization becomes possible.

In order to introduce semiconductor impurities into the semiconductor substrate through the first conductive layer, the problem that the surface of the semiconductor substrate is hit by implanted ions and crystal defects occur to cause junction leakage is eliminated. Source / drain layers can be formed.

[0016]

2 and 3 are schematic cross-sectional views showing the steps of an embodiment of the present invention. In the figure, 12 is a Si substrate, 13 is a field SiO ₂ film, 14 is a first poly-Si film, 15 is an opening, and 16 is Si ₃ N
₄ film, 17 is low concentration source / drain diffusion layer, 18 is resist film, 19 is As ⁺ , 20 is SiO ₂ film, 21 is high concentration source / drain diffusion layer, 22 is gate SiO ₂ film, 23 is source / drain diffusion layer Drain contact extraction electrode, 24 is the gate electrode, 25 is the source electrode
It is a drain electrode.

[0017] Using the Si substrate 12 of p-type as shown in FIG. 2 (a), about a SiO ₂ film of about 200Å not shown Si substrate 12 over the entire surface
After an Si ₃ N ₄ film by CVD of 1,500Å was grown in this order, leaving the active element formation region, a the Si ₃ N ₄ film of other regions is removed by etching with a resist patterning, a field SiO ₂ film 13 thermally oxidized Grows to a thickness of about 5,000 mm. Subsequently, the Si ₃ N ₄ film was removed with boiling phosphoric acid, and
SiO ₂ film is removed by hydrofluoric acid control etching, and LOC
Complete the OS process.

As shown in FIG. 2B, a first poly-Si film 14 doped with phosphorus (P) is grown to a thickness of about 4,000 to 5,000 mm, and the first poly-Si film 14 is patterned by resist. Si
When an opening 15 is formed in a gate formation region corresponding to the center of the film 14, the first poly-Si film 14 becomes a source / drain contact lead-out electrode as it is.

As shown in FIG. 2C, the CV
After growing the Si ₃ N ₄ film 16 by D to a thickness of about 700 to 1,500 mm, a heat treatment is performed at 1,000 ° C. for 20 seconds to form the first poly-Si film.
Phosphorus is diffused from the film 14 into the Si substrate 12 so that
The drain layer 17 is formed.

As shown in FIG. 2D, a resist film (not shown) is formed to a thickness of about 7,000 to 8,000 よ う so that the opening 15 is completely filled.
The resist film is flattened, the resist film is anisotropically etched, and the resist film is buried only in the opening 15. Then, the Si ₃ N ₄ film 16 is subjected to anisotropic etching etching using the resist film as a mask, so that the Si ₃ N ₄ film 16 is left only on the bottom side of the opening 15. afterwards,
The resist film of the mask material is removed.

As shown in FIG. 2E, a first poly-Si film
The surface of 14 is subjected to isotropic etching for about 1,000 to 2,000 ,, and the Si ₃ N ₄ film 16 and the first poly-Si film 14 at the bottom of the opening 15 are formed.
A gap of about 1,000 to 2,000 mm is formed between them.

Subsequently, as shown in FIG. 3F, a resist film 18 is formed to a thickness of about 7,000 to 8,000 so that the opening 15 is completely filled.
It is applied to a thickness of 0 mm to flatten the surface of the resist film 18. As shown in FIG. 3G, the resist film 18 is anisotropically etched to bury the resist film 17 only in the opening 15. Then, using the resist film 18 as a mask, arsenic ions (As ⁺ ) 19 are ion-implanted into the first poly-Si film 14 to form a high-concentration source / drain layer at an acceleration voltage of 35 keV and a dose of 4 × 10 ¹⁵ / After the implantation under the condition of cm ² , the resist film 18 is removed.

As shown in FIG. 3H, using the Si ₃ N ₄ film 16 at the bottom of the opening 15 as a mask, the Si substrate 12 and the first poly
The thermal oxidation of the Si film 14 is performed, and an SiO ₂ film 20 is formed to a thickness of about 1,000 to 2,000 mm on the surface of the first poly-Si film 14 and on the surface of the Si substrate 12 which is partially exposed. As a result, the first poly-Si film 14 is completely insulated from the gate forming portion and becomes the source / drain contact lead-out electrode 23.

At the same time, the arsenic doped in the first poly-Si film 14 is
19 diffuses into the Si substrate 12 to form a high concentration source / drain diffusion layer 21. After this, the Si ₃ N ₄
The film 16 is removed by etching with a phosphoric acid boiler.

As shown in FIG. 3I, a gate SiO ₂ film 22 is formed on the bottom of the opening 15 by thermal oxidation to a thickness of about 200 °. Then, the second poly-Si film doped with phosphorus is
A gate electrode 24 is formed by growing the substrate to a thickness of about 2,000 to 4,000 mm on the substrate 12 and performing resist patterning.

Subsequently, openings for source / drain electrode contacts are formed in the SiO ₂ film 20, and an aluminum (Al) film is
The LDD-MOS transistor is completed by forming a source / drain electrode 25 by sputtering deposition to a thickness of 000 mm and resist patterning.

[0027]

As described above, according to the present invention,
Since the formation of the source / drain electrodes and the formation of the window of the gate electrode are performed in a self-alignment manner, the problem of alignment accuracy is eliminated, and further miniaturization becomes possible. In addition, since the semiconductor impurity is introduced into the semiconductor substrate through the first conductive layer, the problem that the surface of the semiconductor substrate is hit by implanted ions and crystal defects occur to cause junction leakage is eliminated. -A drain layer can be formed.

As a result, the manufacturing method of the present invention greatly contributes to the development of highly integrated and ultra-miniaturized semiconductor integrated circuits.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating the principle of the present invention,

FIG. 2 is a schematic sectional view of a process in an embodiment of the present invention (part 1).

FIG. 3 is a schematic cross-sectional view of an embodiment of the present invention in the order of steps (part 2).

FIG. 4 is an explanatory view of a conventional example.

[Explanation of symbols]

REFERENCE SIGNS LIST 1 semiconductor substrate 2 first conductive layer 3 opening 4 oxidation resistant film 5 low concentration source / drain diffusion layer 6 ion resistant coating 7 impurity 8 insulating film 9 source / drain diffusion layer 10 gate insulating film 11 second conductivity Layer (gate electrode) 12 Si substrate 13 Field SiO ₂ film 14 First poly Si film 15 Opening 16 Si ₃ N ₄ film 17 Low concentration source / drain diffusion layer 18 Resist film 19 As ⁺ 20 SiO ₂ film 21 High concentration Source / drain diffusion layer 22 Gate SiO ₂ film 23 Source / drain contact extraction electrode 24 Gate electrode 25 Source / drain electrode

Claims (1)

(57) [Claims] A first conductive layer (2) containing an impurity of the opposite conductivity type is formed on a semiconductor substrate (1) of one conductivity type.
Forming an opening (3) reaching the surface layer of the semiconductor substrate (1) by etching the conductive layer (2) of the semiconductor substrate (1);
(1) An oxidation resistant film (4) is formed on the semiconductor substrate (1).
Forming a low-concentration source / drain diffusion layer (5) in the semiconductor substrate (1) by performing a heat treatment of the above; and anisotropically etching the oxidation resistant coating (4) to form the opening ( 3) leaving the oxidation-resistant film (4) only on the bottom of the first conductive layer (2), and partially isotropically etching the surface of the first conductive layer (2) to form the first conductive layer (2). ) And providing a gap between the oxidation-resistant coating (4) and applying an ion-resistant coating (6) on the semiconductor substrate (1) by filling the opening (3). The ion resistant coating (6) is anisotropically etched to bury the ion resistant coating (6) only in the opening (3), followed by the ion resistant coating (6).
Using the first conductive layer as a mask by ion implantation.
(2) implanting an impurity (7) of the opposite conductivity type to the semiconductor substrate (1) into the semiconductor substrate (1); removing the ion-resistant coating (6) on the semiconductor substrate (1); 1) and the surface of the first conductive layer (2) are thermally oxidized to form an insulating film (8), and at the same time, the first conductive layer (2) has a conductivity type opposite to that of the semiconductor substrate (1). Source / drain diffusion layer (5)
Forming a higher concentration source / drain diffusion layer (9); removing the oxidation resistant coating (4);
A gate insulating film (10) is formed in the first opening (3) of (1), and a second conductive layer (11) is formed on the semiconductor substrate (1). Patterning the conductive layer (11) of
Forming a gate electrode in a region including (3).