JPH04139834A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To enable the spread of low concentration source-drain regions in the lateral direction to be controlled by a method wherein an ion-implantation step is performed to form high concentration source-drain region using a gate sidewall layer as a mask and after removing the gate sidewall layer, another ion-implantation step is performed to form low concentration source-drain region. CONSTITUTION:A gate oxide film 3 is formed on the surface of the element formation region of a substrate 1 and then a gate electrode 4 is selectively provided on the film 3. Next, high concentration impurities of opposite conductivity type are ion-implanted in the element formation region using the gate electrode and gate sidewall layer 5 as masks so as to form high concentration source-drain region. Furthermore, after removing the gate sidewall layer 5, the inverse conductivity type low concentration impurities are ion-implanted in the element formation region using the gate electrode 4 as a mask so as to form the low concentration source-drain region 8 connecting to the high concentration region 7. Through these procedures, the spread in the lateral direction from the low concentration source-drain region to the part below the gate electrode 4 can be controlled.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for manufacturing a semiconductor device, and in particular to a method for manufacturing a semiconductor device.
(Lightly doped drain)M
The present invention relates to a method of manufacturing a semiconductor device having an OSFET.

[Conventional technology]

In order to obtain high reliability of miniaturized MO3FET, Fig. 2 (
1A to 1C are cross-sectional views of a semiconductor chip shown in the order of steps for explaining a conventional method of manufacturing a semiconductor device.

As shown in FIG. 2(a), a silicon oxide film 2 is selectively provided on the entire surface of a p-type silicon substrate 1 to define an element formation region, and the surface of the element formation region is thermally oxidized to form a gate oxide film. 3
form. Next, a polycrystalline silicon film is deposited on the gate oxide film 3 and selectively etched to form a gate electrode 4. Next, phosphorus ions are implanted using the gate electrode 4 and the silicon oxide film 2 as masks to form n-type low concentration source/drain regions 8.

Next, as shown in FIG. 2(b), a silicon oxide film is deposited on the surface including the gate electrode 4 and etched back.
A gate sidewall layer 5 is formed leaving the silicon oxide film only on the side surfaces of the electrode 4. Next, thermal oxidation is applied to the element formation region and the gate electrode iFf! A silicon oxide film 6 is provided on 4. Next, arsenic ions are implanted using the gate electrode 4, gate sidewall layer 5, and silicon oxide film 2 as masks to form n-type high concentration source/drain regions 7.

Next, as shown in FIG. 2(c), a PSG film 9 is deposited on the entire surface to form contact holes, and a metal film is deposited on the surface including the contact holes and selectively etched to form a high concentration source. A metal wiring 10 connected to the drain region 7 and extending over the PSG film 9 is formed to constitute an n-channel MO8FET.

[Problem to be solved by the invention]

This conventional semiconductor device manufacturing method involves forming lightly doped source/drain regions aligned with the gate electrode, forming gate sidewall layers on the sides of the gate electrode, and forming highly doped source/drain regions aligned with the gate sidewall layers. To form the drain region,
The effective channel length of a MOSFET is determined by the dimensions of the gate electrode and the lateral inward slope of impurities due to a heat treatment process after ion implantation to form lightly doped source/drain regions. Further, the lateral inward slope of the lightly doped source/drain region causes the gate electrode and the lightly doped source/train region to overlap, resulting in an increase in gate electrode capacitance. Therefore, the fact that the lateral slope due to thermal diffusion of impurities is a factor that determines the effective channel length results in the gate electrode dimensions being
Must be large for the desired effective channel length,
There was a problem that led to a decrease in the degree of integration. Furthermore, an increase in gate electrode capacitance causes a problem in that the transient response characteristics of the transistor deteriorate, resulting in a reduction in signal processing speed.

[Means to solve the problem]

The method for manufacturing a semiconductor device of the present invention includes the steps of: - selectively providing an insulating film on a conductive type semiconductor substrate to define an element formation region, and forming a gate oxide film on the surface of the element formation region; selectively providing a gate electrode on the gate electrode and providing a gate sidewall layer on the side surface of the gate electrode;
・A step of ion-implanting high-concentration impurities of opposite conductivity type into the element formation region using the electrode and gate sidewall layer as a mask to form a high-concentration source/drain region, and a step of removing the gate sidewall layer and using the gate electrode as a mask. The method includes a step of ion-implanting a low concentration impurity of a reverse conductivity type into the element formation region to form a low concentration source/train region connected to the high concentration source/drain region.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIGS. 1(a) to 1(c) are cross-sectional views of a semiconductor chip shown in the order of steps for explaining an embodiment of the present invention.

First, as shown in FIG. 1(a), a p-type silicon substrate 1
Silicon substrate 1 is thermally oxidized using a silicon nitride film selectively provided on one main surface as an oxidation-resistant mask, and silicon oxide film 2 is formed to a thickness of about 0.5 μm to define device formation regions.

Next, the silicon nitride film used as an oxidation-resistant mask was
After removal with phosphoric acid heated to about .degree. C., the surface of the element formation region is thermally oxidized to form a gate oxide film 3 with a thickness of about 20 nm. Next, a polycrystalline silicon film in which phosphorus is diffused is deposited on the surface including the gate oxide film 3 to a thickness of 0.148 m by the CVD method, and selectively etched to form the gate electrode 4.
form. Next, a silicon oxide film is deposited on the surface including the gate electrode 4 to a thickness of about 0.2 μm by CVD. The silicon oxide film deposited in this manner is applied to the gate electrode 4.
Since the film is deposited in a direction perpendicular to the side surface of the gate electrode 4, that is, in a direction horizontal to the surface of the silicon substrate 1, the thickness of the film in the direction perpendicular to the surface of the silicon substrate 1 on the side surface of the gate electrode 4 is the same as that of the gate electrode 4. The thickness is equal to or greater than the film thickness. Therefore, in the case of this example, the thickness of the silicon oxide film deposited by the CVD method on the side surface of the gate electrode is approximately 0.4 to 0.0.
It becomes 45 μm. Next, the entire surface is etched back by anisotropic etching to form the gate sidewall layer 5, leaving the silicon oxide film only on the side surfaces of the electrodes 1 to 4. During the anisotropic etching for forming the gate sidewall layer 5, the goo I/oxide film 3 in the element forming region is also etched away at the same time. Next, a thermal oxide film 6 with a thickness of 40 nm is formed on the surface of the element formation region as a buffer film for the silicon substrate when ion implantation is performed.

At this time, the surface of the gate electrode 4 is also oxidized and the silicon oxide film 6
are formed simultaneously. Next, arsenic ions are implanted at an acceleration energy of 70 keV, a dose of 5×], and 0.15 cm to 2 to form n-type high concentration source/drain regions 7.

Next, as shown in 11'2I(b), the gate sidewall layer 5 is removed using a diluted hydrogen fluoride aqueous solution. next,
A silicon oxide film 6a is formed to a thickness of about 40 nm by thermal oxidation as a buffer film during ion implantation. The thermal oxidation at this time activates the previously implanted arsenic ions. Next, using the gate electrode 4 and the silicon oxide film 2 as masks, phosphorus ions are accelerated at an energy of 40 keV and at a dose of 3.
N-type low concentration source/drain regions 8 are formed by ion implantation at a size of x1-013 cm-2.

Next, as shown in FIG. 1(c), silicon glass M containing phosphorus (hereinafter referred to as PSG film) is coated on the entire surface by CVD method.
9 is deposited, the PSG film 9 and the silicon oxide film 6a on the high concentration source/drain region 7 are selectively and sequentially etched to form contact holes, and the surfaces including the contacts 1 to the holes are coated with metal by sputtering or the like. A film is deposited and selectively etched to form a metal interconnect 10 connecting to the heavily doped source train region 7 to form an n-channel MO3FE1.

〔Effect of the invention〕

As explained above, in the present invention, ions are first implanted to form highly doped source and drain regions using the gate sidewall layer as a mask, followed by annealing, and then the gate sidewall layer is removed to form a lightly doped source and drain region. Since ion implantation to form the source/train region is performed and annealing is performed, the only heat treatment for the low concentration source/drain region is the annealing process after ion implantation. Self-storage can be controlled independently, and the effective channel length of MO3 type FET is
This is determined by the dimensions of the gate electrode, and it is also possible to reduce the overlap between the gate electrode and the source/drain regions, thereby improving the performance of the MO8 type FET.

[Brief explanation of drawings]

FIGS. 1(a) to (c) are cross-sectional views of a semiconductor chip shown in the order of steps for explaining one embodiment of the present invention, and FIG.
1A to 1C are cross-sectional views of a semiconductor chip shown in the order of steps for explaining a conventional method of manufacturing a semiconductor device. 1...p-type silicon substrate, 2...silicon oxide film, 3
...Gate oxide film, 4...Gate electrode, 5...Gate side wall layer, 6, 6a...Silicon oxide film, 7...High concentration source/drain region, 8...Low concentration source -Drain region, 9...PSG film, 10...metal wiring. (tJl!A ffP4°1 Susumu Uchihara 3z C1

Claims (1)

[Claims] A step of selectively providing an insulating film on a semiconductor substrate of one conductivity type to divide an element formation region and forming a gate oxide film on the surface of the element formation region; selectively forming a gate electrode on the gate oxide film; a step of providing a gate sidewall layer on a side surface of the gate electrode; and a step of ion-implanting a high concentration impurity of a reverse conductivity type into the element formation region using the gate electrode and the gate sidewall layer as a mask to form a high concentration source/drain region. , after removing the gate sidewall layer, using the gate electrode as a mask, ion-implanting a low concentration impurity of a reverse conductivity type into the element formation region to form a low concentration source/drain region connected to the high concentration source/drain region; A method for manufacturing a semiconductor device, comprising: