JPS6156448A - Manufacture of complementary semiconductor device - Google Patents

Abstract

PURPOSE:To prevent the decrease in withstand voltage of an n-channel transistor and the variation or decrease in threshold voltage of a p-channel transistor by a method wherein a film to be oxidized is formed under a film or by another method at the time of forming the wall by leaving a film on the side surface of a gate electrode. CONSTITUTION:A semiconductor layer 102 of the second conductivity type is selectively formed in a semiconductor substrate 101 of the first conductivity type, and element- isolating regions 103 are formed. Insulation films 10 are formed on the surfaces of element regions, and the gate electrodes 106 and 107 are selectively formed thereon, respectively. Next, after an impurity of the first conductivity type is doped to each element region with the mask of each of the gate electrodes 106 and 107 and the element-isolating regions 103, a film 111 to be oxidized and a film 112 are successively deposited over the whole surface, and the film 112 is selectively left on the side surfaces of the gate electrodes 106 and 107. Then, the impurity of the first conductivity type is doped to each element region with the mask of the gate electrodes 106 and 107 and the element-isolating regions 103. Thereafter, the remaining film 114 is removed, and the film 111 to be oxidized is changed into an oxide film 118; then, an impurity of the second conductivity type is selectively doped to the element regions of the first conductivity type.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method for manufacturing a complementary semiconductor device, and in particular to a method for manufacturing a complementary semiconductor device.
The present invention relates to a method of manufacturing a complementary semiconductor device that improves the process of forming channel, source and drain regions of a p-channel transistor.

[Technical background of the invention]

As is well known, a complementary MO8 semiconductor device (hereinafter abbreviated as CMO8) has an n-channel transistor and an n-channel transistor formed on the same substrate. In recent years, miniaturization technology has been rapidly established for OMO8, and along with this, higher performance and higher integration have been achieved. in particular,
0MO8 with a channel length of 1 μm or less is being developed.

In such a 1m MO8, the electric field between the source and drain regions (especially the electric field between the source and drain regions in an n-channel transistor) becomes extremely large, and problems arise due to electrons and holes generated in this high electric field. Occur. For example, there is a fluctuation (increase) in the threshold voltage due to electrons injected into the gate oxide film, and an abnormal increase in substrate current due to holes injected into the semiconductor substrate.

For this reason, a method for manufacturing an OMO8 having a structure in which the high electric field between the source and drain back regions is relaxed has been proposed. This will be explained below with reference to FIGS. 2(a) to (Q).

First, a p-type semiconductor layer (p-well) 2 is selectively formed on an n-type silicon substrate 1 with crystal orientation (100). Subsequently, after forming a field oxide film 3 as an element isolation region on the substrate 1 and the p-well 2, an island-like element f of the substrate 1 and the p-well 2 separated by the field oxide film 3 is formed.
An oxide film is formed in the iji region. Subsequently, a phosphorus-doped polycrystalline silicon film, for example, is deposited on the entire surface and patterned to form gate electrodes 4 on the oxide film in each element region.
5 is formed, and the oxide film is selectively etched and removed using the gate electrode 4.5 as a mask to form a gate oxide film 6.7.
(as shown in FIG. 1(a)).

Next, after forming a resist pattern 8 covering the element region side of the substrate 1 by photolithography, the resist pattern 8 is
Using the gate electrode 4 and the field oxide film 3 as a mask, an n-type impurity, for example phosphorus, is applied at an acceleration voltage of 20 keV and a dose of 1 x 1013 cm4. hot water. 1. (Layers 91 and 92 are formed (as shown in FIG. 3B).Then, the resist pattern 8 is removed and the p-well 2 is formed again by photolithography.
After forming the resist pattern 10 covering the side, the resist pattern 10, the gate electrode 5 and the field oxide film 3 are formed.
Using as a mask, an n-type impurity, for example boron, is
Boron ion implantations W 111 and 112 are formed by ion implantation under the conditions of 0 keV and a dose of 1×10 1 SCa+' (as shown in FIG. 3(c)).

Next, after removing the resist pattern 10, a CVD-8i 02 film 12 is deposited on the entire surface to a thickness of, for example, 400 cm, and then heat treated for 30 minutes in a nitrogen atmosphere at, for example, 900°C. As a result, the phosphorus ion implantation layers 91 and 92 are activated and the low concentration n
− type diffusion layers 131 and 132 are formed, and the boron ion implantation layers 111 and 112 are activated to form p+ type source and drain regions 14 and 15. Subsequently, the CVD-8i○2 film 12 is removed by reactive ion etching (RTE) to a thickness similar to that of the CVD-8i○2 film 12, and the side surfaces of the gate electrode 4 and the gate oxide film 6 and the gate electrode are removed. 5 and the side surfaces of the gate oxide film 7, the SiO2 film 12 is left on the side surfaces of the wall body 1.
6 (as shown in FIG. 6(e)).

Next, a resist pattern (not shown) covering the element region side of the substrate 1 is again formed by photolithography, and then an n-type impurity, For example, arsenic is accelerated at a voltage of 40 keV.

Ion implantation is performed at a dose of i3X 101San'. Thereafter, the resist pattern is removed and heat treatment is performed in a nitrogen atmosphere at 900° C. to activate the arsenic ion implantation layer and form a high concentration n+ type resistive diffusion layer 171172. As a result, a source region 18 consisting of the n- type diffusion layer 131 and the n+ type resistive diffusion layer 171 is formed, and a drain region 19 consisting of the n- type diffusion layer 132 and the n+ type dispersion layer 172 is formed. Ru. Next, Si
02 film 20 is deposited, a contact hole 21 is opened, an upper film 20 is evaporated on the SiO2 film 20, and this is patterned to form a 2 wiring to be connected to the n-type source region 18 through the contact hole 21. 22. Aλ wiring 23 commonly connected to the drains [15, 19 through contact holes 21 and 21, and A°C wiring 2 connected to the p++ source region 14 through the contact hole.
4 to produce 0MO8 (as shown in FIG. 4(Q)).

According to the conventional method described above, an n-channel transistor has a lightly doped n-type diffusion layer 131 located near the gate electrode 4 and a highly doped n+ type diffused layer 131 located away from the gate electrode 4. 171, a low concentration n-type diffusion layer 132 located near the gate electrode 4, and a high concentration n+ type scattering layer 17 in a portion far from the gate electrode 4.
Since the drain region 19 consisting of 2 is formed, a so-called LDD structure is formed, and the generation of the high electric field between the source and drain regions described above can be suppressed.

[Problems with background technology]

However, the conventional method described above has various problems listed below.

(a) In the process of FIG. 2(d) above, CVD-8i
When the O2 film 12 is etched to the same thickness using the RIE method to form the wall body 16 on the side surface of the gate electrode 4.5, the field oxide film 3 is overetched and thinned. As a result, as shown in FIG.
The distance between the + layer 25 and the n+ layer 25 is reduced from the length L before the RIE process to the length 1e, resulting in a decrease in breakdown voltage.

(b) Since the wall body 16 is formed by the RIE method, the surfaces of the silicon substrate 1 and the p-well 2 where the source and drain regions are formed are damaged by ions during the formation, significantly deteriorating the device characteristics.

(c) When forming the gate oxide film 6.7 by selectively etching the oxide film using the gate electrode 4.5 as a mask, an undercut occurs in the gate oxide film, resulting in a breakdown voltage between the gate electrode and the source and drain regions. decreases, causing problems in terms of reliability. f (d) In the above method, the source and drain fa of the n-channel transistor
[In order to avoid offset of 14 and 15, the source and drain regions 14.15 are formed before forming the wall 16 on the side surface of the gate electrode 4.5. For this reason, p+
Even after forming the type source and drain regions 14.15, high temperature heat treatment is performed to form the n2 type diffusion layers 171 and 172, so the source and drain regions are re-diffused and the junction depth increases. , the short channel effect of the n-channel transistor becomes significant, leading to fluctuations in threshold voltage, etc. Note that in order to prevent re-diffusion of the p+ type source and drain regions 14 and 15, cvo-s
Another possible method is to remove the +02 wall body 16 and then ion-implant p-type impurities to form p+-type source and drain regions. However, with the darning method, the CV
When removing the wall 16 of D-8i02, the field oxide film 3 is etched and thinned, causing the same problem as in (a) above.

[Purpose of the invention]

, the present invention eliminates the drop in breakdown voltage between n''-n+ type high concentration impurity layers, the drop in breakdown voltage between the gate electrode and the source and drain regions, and the damage caused by ions on the surface of the semiconductor substrate, while the n-channel transistor has an LDD structure. And then n
It is an object of the present invention to provide a method for manufacturing a high-performance, highly reliable complementary semiconductor device that prevents variations or decreases in the threshold voltage of a channel transistor.

[Summary of the invention]

The present invention includes a step of selectively forming a semiconductor layer of a conductivity type opposite to that of the substrate on a semiconductor substrate of one conductivity type, a step of forming an element isolation region between the semiconductor substrate and the semiconductor layer, and a step of forming an element isolation region between the semiconductor substrate and the semiconductor layer. forming an insulating film on the surfaces of the island-shaped element regions of the semiconductor substrate and the semiconductor layer separated by the ll1i region; and selectively forming gate electrodes on the first insulating films on the surfaces of each of the element regions. The process and each gate WN! a step of doping impurities of a first conductivity type into each of the device regions using the device isolation region as a mask; a step of sequentially depositing an oxidizable film and a coating on the entire surface; and a step of selectively applying the coating to the side surface of each of the gate electrodes. a step of doping impurities of a first conductivity type into each element region using the remaining film, each gate electrode, and an element isolation region as a mask; a step of removing the remaining film; It is characterized by comprising a step of converting the film into an oxide film, and a step of selectively doping an impurity of a second conductivity type into an element region of a conductivity type opposite to that of the impurity using at least a gate electrode and an element isolation region as a mask. That is.

According to the method of the present invention, the <rl-Yannel transistor has an LDD structure as described above, and also reduces the breakdown voltage between the n''-n+ type temperature concentration impurity layers, the breakdown voltage between the gate electrode and the source and drain regions, and Furthermore, it is possible to obtain a high-performance, highly reliable complementary semiconductor device in which damage caused by ions on the surface of a semiconductor substrate is eliminated, and variation or decrease in the threshold voltage of a p-channel transistor is prevented.

[Embodiments of the invention]

Hereinafter, Examples 1 (a) to (h) of the present invention will be described as 11.
This will be explained in detail with reference to the following.

First, a p-well 102 is selectively formed on an n-type silicon substrate 101 with crystal orientation (100) by thermal diffusion, and then a field as an element isolation region is formed on the substrate 101 and the p-well 102 by selective oxidation. An oxide film 103 was formed. Subsequently, after forming an oxide layer 1104 on the island-shaped element region of the substrate 101 and the p-well 102 separated by the field oxidation layer 1i1103, for example, phosphorus-doped polycrystalline silicon 1105 is deposited on the entire surface (see FIG. 1(a)). (Illustrated).

Next, the polycrystalline silicon film 105 is patterned to form a gate electrode 10 on the oxide 11104 of each element region.
6. After forming each gate electrode 107, each gate electrode 106 is
．． Using 107 as a mask, oxidation film 1104 was selectively etched away to form gate oxide films 108 and 109. Next, using each gate electrode 106, 107 and field oxide film 103 as a mask, n-type impurities, such as phosphorus, are ion-implanted at an acceleration voltage of 20 keV and a dose of 1×10 13 α to perform low-concentration phosphorus ion implantation 1
Layers 1101, 1102, 1103, and 1104 were formed (as shown in the same figure (b)). Continue to coat the entire surface with a thickness of, for example, 3
00 polycrystalline silicon 11111, and a thickness of e.g. 4
After sequentially depositing the CVD-8i02 films 112 of 1,000 layers, heat treatment is performed in a nitrogen atmosphere at, for example, 900° C. for 30 minutes. As a result, the phosphorus ion implantation layers 11o1 to 1104 are activated and the low concentration n-
Type diffusion layers 1131 to 1134 were formed. After that, the cVD-8i02 film 112 is etched by a reactive ion etching method (RIE method).
A wall body 114 was formed by etching and removing the SiO2 film to a thickness of about 12 mm, leaving the SiO2 film on the side surfaces of the gate electrode 106 and gate oxide film 108, and on the side surfaces of the gate electrode 107 and gate oxide film 109, respectively. 1) As shown).

Next, after forming a resist pattern (not shown) covering the element region side of the substrate 101 by photolithography, the resist pattern covers the gate electrode 106 on the p-well 102 side.
, using the wall body 114 and field oxide film 103 as masks, an n-type impurity, such as arsenic, was ion-implanted at an acceleration voltage of 40 keV and a dose of ffi 3×1Q1sα. Thereafter, the resist pattern is removed and heat treatment is performed in a nitrogen atmosphere at 900'C to activate the arsenic ion-implanted layer and form a highly concentrated n+ type scattered layer 115! , 1152 was formed. As a result, a source region 116 consisting of an n- type diffusion layer 11131 and an n+ type scattering layer 1151 is formed as shown in FIG.
A drain region 117 consisting of 1'32 and an n+ type scattering layer 1152 was formed.

Next, after removing the wall 114 as shown in FIG.
was converted to oxidation 1!1118. Subsequently, after forming a resist pattern (not shown) covering the p-well 102 side by photolithography, using the resist pattern, gate electrode 107, and field oxide film 103 as a mask,
A type impurity, for example, boron, was ion-implanted into the n-type diffusion lW1133.1134 of the substrate 101 under the conditions of an acceleration voltage of 40 keV and a dose of 1×10"car4. After this,
The resist pattern is removed, heat treatment is performed at, for example, 900''C to activate the boron ion implantation layer, and p+ type source and drain regions 119.1 are formed in the element region of the substrate 101.
20 was formed (as shown in the same figure ((J))).

Next, a 5102 film 121 is deposited on the entire surface, a contact hole 122 is opened, and an A
A Q film is deposited and patterned to connect the n-type source region 116 through the contact hole 122, the wiring 123, and the drain region 117.12.
0 and the A2 wiring 124 commonly connected through contact holes 122 and 122 and the p + type source region 11
9 and 2 wirings 125 connected through contact holes 122 are respectively formed to manufacture 0MO8 (see (h) in the same figure).
).

According to the present invention, the CVD-8i02 film 112 is etched by the RIE method, and the gate electrode 106.10 is etched.
CVD-8i 02 left on the side of wall 11
4, a polycrystalline silicon film 111 is formed under the CVO-3i02 film 112. As a result, the polycrystalline silicon film 111 acts as a stopper, so
It is possible to prevent the reduction of the field oxide film 103, and
Substrate 101 and p-well 1 by ions in RIE method
Damage to the 02 surface can be prevented and highly reliable CMOS can be obtained.

Also, using the gate electrodes 106 and 107 as a mask, oxidation 1
Gate oxide film 10 formed when etching 1104
8. The undercut at 109 is the polycrystalline silicon film 11
It is filled with an oxide film 118 that is converted by thermally oxidizing 1. As a result, the gate electrodes 106, 107 and the source,
A decrease in breakdown voltage between the drain region 116, 119, 117, and 120 can be prevented.

Furthermore, as shown in FIGS. 1(e) and 1(f), when the wall 114 is removed, the field oxide film 103 is covered with the polycrystalline silicon film 111. Can prevent film loss. As a result, as shown in FIG. 1(0), after the removal process of the wall 114, that is, after high-temperature heat treatment for forming the source and drain regions 116 and 117 of the n-channel transistor, an n-channel transistor with no offset is formed. P+ type source and drain regions 119 and 120 can be formed. Therefore, it is possible to eliminate re-diffusion of the p+ type source and drain regions 119 and 120, prevent fluctuations in threshold voltage due to deepening of the junction depth, and obtain a high-performance 0MO8.

In the above embodiment, a polycrystalline silicon film is used as the oxidizable film, but an amorphous silicon film or a metal silicon film may be used instead.

In the above embodiment, a CVD-8i02 film was used as the film, but a phosphorus silicide glass film (PSG film) or a nitride film may be used instead.

In the above embodiments, the high concentration p-type diffusion layer was formed after converting the polycrystalline silicon film into an oxide film, but the high concentration p-type diffusion layer may be formed before converting the polycrystalline silicon film into an oxide film.

〔Effect of the invention〕

As detailed above, according to the present invention, an n-channel transistor has an LDD structure, and there is a reduction in breakdown voltage between the nl-n" type high concentration impurity layer, a reduction in breakdown voltage between the gate electrode and the source and drain regions, and a reduction in the breakdown voltage between the gate electrode and the source and drain regions. It is possible to provide a method for manufacturing a high-performance, highly reliable complementary semiconductor device that eliminates damage caused by ions and also prevents fluctuations or decreases in the threshold voltage of an n-channel transistor.

[Brief explanation of drawings]

FIG. 1(a) to (h) are 0MO in the embodiment of the present invention.
2 (a) to (Q) are sectional views showing the manufacturing process of conventional 0MO3, and Figure 3 is a cross-sectional view showing the manufacturing process of 0MO8 obtained by the conventional method. FIG. 101...N-type silicon substrate, 1o2...P-well, 103...Field oxide film (element isolation region Ja
), 106.107...gate electrode, 108.109
... Gate oxide film, 111 ... Polycrystalline silicon film (
oxidizability, film), 112-CVD-8i 02 film (coating), 1131-1134...n-type diffusion layer, 114
...Wall body, 115, 1152...n+ type scattered layer 116...source region, 117...drain region,
118... Oxide film, 119... P++ source region,
120...p+ type tray area 121-3 i02
Il! , 123-125...AΩ wiring. Applicant's agent Patent attorney Takehiko Suzue Figure 1 Figure 2

Claims (4)

[Claims] (1) A step of selectively forming a semiconductor layer of a conductivity type opposite to that of the substrate on a semiconductor substrate of one conductivity type, a step of forming an element isolation region between the semiconductor substrate and the semiconductor layer, and the element isolation region a step of forming an insulating film on the surfaces of the island-shaped element regions of the semiconductor substrate and the semiconductor layer separated from each other; and a step of selectively forming gate electrodes on the first insulating films on the surfaces of each of the element regions. , a step of doping impurities of a first conductivity type into each of the device regions using each of the gate electrodes and the device isolation region as a mask, a step of sequentially depositing an oxidizable film and a coating on the entire surface, and a step of depositing the coating on each of the gates. A step of selectively leaving the remaining film on the side surface of the electrode, a step of doping the impurity of the first conductivity type into each of the device regions using the remaining film, each gate electrode, and the device isolation region as a mask, and a step of removing the remaining film. , a step of converting the oxidizable film into an oxide film, and a step of selectively doping an impurity of a second conductivity type into a device region of a conductivity type opposite to that of the impurity using at least the gate electrode and the device isolation region as a mask. A method for manufacturing a complementary semiconductor device, comprising: (2) The method for manufacturing a complementary semiconductor device according to claim 1, wherein the oxidizable film is made of polycrystalline silicon. (3) The method for manufacturing a complementary semiconductor device according to claim 1, wherein the thickness of the oxidizable film is thicker than 1/2 of the thickness of the insulating film. (4) The method for manufacturing a complementary semiconductor device according to claim 1, wherein the second conductivity type impurity is doped after the remaining film is removed.