JPH0621373A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To prevent a change in the surface concentration of an LDD layer which occurs in the course of a manufacturing process, in CMOS having an LDD structure. CONSTITUTION:After a gate electrode 6 is formed, a silicon oxide film 7a and then N<->type conducting layers 9a and 9b and P<->type conducting layers 10a and 10b are formed and a silicon nitride film 8 is deposited on the whole surface. Thereafter deposition and reflow of a BPSG film 11 are executed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a CMOS transistor having an LDD structure.

[0002]

2. Description of the Related Art Referring to FIG. 3 which is a sectional view in the order of steps illustrating a method for manufacturing a semiconductor device, a conventional CMOS transistor having an LDD structure is first manufactured by a P-type silicon substrate 1.
After forming the P-well 2 and the N-well 3 on the substrate, an element isolation region is formed by forming the silicon oxide film 4 by the LOCOS method, and is formed on the surface of the silicon substrate 1 including the N-channel and P-channel MOS transistor formation planned regions. A gate oxide film 5 is formed, and a gate electrode 6 made of an N-type polycrystalline silicon film is selectively formed. Next, a silicon oxide film 7a having a film thickness of about 30 nm is formed again by thermal oxidation on the surfaces of the regions where the N-channel and P-channel MOS transistors are to be formed including the surface of the gate electrode 6 by thermal oxidation. , N-channel MOS Totanjisuta selectively N in forming region of the ^- type conductive layer 9a, N ^- P-well 2 to form a conductive layer 9b, P-channel MOS
P ^-type conductive layer 1 is selectively formed in the area where the transistor is to be formed.
0a, P ^{− type} conductive layer 10b is sequentially formed [FIG.
(A)].

Next, a BPSG film 11 is deposited and heat-treated to form N ^--type conductive layers 9a, 9b, P ^--type conductive layer 10a,
Openings reaching 10b are formed, and a silicon oxide film 17 is formed by thermal oxidation on the surfaces of these openings. Next, after the aluminum film 23a is formed, the N ^{+ type} conductive layer 19 is formed in the openings of the N ^{− type} conductive layers 9a and 9b by ion implantation using this as a mask [FIG. 3 (b)]. After the aluminum film 23a is removed to form the aluminum film 23b, the P ⁺ -type conductive layer 20 is formed in the openings of the P ⁻ -type conductive layers 10a and 10b by ion implantation using this as a mask [FIG. )].

Next, the aluminum film 23b is removed and a heat treatment is performed, the silicon oxide film 17 is removed, and then a tungsten silicide film 12 and an aluminum film 13 are sequentially deposited, and this laminated film is patterned and heat treated. As a result, a conventional CMOS transistor having an LDD structure can be obtained [FIG. 3 (d)].

[0005]

In the conventional method for manufacturing a semiconductor device described above, the surface of the region where the low-concentration conductive layer of the source / drain is formed is high with the silicon oxide film 7a having a thickness of about 30 nm interposed therebetween. It is in contact with the BPSG film 11 containing phosphorus and boron at a concentration. Therefore, this BPS
In the heat treatment for reflowing the G film 11, the BPS
The G film 11 serves as a finite diffusion source, and phosphorus or boron is diffused into the low-concentration conductive layer through the silicon oxide film 7a having a small masking effect against thermal diffusion of impurities. On the other hand, although the CVD method is used to form the BPSG film 11, it is difficult to control the phosphorus and boron concentrations thereof.

As a result, in the low-concentration conductive layer of the same conductivity type as the diffused impurities, the impurity concentration on the surface increases and the junction reverse breakdown voltage decreases, which is large in the characteristics of the MOS transistor of the same conductivity type channel. It becomes a defect. At the same time, in the reverse-conductivity-type low-concentration conductive layer, the impurity concentration on the surface decreases, the series resistance between the source and drain increases, and this is a major defect in the characteristics of the reverse-conductivity-type channel MOS transistor.

Further, in recent years, the planar miniaturization of semiconductor elements has been advanced with the high integration of LSIs, but the miniaturization in the stacking direction, that is, the vertical direction has been delayed. As a result, the aspect ratio of the opening with respect to the semiconductor element becomes high, and reflow of the BPSG film is used to solve this. Therefore, the impurity concentration of the BPSG film tends to increase, and the above-mentioned problem of diffusion of impurities in the BPSG film to the source / drain is becoming a more serious problem.

[0008]

A method of manufacturing a semiconductor device according to the present invention comprises a step of forming an element isolation region on a surface of a silicon substrate and a second step on a surface of a first conductivity type region of the silicon substrate.
A step of forming a gate electrode through a first insulating film in the channel type transistor formation planned region and the first channel type transistor formation planned region on the surface of the second conductivity type region of the silicon substrate; Introduction of impurities of the first conductivity type by forming a second insulating film over the entire surface of the first channel type transistor formation planned region including the surface and the second channel type transistor formation planned region and using the gate electrode as a mask To form a first conductive type first conductive layer serving as a source / drain in the first channel type transistor formation region, and by introducing an impurity of the second conductive type using the gate electrode as a mask, Second source / drain in the transistor formation area
A step of forming a conductive type first conductive layer, a step of forming a third insulating film, a step of forming an interlayer insulating film containing impurities on the entire surface, a step of performing heat treatment, an interlayer insulating film and a second and third insulating layer. The film is patterned to form an opening reaching the first conductive layer of the first conductivity type and the first conductive layer of the second conductivity type, a fourth insulating film is formed on the bottom surface of the opening, and heat treatment is performed. The step of applying and the introduction of impurities of the first conductivity type make the first conductivity having a higher impurity concentration than the first conductivity type first conductive layer in the region of the first conductivity type first conductive layer immediately below the fourth insulating film. Type second conductive layer is formed, and impurities of the second conductive type first conductive layer are formed in a region of the second conductive type first conductive layer immediately below the fourth insulating film by introducing impurity of the second conductive type. And a step of forming a second conductive layer of the second conductivity type having a high concentration. Preferably, the third insulating film is a silicon nitride film.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

Referring to FIG. 1, which is a sectional view in order of steps for explaining a method for manufacturing a semiconductor device, a first embodiment of the present invention is designed such that a surface of a P-type silicon substrate 1 is selectively formed. surface impurity concentration sequentially formed 5 × 10 ¹⁵ / cm ³ of about P-well 2, N-well 3. Next, a silicon oxide film 4 having a thickness of about 1 μm is formed in a predetermined region by the LOCOS method to form an element isolation region. Next, in a region where elements such as N-channel and P-channel MOS transistors are formed, a silicon oxide film 5 having a film thickness of about 30 nm to be a gate oxide film is formed by a thermal oxidation method, and the threshold value of each transistor is set. Ion implantation for setting is sequentially performed.

Next, a polycrystal silicon film having a film thickness of about 600 nm is deposited by the CVD method, and the polycrystal silicon film is subjected to thermal diffusion of phosphorus to form an N-type polycrystal silicon film having a sheet resistance of about 18 Ω / □. To This N-type polycrystalline silicon film is patterned by a dry etching method,
The gate electrode 6 is formed. Next, after acid treatment, 1
A silicon oxide film 7a having a thickness of about 30 nm is formed on the surface of the gate electrode 6 and the surface of the silicon substrate 1 on which the silicon oxide film 4 is not formed by a thermal oxidation method at 000 to 1100 ° C.

Next, by ion implantation, N ^--type conductive layers 9a and 9b are sequentially formed in the N well 3 and the P well 2, respectively, and P ^--type conductive layers 10a and 10b are respectively formed in the P well 2 and the N well 3. To form. N ^{− type} conductive layers 9a, 9b,
The surface impurity concentration of each of the P ^{− type} conductive layers 10a and 10b is about 5 × 10 ¹⁷ / cm ³ .

Next, a film thickness of 100 n is formed by a low pressure CVD method.
A silicon nitride film 8 of about m is deposited on the entire surface. continue,
1 μm of BPSG film 11 having a phosphorus concentration of about 10 mol% and a boron concentration of about 20 mol% by the atmospheric pressure CVD method.
About 100 ° C. and heat-treated at about 1000 ° C. in an H ₂ —O ₂ atmosphere [FIG. 1 (a)].

Next, the BPSG film 11, the silicon nitride film 8 and the silicon oxide film 7a are sequentially removed by etching by a known photolithography technique and dry etching method.
Openings are formed to reach the N ^{− type} conductive layers 9a and 9b and the P ^{− type} conductive layers 10a and 10b, respectively. After the acid treatment, thermal oxidation is performed at 1000 ° C. for 10 minutes to form a silicon oxide film 7 having a film thickness of about 20 nm on the surfaces of these openings.
b is formed [FIG. 1 (b)]. Next, by ion implantation, in each self-aligned with these openings, N ^- type conductive layer 9a, an N ⁺ type conductive layer 19 is formed on 9b, P ^- type conductive layer 10a, 10b in the P ⁺ type conductive Form layer 20. N
The surface impurity concentrations of the ^{+ type} conductive layer 19 and the P ^{+ type} conductive layer 20 are about 1 × 10 ¹⁹ / cm ³ respectively (FIG. 1).
(C)].

After that, heat treatment is performed in a nitrogen atmosphere at 1000 ° C. for about 10 minutes. Next, after removing the silicon oxide film 7b of about 30 nm by an acid treatment method using HF, a tungsten silicide film 12 and an aluminum film 13 are sequentially deposited, and this laminated film is patterned and heat-treated. LDD according to the first embodiment
A CMOS transistor having a structure can be obtained [Fig. 1
(D)].

Referring to FIG. 2 which is a sectional view in the order of steps for explaining a method for manufacturing a semiconductor device, the second embodiment of the present invention is the same as the first embodiment until formation of the gate electrode 6 and acid treatment.
In the same manner as in the above embodiment, N ⁻ type conductive layers 9a and 9b and P ^{− type} conductive layers 10a and 10b are formed. Next, a CVD silicon oxide film 13 having a film thickness of about 100 nm is deposited on the entire surface by a low pressure CVD method. Subsequently, the CVD silicon oxide film 13 is etched back by a dry etching method, and the CVD silicon oxide film 13 is left only on the side surface of the gate electrode 6. Then, after cleaning, a film thickness of 100 is obtained by the low pressure CVD method as in the first embodiment.
A silicon nitride film 8 having a thickness of about nm is deposited on the entire surface. Subsequently, the BPSG film 11 is deposited to a thickness of about 1 μm by the atmospheric pressure CVD method, and heat-treated at 1000 ° C. for about 20 minutes in an H ₂ —O ₂ atmosphere to flatten the surface of the BPSG film 11 [FIG. ].

Thereafter, similar to the first embodiment, the N ^--type conductive layers 9a and 9b and the P ^--type conductive layer 10 are respectively formed.
Apertures reaching a and 10b are formed. After the acid treatment, thermal oxidation is performed at 1000 ° C. for 10 minutes to form a silicon oxide film 7b having a film thickness of about 20 nm on the surfaces of these openings. Next, by ion implantation, the N ^{+ type} conductive layer 1 is formed.
9, P ^{+ type} conductive layer 20 is formed. [FIG. 2 (b)].

After that, heat treatment is performed in a nitrogen atmosphere at 1000 ° C. for about 10 minutes. Next, after removing the silicon oxide film 7b of about 30 nm by an acid treatment method using HF, a tungsten silicide film 12 and an aluminum film 13 are sequentially deposited, and the laminated film is patterned and heat-treated. LDD according to the second embodiment
A CMOS transistor having a structure can be obtained [Fig. 2
(C)].

[0019] According to the second embodiment, N ^- type conductive layer 9a, 9b, and P ^- type conductive layer 10a, in the region where the opening is formed in 10b, the silicon nitride film 8 of these N ^- Type conductive layers 9a and 9b, and P ^{− type} conductive layer 1
Since they are deposited directly on the surfaces of 0a and 10b, the diameter of the opening is not enlarged by the side etching during the dry etching for forming the opening and the subsequent acid treatment. Further, in the first embodiment, since the silicon oxide film 7a and the silicon nitride film 8 are laminated in the region where the opening is formed, the undercut of the silicon oxide film 7a is caused by the etching for forming the opening. Although it is likely to occur, it does not occur in this embodiment. Therefore, in this embodiment, as compared with the first embodiment, the contact property between the metal wiring made of the tungsten silicide film 12 and the aluminum film 13 and the N ^{+ type} conductive layer 19 and the P ^{+ type} conductive layer 20 is improved. Will be very good.

[0020]

As described above, according to the present invention, L
After the low concentration regions (N ^{− type} conductive layer, P ^{− type} conductive layer) of the source / drain of the DD structure are formed and before the BPSG film is deposited, the silicon nitride film is deposited on the entire surface, so that the reflow of the BPSG film is performed. During this heat treatment, high-concentration phosphorus and boron from this film will not diffuse into the low-concentration regions of the source / drain. As a result, a decrease or increase in the impurity concentration on the surface of the low concentration region can be avoided, and a decrease in junction breakdown voltage and an increase in source / drain series resistance do not occur in each of N-channel and P-channel transistors. Thus, a CMOS transistor having good transistor characteristics can be obtained.

Further, according to the present invention, it becomes possible to obtain a good reflow state of the BPSG film even if the concentrations of phosphorus and boron are further increased with the miniaturization of the semiconductor element, and the miniaturization technology in the future. It becomes an effective means in.

For example, in a CMOS transistor manufactured according to the present invention, the concentration of phosphorus and boron is 20 mo.
Even if it is increased up to about 1% and about 30 mol%, the PN junction breakdown voltage of the N-channel and P-channel MOS transistors is very high at about 45 V and is stable. Further, the width and spacing of the gate electrodes are about 1.5 μm and 1.2 μm, and the BPS on the gate electrodes from the surface of the silicon substrate is
Even if the height to the G film surface is about 1 μm (the aspect ratio becomes high), a highly reliable CMOS transistor can be obtained.

[Brief description of drawings]

1A to 1D are cross-sectional views in order of processes for explaining a first embodiment of the present invention.

2A to 2D are cross-sectional views in order of a process, for illustrating a second embodiment of the present invention.

3A to 3D are cross-sectional views in order of processes for explaining a method for manufacturing a conventional CMOS transistor having an LDD structure.

[Explanation of symbols]

1 P-type silicon substrate 2 P-well 3 N-well 4, 7a, 7b, 17 Silicon oxide film 5 Gate oxide film 6 Gate electrode 8 Silicon nitride film 9a, 9b N ^{− type} conductive layer 10a, 10b P ^{− type} conductive layer 11 BPSG film 12 Tungsten silicide film 13, 23a, 23b Aluminum film 19 N ^{+ type} conductive layer 20 P ^{+ type} conductive layer

Claims (2)

[Claims] 1. A step of forming an element isolation region on a surface of a silicon substrate, a region for forming a second channel type transistor on a surface of a first conductivity type region of the silicon substrate, and a second conductivity type of the silicon substrate. A step of forming a gate electrode in the first channel type transistor formation scheduled area on the surface of the region via a first insulating film; and the first channel type transistor formation scheduled area including at least the surface of the gate electrode , And a second insulating film is formed on the entire surface of the second channel type transistor formation planned region, and the first conductivity type impurity is introduced by using the gate electrode as a mask to introduce the first channel type transistor formation planned region. A first conductive type first conductive layer serving as a source / drain is formed on the substrate, and the second conductive type impurity is introduced by using the gate electrode as a mask. Second as the source and drain in the transistor formation region of the second channel type
A step of forming a first conductive type conductive layer, a step of forming a third insulating film, a step of forming an interlayer insulating film containing impurities on the entire surface, and a heat treatment; A third insulating film is patterned to form an opening reaching the first conductive type first conductive layer and the second conductive type first conductive layer, and a fourth insulating film is formed on the bottom surface of the opening. And heat treatment, and introducing a first conductivity type impurity into the first conductivity type first
In the region of the conductive layer directly below the fourth insulating film, the second conductive type second having a higher impurity concentration than the first conductive type first conductive layer is formed.
A conductive layer is formed, and the impurity concentration of the second conductive type is lower than that of the first conductive layer of the second conductive type in the region immediately below the fourth insulating film of the first conductive layer of the second conductive type. And a step of forming a second conductive layer having a high second conductivity type. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the third insulating film is a silicon nitride film.