JPS61154172A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS61154172A JPS61154172A JP27822484A JP27822484A JPS61154172A JP S61154172 A JPS61154172 A JP S61154172A JP 27822484 A JP27822484 A JP 27822484A JP 27822484 A JP27822484 A JP 27822484A JP S61154172 A JPS61154172 A JP S61154172A
- Authority
- JP
- Japan
- Prior art keywords
- gate electrode
- oxide film
- film
- region
- psg
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 11
- 239000004065 semiconductor Substances 0.000 title claims description 11
- 239000000758 substrate Substances 0.000 claims abstract description 20
- 238000009792 diffusion process Methods 0.000 claims description 24
- 238000007254 oxidation reaction Methods 0.000 claims description 13
- 230000003647 oxidation Effects 0.000 claims description 9
- 239000011521 glass Substances 0.000 claims description 5
- 238000000059 patterning Methods 0.000 claims description 5
- 239000007772 electrode material Substances 0.000 claims description 4
- 238000005530 etching Methods 0.000 claims description 4
- 239000012535 impurity Substances 0.000 claims description 4
- 239000000463 material Substances 0.000 claims description 2
- 238000000034 method Methods 0.000 abstract description 18
- 229910052698 phosphorus Inorganic materials 0.000 abstract description 11
- 239000011574 phosphorus Substances 0.000 abstract description 11
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 abstract description 10
- 238000000137 annealing Methods 0.000 abstract description 6
- 229910052785 arsenic Inorganic materials 0.000 abstract description 6
- HAYXDMNJJFVXCI-UHFFFAOYSA-N arsenic(5+) Chemical compound [As+5] HAYXDMNJJFVXCI-UHFFFAOYSA-N 0.000 abstract description 4
- 150000002500 ions Chemical class 0.000 abstract description 4
- 239000012299 nitrogen atmosphere Substances 0.000 abstract description 4
- -1 arsenic ions Chemical class 0.000 abstract description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 3
- 229910052681 coesite Inorganic materials 0.000 abstract description 2
- 229910052906 cristobalite Inorganic materials 0.000 abstract description 2
- 239000000377 silicon dioxide Substances 0.000 abstract description 2
- 229910052682 stishovite Inorganic materials 0.000 abstract description 2
- 229910052905 tridymite Inorganic materials 0.000 abstract description 2
- 239000010410 layer Substances 0.000 description 8
- 208000022010 Lhermitte-Duclos disease Diseases 0.000 description 5
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 5
- 238000005468 ion implantation Methods 0.000 description 4
- 238000001259 photo etching Methods 0.000 description 4
- 238000001020 plasma etching Methods 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 239000012298 atmosphere Substances 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000020169 heat generation Effects 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
本発明は、半導体装置の製造方法に関し、特にＭＯ８型
半導体装置の製造方法の改良に係わる。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method for manufacturing a semiconductor device, and particularly to an improvement in a method for manufacturing an MO8 type semiconductor device.
ＭＯ８型半導体装置において、高耐圧化、微細化に伴い
、ドレイン領域端部での電界集中を回避するために、ゲ
ート領域端部のチャンネル領域に該ドレイン領域よりも
低濃度の領域を設けるＬＤＤ （Ｌ ｉ！１ｌｈｔ
Ｄ ０Ｄｅｄ Ｄ ｒａｉｎ）構造が開発サレテいる
。こうしたＬＤＤ構造を有するＭＯ８半導体装置、例え
ばｎチャンネルＭＯＳトランシタは、従来より以下に説
明する第２図（ａ）〜（ｅ）に示す方法によって製造さ
れている。In MO8 type semiconductor devices, in order to avoid electric field concentration at the end of the drain region due to higher breakdown voltage and miniaturization, LDD (LDD) provides a channel region at the end of the gate region with a lower concentration than the drain region. L i!1lht
D0DedDrain) structure is under development. MO8 semiconductor devices having such an LDD structure, such as n-channel MOS transistors, have conventionally been manufactured by the method shown in FIGS. 2(a) to 2(e) described below.
まず、ｐ型シリコン基板１表面に選択酸化法により厚さ
約１μｍのフィールド酸化膜２を形成した後、熱酸化処
理を施してフィールド酸化膜２で分離された島状の基板
１領域表面に厚さ５００人の酸化膜３を形成する。つづ
いて、酸化膜３を通して閾値制御のためのチャンネルイ
ンプラを行なう。ひきつづき、全面にゲート電極材料膜
、例えば多結晶シリコン膜を堆積し、ＰＯＣｆｆｉの雰
囲気中でリン拡散を行なって多結晶シリコン膜中にリン
をドープして低抵抗化させた後、該多結晶シリコン膜を
フォトエツチング技術によりパターニングしてゲート電
極４を形成する（第２図（ａ）図示）。First, a field oxide film 2 with a thickness of approximately 1 μm is formed on the surface of a p-type silicon substrate 1 by selective oxidation, and then thermal oxidation treatment is performed to form a thick film on the surface of island-shaped substrate 1 regions separated by field oxide film 2. An oxide film 3 of 500 layers is formed. Subsequently, channel implantation for threshold control is performed through the oxide film 3. Subsequently, a gate electrode material film, such as a polycrystalline silicon film, is deposited on the entire surface, and phosphorus is diffused in the POCffi atmosphere to dope phosphorus into the polycrystalline silicon film to lower its resistance. The gate electrode 4 is formed by patterning the film using a photoetching technique (as shown in FIG. 2(a)).
次いで、ゲート電極４及びフィールド酸化膜２をマスク
として酸化１１１３を選択的にエツチング除去してゲー
ト酸化［１５を形成した後、同ゲート電極４及びフィー
ルド酸化１２をマスクとしてリンをイオン注入してリン
イオン注入層６１．６２を形成する（同図（ｂ）図示）
。Next, using the gate electrode 4 and the field oxide film 2 as a mask, the oxide 1113 is selectively etched away to form a gate oxide [15], and then phosphorus is ion-implanted using the gate electrode 4 and the field oxide film 2 as a mask to form phosphorus ions. Form injection layers 61 and 62 (as shown in the same figure (b))
.
次いで、Ｎ２雰囲気中でアニーリングを行なってリンを
活性化し、低濃度のｎ−型拡散領域７１．７２を形成す
る。ひきづづき、後酸化処理を施してゲート電極４及び
露出した基板１表面に薄い後酸化膜８を形成した後、全
面にＣＶＤ−８ｉ０２膜９を堆積する（同図（Ｃ）図示
）。ひきつづき、反応性イオンエツチング（ＲＩＥ）に
より全面エツチングしてゲート電極４側面の後酸化膜８
にＳｉＯ２からなる壁体１０を形成した後、フィールド
酸化膜２、ゲート電極４及び壁体１０をマスクとして砒
素を基板１にイオン注入して砒素イオン注入層１１１．
１１２を形成する（同図（ｄ）図示）。Next, annealing is performed in an N2 atmosphere to activate phosphorus and form low concentration n-type diffusion regions 71 and 72. Subsequently, a post-oxidation treatment is performed to form a thin post-oxidation film 8 on the gate electrode 4 and the exposed surface of the substrate 1, and then a CVD-8i02 film 9 is deposited on the entire surface (as shown in FIG. 4C). Subsequently, the entire surface is etched by reactive ion etching (RIE) to form a post-oxide film 8 on the side surface of the gate electrode 4.
After forming a wall 10 made of SiO2, arsenic is ion-implanted into the substrate 1 using the field oxide film 2, gate electrode 4, and wall 10 as a mask to form an arsenic ion-implanted layer 111.
112 (as shown in FIG. 11(d)).
次いで、Ｎ２雰囲気中でアニーリングを行なって砒素を
活性化して高濃度のｎ＋型拡散領域１２１．１２２を形
成する。これにより、基板１表面にｎ−型拡散領域７１
とｎ＋型拡散領域１２１からなるソース領域１３とｎ−
型拡散領［７２とｎ“型拡散領域１２２からなるドレイ
ン領域１４が形成される。つづいて、全面に層間絶縁膜
としてのＣＶＤ−８ｉ０２膜１５を堆積し、フォトエツ
チング技術によりコンタクトホール１６を開孔した後、
Ａ２膜の蒸着、パターニングにより前記コンタクトホー
ル１６を通してソース、ドレイン領域１３．１４と接続
するＡｊ２配線１７．１８は夫々形成してｎチャンネル
ＭＯＳトランジスタを製造する（同図（ｅ）図示）。Next, annealing is performed in an N2 atmosphere to activate arsenic and form highly concentrated n+ type diffusion regions 121 and 122. As a result, an n-type diffusion region 71 is formed on the surface of the substrate 1.
and a source region 13 consisting of an n+ type diffusion region 121 and an n-
A drain region 14 consisting of a type diffusion region [72] and an n" type diffusion region 122 is formed. Subsequently, a CVD-8i02 film 15 as an interlayer insulating film is deposited on the entire surface, and a contact hole 16 is opened by photoetching. After making a hole,
By vapor deposition and patterning of the A2 film, Aj2 wirings 17 and 18 which are connected to the source and drain regions 13 and 14 through the contact hole 16 are formed, respectively, to manufacture an n-channel MOS transistor (as shown in FIG. 12(e)).
しかしながら、上述した従来方法にあっては、ｎ−型拡
散領域７１．７２を形成するためのリンのイオン注入工
程、ＣＶＤ−８ｉ０２膜９の堆積工程、壁体１０の形成
工程、ｎ＋型拡散領域１２１．１２２を形成するための
砒素のイオン注入工程等、複雑な工程を経て製造される
ために、生産性の点で問題となる。また、ｎ−型拡散領
域７工、７２上部のゲート酸化膜５の膜中に正の可動イ
オン（例えばＮａ”、Ｋ”）が含まれると、表面が蓄積
状態となり、ｎ＋領域化してＬＤＤ構造の役目を果たさ
なくなり、耐圧劣化を招く。一方、ｎチャンネルＭＯＳ
トランジスタのＬＤＤ構造の場合には、ｐ−型領域上部
のゲート酸化膜中に正の可動イオンが含まれると、表面
が空乏層状態となり、ｐ−型領域上部に空乏層が形成さ
れ、ｐ−型領域の実効的な厚さを減少させて抵抗を増大
させ、トランジスタの駆動力を低下させたり、ジュール
熱発生により破壊に至る等の信頼性の上で問題が生じる
。However, in the conventional method described above, there is a phosphorus ion implantation step for forming the n-type diffusion regions 71, 72, a deposition step of the CVD-8i02 film 9, a step of forming the wall body 10, and a step of forming the n+-type diffusion region. Since it is manufactured through complicated processes such as an arsenic ion implantation process to form 121 and 122, it poses a problem in terms of productivity. Furthermore, if positive mobile ions (e.g., Na'', K'') are contained in the gate oxide film 5 above the n- type diffusion regions 7 and 72, the surface becomes accumulated and becomes an n+ region, forming an LDD structure. It no longer fulfills its role, leading to deterioration in pressure resistance. On the other hand, n-channel MOS
In the case of an LDD structure of a transistor, when positive mobile ions are included in the gate oxide film above the p-type region, the surface enters a depletion layer state, a depletion layer is formed above the p-type region, and the p- This reduces the effective thickness of the mold region and increases the resistance, resulting in reliability problems such as a reduction in the driving force of the transistor and destruction due to Joule heat generation.
（発明の目的）
本発明は、簡単な工程で信頼性の高いＬＤＤ構造を有す
るＭＯＳトランジスタ等の半導体装置を製造し得る方法
を提供しようとするものである。(Objective of the Invention) The present invention provides a method for manufacturing a semiconductor device such as a MOS transistor having a highly reliable LDD structure through simple steps.
本発明は、第１導電型の半導体基板の表面に酸化膜を介
してゲート電極材料膜を形成する工程と、この材料膜を
パターニングしてゲート電極を形成した後、該ゲート電
極をマスクとして前記酸化膜を選択的にエツチングして
ゲート酸化膜を形成する工程と、熱酸化処理を施して露
出した基板表面に薄い酸化膜を形成する工程と、全面に
第２導電型不純物がドープされたガラス膜を堆積した後
、エツチングを行なって前記ゲート電極の側面に前記ガ
ラスからなる壁体を形成する工程と、前記ゲート電極及
び壁体をマスクとして露出した基板表面に高濃度の第２
導電型拡散領域を形成すると共に、前記壁体から第２導
電型の不純物を基板に拡散して低濃度の第２導電型拡散
領域を形成する工程とを具備したことを特徴とするもの
である。かかる本発明によれば既述の如く簡単な工程で
信頼性の高いＬＤＤ構造を有するＭＯＳトランジスタ等
の半導体装置を得ることができる。The present invention includes a step of forming a gate electrode material film on the surface of a first conductivity type semiconductor substrate via an oxide film, and after patterning this material film to form a gate electrode, using the gate electrode as a mask, A process of selectively etching the oxide film to form a gate oxide film, a process of performing thermal oxidation treatment to form a thin oxide film on the exposed substrate surface, and a process of forming a glass doped with second conductivity type impurities on the entire surface. After depositing the film, etching is performed to form walls made of the glass on the side surfaces of the gate electrode, and etching is performed on the exposed substrate surface using the gate electrode and walls as masks.
The method is characterized by comprising a step of forming a conductivity type diffusion region and diffusing a second conductivity type impurity from the wall into the substrate to form a low concentration second conductivity type diffusion region. . According to the present invention, a semiconductor device such as a MOS transistor having a highly reliable LDD structure can be obtained through a simple process as described above.
以下、本発明をＬＤＤ構造を有するｎチャンネルＭＯＳ
トランジスタの製造に適用した例について第１図（ａ）
〜（ｄ）を参照して説明する。Hereinafter, the present invention will be described as an n-channel MOS having an LDD structure.
Figure 1(a) shows an example of application to transistor manufacturing.
This will be explained with reference to (d).
まず、ｐ型シリコン基板２１表面に選択酸化法により厚
さ約１μｍのフィールド酸化膜２２を形成した後、熱酸
化処理を施してフィールド酸化膜２２で分離された島状
の基板２１領域表面に厚さ５００人の酸化膜２３を形成
する。つづいて、酸化膜２３を通して閾値制御のための
チャンネルインプラを行なった。ひきつづき、全面に厚
さ４０００人のゲート電極材料膜、例えば多結晶シリコ
ン膜を堆積し、ＰＯＣｌ２の雰囲気中でリン拡散を行な
って多結晶シリコン膜中にリンをドープして低抵抗化さ
せた後、該多結晶シリコン膜をフォトエツチング技術に
よりパターニングしてゲート電極２４を形成した（第２
図（ａ）図示）。First, a field oxide film 22 with a thickness of about 1 μm is formed on the surface of a p-type silicon substrate 21 by selective oxidation, and then a thermal oxidation process is performed to form a thick film on the surface of the island-shaped substrate 21 separated by the field oxide film 22. An oxide film 23 of 500 layers is formed. Subsequently, channel implantation for threshold control was performed through the oxide film 23. Subsequently, a gate electrode material film, for example, a polycrystalline silicon film, is deposited to a thickness of 4000 μm over the entire surface, and phosphorus is diffused in an atmosphere of POCl2 to dope phosphorus into the polycrystalline silicon film to lower its resistance. Then, the polycrystalline silicon film was patterned using photoetching technology to form a gate electrode 24 (second
Figure (a) shown).
次いで、ゲート電極２４をマスクとして酸化膜２３を選
択的ににエツチング除去してゲート酸化膜２５を形成し
た。つづいて、後酸化処理を施してゲート電極２４及び
露出した基板２１表面に薄い後酸化膜２６を形成した後
、ゲート電極２４を含む全面にリン添加ガラス膜（ＰＳ
Ｇ膜）２７を堆積した（同図（ｂ）図示）。Next, using the gate electrode 24 as a mask, the oxide film 23 was selectively etched away to form a gate oxide film 25. Subsequently, after performing post-oxidation treatment to form a thin post-oxidation film 26 on the gate electrode 24 and the exposed surface of the substrate 21, a phosphorus-doped glass film (PS) is formed on the entire surface including the gate electrode 24.
G film) 27 was deposited (as shown in FIG. 3(b)).
次いで、反応性イオンエツチング（ＲＩＥ）により全面
エツチングしてゲート電極２４側面の後酸化膜２６にＰ
ＳＧからなる壁体２８を形成した後、フィールド酸化［
１２２、ゲート電極２４及び壁体２８をマスクとして砒
素を基板２１にイオン注入して砒素イオン注入層２９ｔ
、２９２を形成した（同図（Ｃ）図示）。Next, the entire surface is etched by reactive ion etching (RIE) to deposit P on the post-oxide film 26 on the side surface of the gate electrode 24.
After forming the wall 28 made of SG, field oxidation [
122, arsenic is ion-implanted into the substrate 21 using the gate electrode 24 and the wall 28 as a mask to form an arsenic ion-implanted layer 29t.
, 292 (as shown in FIG. 2C).
次いで、Ｎ２雰囲気中でアニーリングを行なった。この
時、砒素イオン注入層２９！、２９２が活性化されて＾
濃度のｎ＋型拡散領域３０１．３０２が形成されると共
に、ＰＳＧからなる壁体２８からリンが基板２１に拡散
されてｎ−型拡散領域３１１．３１２が形成された。こ
れにより、基板２１表面にｎ−型拡散領域３１１とｎ＋
型拡散領域３０１からなるソース領域３２とｎ−型拡散
領域３１２とｎ＋型拡散領域３０２からなるドレイン領
域３３が形成された。つづいて、全面に層間絶縁膜とし
てのＣＶＤ−８ｉ０２膜３４を堆積し、フォトエツチン
グ技術によりコンタクトホール３５を開孔した後、Ａｎ
膜の蒸着、パターニングにより前記コンタクトホール３
５を通してソース、ドレイン領域３２．３３と接続する
°Ａ２配線３６．３７は夫々形成してｎチャンネルＭＯ
Ｓトランジスタを製造した（同図（ｄ）図示）。Next, annealing was performed in an N2 atmosphere. At this time, the arsenic ion implantation layer 29! , 292 is activated ^
At the same time, n+ type diffusion regions 301 and 302 with a high concentration were formed, and phosphorus was diffused into the substrate 21 from the wall body 28 made of PSG to form n− type diffusion regions 311 and 312. As a result, the n- type diffusion region 311 and the n+
A source region 32 consisting of a type diffusion region 301, a drain region 33 consisting of an n- type diffusion region 312, and an n+ type diffusion region 302 were formed. Subsequently, a CVD-8i02 film 34 as an interlayer insulating film is deposited on the entire surface, and a contact hole 35 is opened using photoetching technology.
The contact hole 3 is formed by film deposition and patterning.
A2 wirings 36 and 37 connected to the source and drain regions 32 and 33 through 5 are formed respectively to form n-channel MO
An S transistor was manufactured (as shown in the same figure (d)).
しかして、本発明によればＰＳＧからなる壁体２８をｎ
−型拡散領域３１１．３１２の形成のための拡散源とし
ても利用することによって、ｎ−型拡散領域を形成する
ためのリンのイオン注入工程及びアニーリング工程を省
略できるので、簡単な工程によりＬＤＤ構造を有するｎ
チャンネルＭＯＳトランジスタを得ることができる。ま
た、ＰＳＧからなる壁体２８をゲート酸化膜２５近傍に
形成することによって、該ＰＳＧのパッシベーション効
果により正の可動イオンがゲート酸化膜２５の膜中に蓄
積するのを回避できる。その結果、ゲート酸化［１２５
の耐圧を向上でき、高信頼性のＭＯＳトランジスタを得
ることができる。According to the present invention, the wall body 28 made of PSG is
By also using it as a diffusion source for forming the - type diffusion regions 311 and 312, the phosphorus ion implantation process and annealing process for forming the n - type diffusion region can be omitted. n with
A channel MOS transistor can be obtained. Further, by forming the wall body 28 made of PSG near the gate oxide film 25, it is possible to prevent positive mobile ions from accumulating in the gate oxide film 25 due to the passivation effect of the PSG. As a result, gate oxidation [125
The withstand voltage can be improved, and a highly reliable MOS transistor can be obtained.
なお、本発明は上記実施例に説明したようなｎチャンネ
ルＭＯＳトランジスタの製造のみに限定されず、ＬＤＤ
構造を有するｎチャンネルＭＯＳトランジスタ、同構造
を有する０ＭＯ８等にも同様に適用できる。Note that the present invention is not limited to the manufacture of n-channel MOS transistors as explained in the above embodiments, but is also applicable to LDDs.
The present invention can be similarly applied to an n-channel MOS transistor having the same structure, 0MO8, etc. having the same structure.
以上詳述した如く、本発明によれば簡単な工程で信頼性
の高いＬＤＤ構造を有するＭＯＳトランジスタ等の半導
体装置を製造し得る方法を提供できる。As described in detail above, according to the present invention, it is possible to provide a method for manufacturing a semiconductor device such as a MOS transistor having a highly reliable LDD structure through simple steps.
第１図（ａ）〜（ｄ）は本発明の実施例におけるＬＤＤ
構造を有するｎチャンネルＭＯＳトランジスタの製造工
程を示す断面図、第２図（ａ）〜（ｅ）は従来のＬＤＤ
構造を有するｎチャンネルＭＯＳトランジスタの製造工
程を示す断面図である。
２１・・・ｐ型シリコン基板、２２・・・フィールド酸
化膜、２４・・・ゲート電極、２５・・・ゲート酸化膜
、２８ ・Ｐ Ｓ Ｇからなる壁体、３０ｔ 、３０２
−ｎ１型拡散領域、３１１．３１２・・・ｎ−型拡散領
域、３２・・・ソース領域、３３・・・ドレイン領域、
３６．３７・・・Ａ２配線。FIGS. 1(a) to 1(d) show LDDs in embodiments of the present invention.
2(a) to 2(e) are cross-sectional views showing the manufacturing process of an n-channel MOS transistor having the structure of a conventional LDD.
FIG. 3 is a cross-sectional view showing the manufacturing process of an n-channel MOS transistor having the structure. DESCRIPTION OF SYMBOLS 21... P-type silicon substrate, 22... Field oxide film, 24... Gate electrode, 25... Gate oxide film, 28 ・Wall body made of PSG, 30t, 302
- n1 type diffusion region, 311.312... n- type diffusion region, 32... source region, 33... drain region,
36.37...A2 wiring.
Claims (1)
ト電極材料膜を形成する工程と、この材料膜をパターニ
ングしてゲート電極を形成した後、該ゲート電極をマス
クとして前記酸化膜を選択的にエッチングしてゲート酸
化膜を形成する工程と、熱酸化処理を施して露出した基
板表面に薄い酸化膜を形成する工程と、全面に第２導電
型不純物がドープされたガラス膜を堆積した後、エッチ
ングを行なって前記ゲート電極の側面に前記ガラスから
なる壁体を形成する工程と、前記ゲート電極及び壁体を
マスクとして露出した基板表面に高濃度の第２導電型拡
散領域を形成すると共に、前記壁体から第２導電型の不
純物を基板に拡散して低濃度の第２導電型拡散領域を形
成する工程とを具備したことを特徴とする半導体装置の
製造方法。A step of forming a gate electrode material film on the surface of a first conductivity type semiconductor substrate via an oxide film, and after patterning this material film to form a gate electrode, selecting the oxide film using the gate electrode as a mask. The first step was to perform thermal oxidation treatment to form a gate oxide film, the second step was to perform thermal oxidation treatment to form a thin oxide film on the exposed substrate surface, and the second step was to deposit a glass film doped with second conductivity type impurities over the entire surface. After that, etching is performed to form a wall made of the glass on the side surface of the gate electrode, and a highly concentrated second conductivity type diffusion region is formed on the exposed substrate surface using the gate electrode and the wall as a mask. A method of manufacturing a semiconductor device, further comprising the step of diffusing second conductivity type impurities from the wall into the substrate to form a low concentration second conductivity type diffusion region.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP27822484A JPS61154172A (en) | 1984-12-27 | 1984-12-27 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP27822484A JPS61154172A (en) | 1984-12-27 | 1984-12-27 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61154172A true JPS61154172A (en) | 1986-07-12 |
Family
ID=17594342
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP27822484A Pending JPS61154172A (en) | 1984-12-27 | 1984-12-27 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61154172A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63164465A (en) * | 1986-12-26 | 1988-07-07 | Fujitsu Ltd | Semiconductor device and manufacture thereof |
| JPS6432676A (en) * | 1987-07-29 | 1989-02-02 | Nec Corp | Manufacture of insulated-gate field-effect transistor |
| JPH01119070A (en) * | 1987-10-31 | 1989-05-11 | Toshiba Corp | Semiconductor device and manufacture thereof |
| US5434440A (en) * | 1992-05-29 | 1995-07-18 | Kabushiki Kaisha Toshiba | Semiconductor device and method of manufacturing the same |
| US5698881A (en) * | 1992-05-29 | 1997-12-16 | Kabushiki Kaisha Toshiba | MOSFET with solid phase diffusion source |
-
1984
- 1984-12-27 JP JP27822484A patent/JPS61154172A/en active Pending
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5898203A (en) * | 1909-12-11 | 1999-04-27 | Kabushiki Kaisha Toshiba | Semiconductor device having solid phase diffusion sources |
| JPS63164465A (en) * | 1986-12-26 | 1988-07-07 | Fujitsu Ltd | Semiconductor device and manufacture thereof |
| JPS6432676A (en) * | 1987-07-29 | 1989-02-02 | Nec Corp | Manufacture of insulated-gate field-effect transistor |
| JPH01119070A (en) * | 1987-10-31 | 1989-05-11 | Toshiba Corp | Semiconductor device and manufacture thereof |
| US5434440A (en) * | 1992-05-29 | 1995-07-18 | Kabushiki Kaisha Toshiba | Semiconductor device and method of manufacturing the same |
| US5698881A (en) * | 1992-05-29 | 1997-12-16 | Kabushiki Kaisha Toshiba | MOSFET with solid phase diffusion source |
| US5766965A (en) * | 1992-05-29 | 1998-06-16 | Yoshitomi; Takashi | Semiconductor device and method of manufacturing the same |
| US5903027A (en) * | 1992-05-29 | 1999-05-11 | Kabushiki Kaisha Toshiba | MOSFET with solid phase diffusion source |
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