JPH01119070A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To prevent side wall of a cell transistor from being affected by alkali metal pollution and problems such as data inversion from being produced by providing a non-volatile memory element with a cell transistor having doped oxide film to a transistor in LDD construction which was formed on the same substrate and to the side wall. CONSTITUTION:A field oxide film 102 for separating elements and the first gate oxide film 103 are formed on a p-type semiconductor substrate, a polycrystalline silicon layer is built up on the entire surface, which is subject to patterning, a gate electrode 104 is formed at a CPU part, a polycrystalline silicon layer 105 is left as it is without performing etching at an EPROM part, and the polycrystalline silicon layer 105 becomes a floating gate and a polycrystalline silicon layer 108 becomes a control gate at the EPROM part. After forming an oxide film for insulation is formed around a complex gate of the EPROM part, a phosphosilicate glass(PSG) 114 which is a silicon oxidation film doped with phosphorus is built up on the entire surface and is etched back to allow PSG layers 115, 116, 117, and 118 to remain only on the side wall of each gate electrode.

Description

[Detailed Description of the Invention] [Object of the Invention] (Field of Industrial Application) The present invention relates to a semiconductor device and a method for manufacturing the same;
In particular, the present invention relates to a semiconductor device in which a nonvolatile memory element and a logic element are formed on the same substrate, and a method for manufacturing the same.

(Prior Art) As nonvolatile memory elements, there are known EPROMs in which data can be erased with ultraviolet rays and electrically written, and EEPROMs in which data can be electrically written and erased.

FIG. 4 is an element cross-sectional view showing the structure of EPROM, and p
A gate insulator M2, which is a silicon oxide film, is formed on the surface of a type semiconductor substrate 1, on which a floating gate 3 for accumulating charges, an insulating film 4, and a control gate 5 for controlling charges accumulated in the floating gate are formed. A composite gate is formed by sequentially laminating layers and having a surface covered with an insulating film 6. Note that each layer of floating gate 3 and control gate 5 is usually made of polycrystalline silicon. Further, in the substrate, a source 7 and a drain 8, which are n+ diffusion regions in which impurities such as arsenic are diffused, are formed on both sides of the gate electrode.

In an EPROM having such a structure, a write voltage of 10 to 20 V is applied to the control gate 5, and hot electrons near the drain inject electrons into the floating gate 3 to perform storage. On the other hand, when erasing is performed, electrons are emitted from the floating gate 3 by irradiation with ultraviolet rays. In this way, by injecting or ejecting electrons into the floating gate 3 and changing its potential, the threshold voltage of the cell transistor is changed, and the cell transistor is used as a memory element.

FIG. 5 shows the structure of a FLOTOX type EEPROM that uses a tunnel oxide film among the many types of EEPROM. In this structure, the p-type semiconductor substrate 11
The gate insulating film 12 has a tunnel oxide film 12a, which is a thin part of about 100 A, on the surface of the gate insulating film 12. A floating gate 13, an insulating layer 14, and a control gate 15 are sequentially laminated on the gate insulating film 12. A composite gate covered with Note that the floating gate 3 and the control gate 5
Each layer is typically made of polycrystalline silicon. Also,
In the substrate, a source 17, which is an n-diffusion region in which an impurity such as arsenic is diffused, is formed at the end of the gate electrode, and a drain 18, which is an n-diffusion region, extends below the tunnel oxide film 12a.

In an EEPROM with such a structure, the control gate 15 has two
Applying a write voltage of about 0V, the tunnel oxide film 12a is
Electrons are injected into the floating gate 13 by Fowler-Nordheim (F-N) tunneling. Conversely, when erasing is performed, the voltage applied to the control gate 15 is set to OV, and an erase voltage of about 20 V is applied to the source 17 to emit electrons from the floating gate by FN tunneling.

In this way, the storage mechanism of EEPROM is EPRO
The same is true for M. The above-mentioned Fowler-Nordheim (FφN) tunneling is a phenomenon in which the current density passing through the gate oxide film increases as the electric field strength increases. Injection and emission are made possible by electric field control.

On the other hand, transistors used in semiconductor devices are becoming smaller due to the demands for high speed and high integration, and the gate length of transistors is becoming shorter, causing the problem of deterioration of the gate insulating film due to hot carriers. . Therefore, in order to alleviate the hot carrier effect near the drain, GDD (Gradually Doped Drain), in which the concentration profile of the drain is gradually changed, is used.
) structure or a portion with a low doping concentration is provided between the original source/drain and gate electrode (LDD).
tly Doped Drain) structure has been proposed. In particular, in the case of an n-channel transistor with a gate length of 1.2 μm or less, an LDD structure is essential.

FIG. 6 is an element cross-sectional view showing the structure of a MOS transistor having an LDD structure. According to the figure, a gate electrode 23 is formed on a gate insulating film 22 formed on a p-type substrate 21, and a silicon oxide film is formed on the side walls of this gate electrode 23 with an insulating film 24 interposed therebetween. A layer 25 is formed.

Then, this silicon oxide film layer 25 is formed on the surface of the semiconductor substrate.
A source region 26 and a drain region 27, which are n-type regions, are formed on both sides of the n-type region. Areas 28 and 2
9 are formed respectively. These n- regions 28 and 29 alleviate the hot carrier effect near the drain 27.

FIG. 7 is a step-by-step sectional view illustrating a method for obtaining the configuration shown in FIG. 5.

First, a p-type substrate 51 is prepared, a silicon oxide film 52 is formed on its surface by thermal oxidation, etc., one layer of polycrystalline silicon is deposited thereon, and this is patterned to form a gate electrode 5.
Get 3. An oxide film 54 is formed on the surface of this gate electrode 53. Next, using 53 as a mask, ions of, for example, phosphorus are implanted into the entire surface of the gate electrode at a dose of about 2 x 10' am-2 to form n- regions 55 and 56 (FIG. 7(a)). Next, a silicon oxide film 57 is deposited on the entire surface by the CVD method (FIG. 7(b)), and this is etched back by reactive ion etching (RIE) to form a silicon oxide film 58 only on the side walls of the gate electrode. It is left to remain (Fig. 7(C)). In this state, add 5x1015c of arsenic.
When ions are implanted over the entire surface with a dose of about IT+-2, a source region 59 and a drain region 60, which are n+ regions, are formed.
is formed, and a transistor with an LDD structure is completed (FIG. 7(d)).

Incidentally, in recent years, with the diversification of demands for semiconductor devices, there has been an increasing demand for semiconductor devices in which both a logic circuit such as a CPU and a memory element are formed on the same semiconductor substrate. Among these, MOS transistors constituting logic circuits are becoming increasingly finer due to demands for high speed, and it is essential to employ the above-mentioned LDD structure. On the other hand, although such a structure is not necessary in a nonvolatile memory element, if both are formed on the same substrate, there is a process to obtain an LDD structure, so the sidewall of the cell transistor of the nonvolatile memory element is A silicon oxide film is also formed on the surface. Heavy metal ions, alkali metal ions, etc. may be mixed into the silicon oxide film thus formed during the deposition process. In particular, alkali metal ions such as Na are collected by the electrons accumulated in the floating gate, and some of the electrons released by ultraviolet light are then captured by the positive charges of the alkali metal ions, but some electrons remain in the floating gate. However, after positively charged alkali metal ions diffuse over time, data may be reversed due to electrons remaining in the floating gate.

(Problems to be Solved by the Invention) As described above, in the conventional semiconductor device in which a MOS transistor and a non-volatile memory element are formed on the same substrate, data is There is a problem in that reliability as a non-volatile memory element may be lacking due to the inability to maintain the temperature.

The present invention has been made to solve these problems, and it is possible to form a highly reliable non-volatile memory element and a highly integrated transistor on the same semiconductor substrate without causing alkali metal contamination on the sidewalls. The purpose of the present invention is to provide a semiconductor device and a method for manufacturing the same.

[Structure of the invention]

(Means for Solving the Problems) According to the semiconductor device according to the present invention, an MO of an LDD structure
An S transistor and a non-volatile memory element are formed on the same semiconductor substrate, and a floating gate and a control gate are connected to a stacked substrate through a side wall of a gate electrode of a MOS transistor and an insulating film in a cell transistor of a non-volatile memory element. The composite gate is characterized by having a layer made of an oxide film doped with impurities on the sidewalls of the composite gate.

Further, according to the method for manufacturing a semiconductor device according to the present invention,
A step of forming a gate oxide film on a semiconductor substrate, and a step of depositing and patterning a first electrode material that will become a gate of a MOS transistor and a floating gate of a cell transistor of a nonvolatile memory element on this gate oxide film. After forming an insulating film on the surface of the floating gate in the cell transistor region, depositing a second electrode material that will become the control gate and patterning it to form a composite gate of the cell transistor, and forming the gate of the MOS transistor. A process of implanting low-concentration ions into the surface of a semiconductor substrate as an ion implantation mask, a process of forming an oxide film doped with impurities over the entire surface, and etching back this impurity-doped oxide film by anisotropic etching to form a MOS. The process includes a process in which ions remain only on the sidewalls of the transistor gate and the composite gate of the cell transistor, and a process in which ions are implanted at a high concentration into the semiconductor substrate surface using the impurity-doped oxide film remaining on the sidewalls as an ion implantation mask. It is characterized by

(Function) There is also an LDD on the side wall of the cell transistor of the nonvolatile memory element.
An oxide film doped with impurities for the structure (doped oxide) is formed, and this doped oxide either does not contain any alkali metal or even if it contains alkali metal ions, the alkali metal ions do not move as mobile ions. ,
Problems such as data inversion do not occur.

Furthermore, in the method of the present invention for obtaining such a structure, the doped oxide for creating the LDD structure is simultaneously formed on the sidewall of the composite gate of the cell transistor of the nonvolatile memory element, so that the doped oxide is formed on the same substrate. A CPU and a nonvolatile memory element can be reliably formed at the same time.

(Examples) Hereinafter, some embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a process-by-step cross-sectional view showing an embodiment of the method for manufacturing a semiconductor device according to the present invention, and FIG. 1(g) is an EPRO
This figure shows the completed state of this embodiment, which is equipped with M and CPU-t-.

First, a field oxide film 102 for element isolation and a first gate oxide film 103 having a thickness of, for example, 250 μm are formed by a known method on a p-type semiconductor substrate doped with boron to a concentration of about 1015 cITl-3. Then, a polycrystalline silicon layer is deposited on the entire surface and patterned to form a gate electrode 104 in the CPU section.
The polycrystalline silicon layer 105 is left as it is without being etched (FIG. 1(a)).

Next, heating is performed to oxidize the surfaces of the gate electrode 104 and the polycrystalline silicon layer 105 to form second gate oxide films 106 and 107 to a thickness of approximately 500 mm, and a polycrystalline silicon layer 108 is further formed over the entire surface. Deposits thickly (Fig. 1(b))
.

Subsequently, polycrystalline silicon layers 105 and 108 are patterned to form a composite gate of the EPROM section. As a result, in the EPROM section, the polycrystalline silicon layer 10
5 serves as a floating gate, and the polycrystalline silicon layer 108 serves as a control gate, and the polycrystalline silicon layer 108 is completely removed in the transistor portion (FIG. 1(C)).

Next, using the gate electrode 104 of the CPU section and the composite gate of the EPROM section as part of a mask, ion implantation of, for example, phosphorus is performed at a dose of about 2 x 10'''cm-2.
N- diffusion regions 109 and 110 are formed, and then, for example, arsenic is ion-implanted at a dose of about 5×10 15 cm −2 to form the source 111 and drain 1 of the n + diffusion regions.
form 12.

Next, an insulating oxide film 113 is formed around the composite gate of the EPROM section, and then a phosphorus silicate glass (PSG) 114, which is a silicon oxide film doped with phosphorus, is formed by CVD.
The PSG layer 115 is deposited on the entire surface using the D method (FIG. 1(e)), and then etched back using reactive ion etching (RIE) to form a PSG layer 115 on only the side walls of each gate electrode.
116°, 117', and 118 remain (Fig. 1(f)
).

Finally, arsenic is applied to only the CPU part at a dose of 5 using the gate electrode 104 and the PSG layers 115 and 116 as part of the mask.
Ion implantation was performed at approximately
A source 119 and a drain 120 of the diffusion region are formed (FIG. 1(g)).

FIG. 2 is a cross-sectional view of an element according to steps showing another embodiment of the present invention, in which case a FLOT having a tunnel diode is shown.
An example of an OX type EEPROM is shown.

First, a field oxide film 202 for element isolation is formed by a known method on a p-type semiconductor substrate 201 doped with boron to a concentration of about 1015 cm-3, and then thermally oxidized to
In the PU part, the first gate oxide film 2 has a thickness of, for example, 250 mm.
03 is formed, and a second gate oxide film 204 having a thickness of about 400 wafers is formed in the EEPROM section. At this stage, an n+ diffusion layer 205 is formed in a portion corresponding to the drain region of the cell transistor. Then, a part of the second gate oxide film 204 is removed by etching, and a third gate oxide film 205 having a thickness of about 100 mm is formed thereon (FIG. 2(a)).

Next, a polycrystalline silicon layer is deposited on the entire surface and patterned to form a gate electrode 207 in the CPU section.
In the EEPROM section, the polycrystalline silicon layer 208 is left as it is without being etched (FIG. 2(b)).

Next, heating is performed to oxidize the surfaces of the gate electrode 207 and the polycrystalline silicon layer 208 to form a fourth gate oxide film with a thickness of about 500A, and a thick polycrystalline silicon layer 211 is further formed over the entire surface ( Figure 2 (C)).

Subsequently, polycrystalline silicon layers 208 and 211 are patterned to include a third gate oxide film at their ends to form a composite gate of the EPROM section. As a result, in the EEPROM part, the polycrystalline silicon layer 2
08 serves as a floating gate, the polycrystalline silicon layer 211 serves as a control gate, and the polycrystalline silicon layer 108 is completely removed in the CPU section. A selection gate 212 for selecting cell transistors to be written and erased simultaneously at this time.
(Fig. 2(d)). In addition, at this time, the EPROM
section selection gate 212 and CPU section gate electrode 20
The polycrystalline silicon above 7 is removed.

Next, in the CPU section, using the gate electrode 207 as an ion implantation mask, ions of, for example, phosphorus are implanted at a dose of about 2x1013clTl-2, and n
- Forming diffusion regions 213 and 214 followed by EEP
In the ROM part, for example, arsenic is implanted at a dose of 5 x 10 using the composite gate and the selection gate 212 as an ion implantation mask.
Ion implantation is performed at a depth of about 15 cm-2 to form the source 215, 216 and drain 217 of the n+ diffusion region (
Figure 2(e)).

Next, phosphorus silicate glass (PSG) 218, which is a silicon oxide film doped with phosphorus, is deposited on the entire surface using the CVD method (Fig. 2 (f)), and this is etched back using reactive ion etching (RIE). This allows the PSG layers 219, 220, 221 .
222 remains (Fig. 2(g)).

Finally, arsenic is dosed only in the CPU section using the gate electrode 207 and the PSG layers 219 and 220 as part of the mask.
Ion implantation was performed at approximately 5 x 10''cm-2.
The source 223 and drain 224, which are + diffusion regions, are formed, and at this time, the n+ diffusion region 22 is also formed in the EEPROM section.
5,226 (Fig. 2(g)).

As described above, in these embodiments, a transistor with an LDD structure is formed in the CPU section, and a memory cell having a PSG film on the sidewall in place of the conventional CVD silicon oxide film is formed in the EPROM section or EEPROM. Become.

In such a structure, the short channel effect of the LDD structure transistor is effectively prevented, and in the EPROM part, the PSG provided on the side wall does not contain an alkali metal, or even if it contains it, it does not become a mobile ion, so the memory content data is No problems such as changes will occur.

FIG. 3 shows an example of performance improvement of a semiconductor device according to the present invention.

The figure shows that the initial value Vth(0) of the threshold value of the cell transistor of the EPROM shown in FIG.
This is a graph showing how the time-lapse value Vth(t) changes when left at ℃, where white dots indicate the conventional device and black dots indicate the device of the present invention. . According to this, it can be seen that as a result of applying the present invention, threshold fluctuations are extremely reduced, and the influence of alkali ions is reduced. In addition, the same result is E
This has also been obtained in the case of EPROM.

In the above embodiment, the film formed on the side wall is PSG.
Although it is a film, any doped oxide can be used, for example, BPSG or the like can be used.

In addition, anisotropic etching other than RIE can be used for the etchback. [Effects of the Invention] As explained in detail based on the embodiments above, according to the semiconductor device of the present invention, etching can be performed on the same substrate. It is equipped with a non-volatile memory element that includes a formed LDD structure transistor and a cell transistor having a doped oxide film on the sidewall, and since the sidewall of the cell transistor is not affected by alkali metal contamination, data inversion etc. Does not cause any problems.

Further, according to the method for manufacturing a semiconductor device according to the present invention,
The semiconductor device described above can be manufactured reliably.

[Brief explanation of the drawing]

FIG. 1 is a step-by-step cross-sectional view showing an ion implantation embodiment of the semiconductor device manufacturing method according to the present invention, and FIG. 2 is a step-by-step cross-sectional view showing another example of the semiconductor device manufacturing method according to the present invention.
FIG. 3 is a graph showing the effects of the present invention, FIG. 4 is an element cross-sectional view showing the structure of a conventional EPROM, FIG. 5 is a cross-sectional view of an element showing the structure of a conventional EEPROM, and FIG. 6 is an LDD.
FIG. 7 is a cross-sectional view showing a method for obtaining the structure shown in FIG. 6. 101.201...Semiconductor substrate, 102,202...
・Field oxide film, 103, 107, 203° 204
．． 210... Gate oxide film, 104, 207... Gate electrode, 105, 208... Floating gate, 108.
211...Control gate, 109,110°213.2
14...n-diffusion region, 111,112°215.2
16,217...n Diffusion region, 114°218...
・Silicon oxide film doped with impurities, 115.116
,117,118,219゜220.221,222・
・Remaining silicon oxide film, 223, 224, 225
．． 226...n diffusion region, 206... tunnel oxide film. Applicant's agent Yutaka Sato / ``A slave ■sumont (H) 3 figures, 4 figures, 6 figures, 7 figures, procedural amendment form) % formula % 1. Indication of the case 1986 patent Application No. 276647 2, Name of the invention Semiconductor device and its manufacturing method 3, Relationship with the amended case Patent applicant (307) Toshiba Corporation 4, Agent (zip code 100) December 1988 24th (shipped January 26, 1986) 6. Drawings subject to correction

Claims (1)

[Claims] 1. In a semiconductor device in which a MOS transistor with an LDD structure and a nonvolatile memory element are formed on the same semiconductor substrate, a side wall portion of a gate electrode of the MOS transistor and a nonvolatile memory element are provided. A semiconductor device characterized in that a layer made of an oxide film doped with an impurity is provided on a side wall portion of a composite gate in which a floating gate and a control gate are laminated with an insulating film interposed therebetween in a cell transistor. 2. The semiconductor device according to claim 1, wherein the nonvolatile memory element is an EPROM element. 3. The semiconductor device according to claim 1, wherein the nonvolatile memory element is an EEPROM element. 4. The semiconductor device according to claim 2 or 3, wherein the oxide film doped with impurities is phosphosilicate glass (PSG). 5. The semiconductor device according to claim 2 or 3, wherein the oxide film doped with impurities is boron phosphosilicate glass (BPSG). 6. Forming a gate oxide film on the semiconductor substrate, depositing a first electrode material that will become the gate of the MOS transistor and the floating gate of the cell transistor of the nonvolatile memory element on this gate oxide film, and patterning it. After forming an insulating film on the surface of the floating gate in the cell transistor region, depositing a second electrode material that will become a control gate and patterning it to form a composite gate of the cell transistor; A process of implanting low concentration ions into the surface of the semiconductor substrate using the gate of a MOS transistor as an ion implantation mask, a process of forming an oxide film doped with impurities over the entire surface, and anisotropic etching of the oxide film doped with impurities. etching back to leave only the sidewalls of the gate of the MOS transistor and the composite gate of the cell transistor; and using the impurity-doped oxide film remaining on the sidewalls as an ion implantation mask to etch back the surface of the semiconductor substrate. A method for manufacturing a semiconductor device, comprising a step of implanting high concentration ions. 7. The process of forming an oxide film doped with impurities is CVD.
Claim 6 characterized in that it is made by law
A method for manufacturing a semiconductor device according to section 1. 8. The method of manufacturing a semiconductor device according to claim 6 or 7, wherein the anisotropic etching is reactive ion etching. 9. A sixth aspect of the present invention includes the step of etching away a part of the gate oxide film in the cell transistor region and forming a second gate oxide film thinner than the gate oxide film in this part. 9. A method for manufacturing a semiconductor device according to any one of items 8 to 8.