JPH06151833A - Semiconductor device and its manufacture - Google Patents

Abstract

PURPOSE:To provide a semiconductor device with resistance against deterioration caused by a carrier capturing center and its manufacturing method. CONSTITUTION:A gate oxide film 13 is provided with an ONO film 13b with a large barrier energy for a substrate 1 at areas near drain regions 7b and 10b. The energy barrier suppresses capturing of DAHC by the gate oxide film. A normal oxide film 13a is provided at areas which are not close to the drain regions 7b and 10b. Therefore, the operation speed of a MOS transistor is reduced as compared with a case when the ONO film with a high dielectric constant, is uniformly adopted for the crate oxide film 13, thus suppressing the injection of carriers into the oxide film without reducing the operation speed of a semiconductor device.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a technique for preventing deterioration due to hot carriers.

[0002]

2. Description of the Related Art MOS (Metal Oxide Se)
As shown in FIG. 15, the transistor is composed of an N ⁻ source / drain region 7, an N ⁺ source / drain region 10, a gate oxide film 4 and a gate 5 electrode. A manufacturing process for obtaining such a structure is shown in FIGS.

As shown in FIG. 12, first, a LOCOS oxide film 2 is formed on a semiconductor substrate 1, and then channel ion implantation 3 is performed. Then, after forming the gate oxide film 4 as shown in FIG. 13, polysilicon is deposited and patterned as shown in FIG. 14 to form a gate electrode 5, and N ⁻ ion implantation 6 is performed to form an N ⁻ source. / Drain region 7 is formed. Next, a side wall film 8 is formed, N ⁺ ion implantation 9 is performed to form N ⁺ source / drain regions 10, and a basic structure of an n-type MOSFET is completed (FIG. 1).
5).

While devices are being miniaturized in order to realize high-density integrated circuits, the operating voltage of the devices is TTL.
(Transistor-Transistor Lo
Since the electric field in the gate oxide film 4 or the semiconductor substrate 1 is effectively increased with the miniaturization of the device, the electric field is effectively increased.

Therefore, carriers (electrons or holes) traveling in the substrate below the gate oxide film 4 are accelerated by the electric field and have high energy, and some of them act as an energy barrier at the substrate / oxide film interface during channel traveling. It gets over and is captured by the capture center in the gate oxide film 4. This type of carrier is CHE (Channel Hot Electron)
It is called.

In addition to this, carriers having a high energy that have reached the N ⁺ drain 10 collide with impurity atoms to newly generate electron-hole pairs, and a part of them is formed in the semiconductor substrate 1 and the gate oxide film 4. It is trapped at the trap center in the gate oxide film 4 by overcoming the energy barrier at the interface. This type of carrier is DAHC (Drain Avalanche Ho)
t Carrier).

In FIG. 16, in addition to the trap center 11 described above, an interface level 12 existing in the gate oxide film 4 and an interface fixed charge 1 are present.
3 and mobile ions 14. When the semiconductor substrate 1 is made of silicon and the gate oxide film 4 is made of a silicon oxide film, the cause of the presence of the interface state 12 is the distorted Si—O bond or unsaturated bond of silicon.

[0008]

[Chemical 1]

[0009] The mobile ion 14 is an alkaline ion such as sodium ion (Na ⁺ ) or potassium ion (K ⁺ ) and has a charge Q _m . The charges possessed by these ions affect the electrical characteristics of the MOS transistor.

The electrical characteristics of the MOS transistor are given by the equation 1 in the triode region.

[0011]

[Equation 1]

Where I _D is drain current, W is gate width, L is gate length, μ is mobility, C _OX is gate capacitance, and V is
_G is the gate voltage, V _T is the gate threshold voltage, and V _D is the drain voltage.

FIG. 17 shows the gate voltage V of the drain current I _D.
It is a graph showing dependence on _G a (I _D -V _G characteristics). Interface order 12, interface fixed charge 13, mobile ion 1
The basic characteristic when 4 is not present is as shown in the curve 15.

In the case of an n-type MOS transistor, when the interface fixed charge 13 (charge amount Q _O ) is generated, the gate threshold voltage V _T is affected by the electric flux generated from this charge and the gate threshold voltage V _T is Q _O.
/ It decreases by C _OX . Therefore, the I _D -V _G characteristic shifts to the negative side of the gate voltage, as shown by the curve 16 in FIG. 17, compared to the basic characteristic represented by the curve 15.

When the interface level 12 is generated, it traps a part of free carriers and reduces the amount of charge that can move freely. Therefore, the I _D -V _G characteristic is as shown by the curve 17 in FIG. The mutual conductance is lower than the basic characteristic represented by the curve 15.

In the gate oxide film 4, since the charge has a distribution ρ (x) in the thickness direction, the gate threshold voltage V
_T becomes

[0017]

[Equation 2]

Here, φ _MS is the work function difference between the semiconductor and the metal, _tox is the thickness of the gate oxide film 4, Q _D is the charge amount of the inversion layer, Q _B is the charge amount of the depletion layer, and C _OX is The size of the capacitance formed by the gate oxide film 4, φ _F, is the Fermi potential.
When the trap center 11 is in the gate oxide film 4, the trap center 11 is in a negatively charged state when the electrons that have crossed the energy barrier at the interface between the semiconductor prayer 1 and the gate oxide film 4 are trapped by the trap center 11. (Charge amount Q _t ), the gate threshold voltage V _T fluctuates according to equation 2.

When the semiconductor substrate 1 is made of silicon and the gate oxide film 4 is made of a silicon oxide film, the trap center 11 is a trap center caused by moisture, a trap center by high temperature heat treatment, and in the oxide film. It is known to be a trapping center or the like generated by carrier injection into. The silicon and the silicon oxide film will be described below.

First, regarding the trapping center caused by water,
Moisture (H ₂ O) in the oxide film is high temperature (Si-O-Si)
Reacts with to generate structural defects such as SiOH (silanol) and SiH. Among them, it is reported that SiOH acts as a trap center 11 for electrons, but SiH does not serve as a trap center for carriers. It has been reported that the capture center of SiOH is remarkably reduced when heat-treated in a non-oxidizing atmosphere at 1000 ° C. or higher.

In addition, in a normal manufacturing process of a MOS transistor on a silicon wafer, since the polysilicon is deposited at a high temperature after the gate oxide film 4 is formed, it is considered that the trap centers due to the water almost disappear.

On the other hand, regarding the trap center by the high temperature heat treatment, after the OH groups and oxygen ions in the silicon oxide film are eliminated, unsaturated bonds (chemical formula 1) and oxygen vacancies of silicon atoms are generated.

[0023]

[Chemical 2]

A structural defect due to is generated. This structural defect acts as a trap center 11 for electrons.

In addition, as the trapping center by the high temperature heat treatment, there is a trapping center by the distorted Si—O bond existing near the interface between the silicon substrate and the silicon oxide film. This trapping center acts on holes. The trap centers formed by the high temperature heat treatment increase in density when the high temperature heat treatment is performed in a non-oxidizing atmosphere.

Next, regarding the trap center generated by carrier injection into the oxide film, it is possible to increase the number of unsaturated silicon atoms near the interface by such injection, which is XPS (X-ray Photoemission).
It has been revealed by the measurement of Spectroscopy).

In the conventional MOS transistor manufacturing process, it is known that the interface state 12 and the interface fixed charge 13 are greatly reduced by heat treatment in a hydrogen atmosphere before forming the gate oxide film 4. By this process, MO
The initial operation of the S-transistor can be controlled by the gate electrode 5 without being affected by the interface level 12 and the interface fixed charge 13, and the variation of the gate threshold voltage V _T within the wafer is reduced. However, when hot carriers are injected into the gate oxide film 4, unsaturated silicon atoms are generated near the interface between the semiconductor substrate 1 and the gate oxide film 4. If this is left as it is, the gate threshold voltage V _T fluctuates with the passage of time, which causes a malfunction.

In addition, the conventional flash EEPROM (E
electrically-Erasable and
In the programmable ROM), the floating gate 1 is formed in the gate oxide film 18 as shown in FIG.
9 and a control gate 20 are formed. If a uniform SiO ₂ film is used for the gate oxide film 18, F between the floating gate 19 and the source region 21 at the time of erasing data is used.
The gate oxide film 14 is deteriorated by an N (Fowler-Nordheim) tunnel current.

[0029]

The conventional semiconductor device and the method of manufacturing the same are configured as described above. When the element is miniaturized, the electric field in the semiconductor substrate becomes high, and the carriers are accelerated by the electric field, so that high energy is generated. As a result, a trapping center for carriers due to unsaturated silicon atoms is newly formed near the semiconductor substrate / gate oxide film energy barrier and near the semiconductor substrate / oxide film interface, which leads to deterioration of the operation of the semiconductor device. There was a point.

The present invention has been made in order to solve the above-mentioned problems, and even if it is operated for a long time, carriers are not injected into the oxide film, and unsaturated atoms near the semiconductor substrate / oxide film interface remain. An object of the present invention is to provide a semiconductor device and a method for manufacturing the semiconductor device, which can avoid deterioration of operation due to generation.

[0031]

A semiconductor device according to the present invention includes at least a semiconductor substrate, first and second semiconductor layers formed on the upper surface of the semiconductor substrate and spaced apart from each other, and at least the upper surface of the semiconductor substrate. A gate oxide film formed on a portion sandwiched between the first and second semiconductor layers and a gate electrode facing the semiconductor substrate via the gate oxide film are provided. The energy barrier formed by the gate oxide film and the upper surface of the semiconductor substrate is increased at least in the vicinity of the first semiconductor layer.

Preferably, the gate oxide film is formed at least in the vicinity of the first semiconductor layer, has a relatively high energy barrier and a relatively high dielectric constant, the first semiconductor layer and the second semiconductor layer. A second film which is formed near the middle of the semiconductor layer and has a relatively low energy barrier and a relatively low dielectric constant.

More preferably, the first film is also formed in the vicinity of the second semiconductor layer.

Alternatively, the first film is substantially ONO (O
xide-Nitride-Oxide) film.

The first aspect of the method for manufacturing a semiconductor device according to the present invention is: (a) a step of forming first and second semiconductor layers formed apart from each other on the upper surface of the semiconductor substrate; and (b) A step of forming a gate oxide film formed on at least a portion sandwiched by the first and second semiconductor layers on the upper surface of the semiconductor substrate; and (c) at least in the vicinity of the first semiconductor layer of the gate oxide film. The method includes the steps of selectively introducing impurities by ion implantation, and (d) forming a gate electrode facing the semiconductor substrate via the gate oxide film.

Desirably, the impurities include at least one of nitrogen, phosphorus and arsenic.

Alternatively, as a second aspect of the method for producing a semiconductor device according to the present invention, a gate containing nitrogen and oxygen is used instead of the step (c) in the first aspect of the method for producing a semiconductor device. A step of nitriding and oxidizing both ends of the oxide film may be provided.

A third aspect of the method of manufacturing a semiconductor device according to the present invention is a method of manufacturing a semiconductor device in which a plurality of MOS structure elements are formed on a semiconductor substrate. And
The method includes (a) a step of forming a gate oxide film on the upper surface of a semiconductor substrate, and (b) a step of ion-implanting an impurity into a region where the film thickness is locally thick in the gate oxide film.

[0039]

In the semiconductor device according to the present invention, the gate oxide film enhances the energy barrier formed by the gate oxide film and the upper surface of the semiconductor substrate in the vicinity of the first semiconductor layer, thereby improving CH.
Suppresses the generation of E and DAHC. The ONO film raises this energy barrier.

In order to avoid the performance deterioration of the semiconductor device caused by increasing the energy barrier and increasing the dielectric constant,
The second film has a low dielectric constant. By forming the first film not only in the vicinity of the first semiconductor layer but also in the vicinity of the second semiconductor layer, the device can be easily used.

The selective ion implantation in the first aspect of the method for manufacturing a semiconductor device according to the present invention can raise the energy barrier in a part of the gate oxide film.

Nitrogen oxidation using a gas containing nitrogen and oxygen in the second embodiment of the method for manufacturing a semiconductor device according to the present invention further suppresses the introduction of defects.

Further, in the third aspect of the method of manufacturing a semiconductor device according to the present invention, the ion implantation makes the capacitance formed by the gate oxide film uniform.

[0044]

【Example】

First embodiment. FIG. 1 shows a sectional view of a MOS transistor according to a first embodiment of the present invention. In the upper surface of the silicon substrate 1, an N ⁻ source region 7a, an N ⁺ source region 10a, an N ⁻ drain region 7b and an N ⁺ drain region 10b are formed. A gate oxide film 13 is formed on the upper surface of silicon substrate 1 so as to extend over N ⁻ source region 7a and N ⁻ drain region 7b. The gate electrode 5 is formed on the gate oxide film 13, and the sidewall 8 is formed beside them.
Each is formed.

ONO (Oxide-Nitride-O
The xide) film has a higher energy barrier against electrons and holes than the SiO ₂ film. Therefore, the gate oxide film 1
If an ONO film is used for 3, DAH near the drain region
Implantation of C into the gate oxide film 13 is less likely to occur as compared with the case where a SiO ₂ film is used for the gate oxide film 13, and deterioration of the gate oxide film 13 is suppressed.

[0046] On the other hand, ONO film is compared to the SiO ₂ film,
High dielectric constant. Therefore, if the gate oxide film 13 is made of a uniform ONO film, the operating speed of the MOS transistor becomes slow.

Therefore, in this embodiment, in the MOS transistor, in order to suppress the injection of DAHC into the gate oxide film 13, a part 13b of the gate oxide film 13 is formed of an ONO film in the vicinity of the N ⁻ drain region 7b. ing.
Then, in order to prevent the operating speed of the MOS transistor from deteriorating, the other portion 13a of the gate oxide film 13 is formed of a SiO ₂ film.

With this structure, further advantages are produced. Since the ONO film has a larger dielectric constant than the SiO ₂ film, the amount of charges near the pinch-off point generated near the N ⁻ drain region 7b is larger than that when the SiO ₂ film is used as the part 13b of the gate oxide film. Become. For this reason, the drain current and the current drive ratio increase.

Second embodiment. FIG. 2 is a sectional view of a cell transistor of a flash EEPROM which is a second embodiment of the present invention. A source region 21 and a drain region 22 are formed in the upper surface of the semiconductor substrate 1, and a gate oxide film 18 is formed on the upper surface of the semiconductor substrate 1 from the source region 21 to the drain region 22. And the gate oxide film 18
A floating gate 19 and a control gate 20 are formed inside.

In this embodiment, the gate oxide film 18 is formed of the ONO film 18a near the source region 21, and the gate oxide film 18 is formed of the SiO ₂ film 18 in other portions.
It consists of b. Therefore, the deterioration due to the FN tunnel current between the source region 21 and the floating gate 19 at the time of erasing data is suppressed as compared with the case where the gate oxide film 18 is composed of only the SiO ₂ film.

If the gate oxide film 18 has a uniform O
The NO film makes it difficult for the DAHC injection current to flow between the floating gate 19 and the drain region 22 at the time of writing data, and the writing efficiency becomes worse than that when the gate oxide film 18 is made of the SiO ₂ film. Also, O
Since the NO film has a larger dielectric constant than the SiO ₂ film, the capacitance between the floating gate 19 and the semiconductor substrate 1 becomes large, and the operation speed becomes slow.

Therefore, the gate oxide film 18 is formed of the ONO film 18a only in the vicinity of the source region 21, and the SiO ₂ film 1 is formed in other portions, for example, in the vicinity of the drain region 22.
It is composed of 8b.

That is, CHE and DA between the drain region 22 and the floating gate 19 during data writing.
It is possible to prevent the HC injection from being hindered and suppress the deterioration of the writing efficiency, while suppressing the deterioration due to the FN tunnel current between the source region 21 and the floating gate 19 at the time of data erasing.

Third Embodiment. 3 to 6 show a method of manufacturing a semiconductor device according to a third embodiment of the present invention. First, Fig. 3
As shown in, an oxide film 4a and a polysilicon film 5a are formed on the upper main surface of the semiconductor substrate 1. For example, the oxide film 4a is 7n
The polysilicon film 5a is formed to have a thickness of m, and the polysilicon film 5a is formed to have a thickness of 350 nm. Next, as shown in FIG. 4, the oxide film 4a and the polysilicon film 5a are patterned to form a gate oxide film 4 and a gate electrode 5 respectively.

Then, as shown in FIG. 5, a portion of the semiconductor substrate 1 where a source region is to be formed in the future and the upper surface of the gate electrode 5 are covered with a resist 11. The gate oxide film 4 (drain end) and the gate electrode 5 near the future formation of the drain region in the semiconductor substrate 1 are not covered with the resist 11. After this, for example, nitrogen ions are applied with an energy of 10 keV and a dose of 2.0 × 10 ¹³ / c.
Diagonal implantation is performed at m ² and an incident angle of 45 ° to introduce nitrogen ions into the drain end of the gate oxide film 4.

After that, the resist 11 is removed and a heat treatment is carried out, so that the ONO film 1 is formed on the drain end of the gate oxide film 4.
3b is formed. The gate oxide film other than the drain end is left as it is and becomes a part 13a of the gate oxide film (FIG. 6).

Through these steps, the gate oxide film 13 having a non-uniform dielectric constant in the lateral direction is formed. The same effect can be obtained by selectively implanting other ions such as phosphorus and arsenic ions into the gate oxide film 4 by ion implantation.

After that, the N ⁻ source region 7a, the N ⁺ source region 10a, and the N ⁻ drain region 7 are formed by a known technique.
By forming the b and N ⁺ drain regions 10b and the like, the MOS transistor of the first embodiment shown in FIG. 1 can be obtained.

Alternatively, by forming the source region 21, the drain region 22, the floating gate 19, the control gate 20, etc., the cell transistor of the flash EEPROM of the second embodiment shown in FIG. 2 can be obtained.

Fourth Embodiment. 7 to 9 show a method of manufacturing a semiconductor device according to a fourth embodiment of the present invention. In the third embodiment, since nitrogen ions are introduced into the gate oxide film 4 by ion implantation, there is a problem in that a large number of defects that become carrier trapping centers are introduced into the gate oxide film 4. In this embodiment, in order to avoid this, nitriding oxidation by gas is performed.

First, the gate electrode 5 is made of polysilicon.
After forming (FIG. 7), nitrogen gas and oxygen gas are caused to flow in the furnace at the time of forming the sidewall. As a result, both ends of the gate oxide film 4 are nitrided and oxidized, ONO films 13b are formed on both ends of the gate oxide film 13, and the others are left as the oxide film 13a. Here, "nitridation and oxidation" means that nitridation and oxidation are performed simultaneously or alternately. For example, in forming the gate oxide film 13, oxygen gas, nitrogen gas, and oxygen gas are introduced in this order, but these may or may not include nitrogen gas, oxygen gas, and nitrogen gas, respectively.

After this, for example, TEOS (Tetra
Ethoxy Silane) is flown to deposit the oxide film 8a (FIG. 8).

Further, as shown in FIG. 9, by anisotropic etching by RIE, the gate oxide film 13 having the ONO films 13b at both ends and the sidewall 8 having the ONO film 13b at the bottom surface are formed.

Thereafter, the N ⁻ source / drain region 7, the N ⁺ source / drain region 10 and the like are formed by a known technique to obtain a MOS transistor as shown in FIG. The MOS transistor described in the first embodiment and shown in FIG. 1 has an advantage that it is not necessary to use the source and the drain separately.

Fifth embodiment. FIG. 11 is a sectional view showing a semiconductor manufacturing method according to the fifth embodiment of the present invention. When a MOS transistor is formed on one main surface of the semiconductor wafer 100, the thickness of the gate oxide film may vary within the wafer 1. This may cause variations in electrical characteristics among MOS transistors on the same wafer.

Therefore, the gate oxide film 30 formed on the wafer 1 is formed for the purpose of suppressing this kind of variation in electrical characteristics.
By selectively performing ion implantation 40 of ions such as nitrogen to give a distribution to the dielectric constant of the gate oxide film, variations in electrical characteristics due to variations in film thickness are suppressed. Specifically, in order to suppress an increase in capacitance, the ion implantation 40 is performed in a portion where the gate oxide film 30 is thick.

[0067]

According to the semiconductor device of the present invention,
Injection of DAHC into the gate oxide film in the vicinity of the first semiconductor layer is suppressed. Therefore, fluctuations in gate threshold voltage and deterioration in performance such as reduction in mutual conductance are suppressed.

Further, the DAHC does not raise the energy barrier of the gate oxide film but raises the energy barrier of the problematic portion, so that it is not necessary to raise the energy barrier in other gate oxide films. Therefore, it is possible to solve the problems of DAHC and FN tunnel current without increasing the gate capacitance and thus slowing the operating speed.

In particular, since the ONO film has a larger dielectric constant than a normal oxide film, the amount of charges near the pinch-off point generated near the first semiconductor layer is smaller when the ONO film is used as the gate oxide film. It will be larger than when used. Therefore, there is an advantage that the current driving force becomes large.

According to the first and second aspects of the method of manufacturing a semiconductor device of the present invention, the semiconductor device of the present invention can be obtained appropriately.

In particular, according to the second aspect, it is possible to suppress the introduction of defects that become carrier trapping centers.

Further, according to the third aspect of the method for manufacturing a semiconductor device of the present invention, it is possible to suppress the variation in the electrical characteristics of the semiconductor device due to the variation in the film thickness of the gate oxide film formed on the wafer. You can

[Brief description of drawings]

FIG. 1 is a sectional view of a MOS transistor according to a first embodiment of the present invention.

FIG. 2 is a flash EEP which is a second embodiment of the present invention.
It is sectional drawing of the cell transistor of ROM memory.

FIG. 3 is a sectional view showing a third embodiment of the present invention in the order of steps.

FIG. 4 is a sectional view showing a third embodiment of the present invention in the order of steps.

FIG. 5 is a sectional view showing a third embodiment of the present invention in the order of steps.

FIG. 6 is a sectional view showing a third embodiment of the present invention in the order of steps.

FIG. 7 is a sectional view showing a fourth embodiment of the present invention in the order of steps.

FIG. 8 is a sectional view showing a fourth embodiment of the present invention in the order of steps.

FIG. 9 is a sectional view showing a fourth embodiment of the present invention in the order of steps.

FIG. 10 is a sectional view showing a fourth embodiment of the present invention in the order of steps.

FIG. 11 is a sectional view showing a fifth embodiment of the present invention in the order of steps.

FIG. 12 is a cross-sectional view showing a conventional MOS transistor manufacturing process in process order.

FIG. 13 is a cross-sectional view showing a conventional MOS transistor manufacturing process in process order.

FIG. 14 is a cross-sectional view showing the manufacturing process of the conventional MOS transistor in the order of processes.

FIG. 15 is a cross-sectional view showing a step-by-step process of manufacturing a conventional MOS transistor.

FIG. 16 is a schematic diagram showing trap centers, interface states, interface fixed charges, and mobile ions in a gate oxide film.

FIG. 17 is a graph showing electrical characteristics of a MOS transistor.

FIG. 18 is a cross-sectional view showing the structure of a conventional flash EEPROM memory cell transistor.

[Explanation of symbols]

1 Semiconductor Substrate 4 Gate Oxide Film 5 Polysilicon Gate 7 N ^- Source / Drain Region 7a N ^- Source Region 7b N ^- Drain Region 10 N ^- Source / Drain Region 10a N ⁺ Source Region 10b N ⁺ Drain Region 18 Gate Oxide Film 19 Floating gate 21 Source region 22 Drain region

[Procedure amendment]

[Submission date] April 8, 1993

[Procedure Amendment 1]

[Document name to be amended] Statement

[Correction target item name] 0066

[Correction method] Change

[Correction content]

Therefore, the gate oxide film 30 formed on the wafer 1 is formed for the purpose of suppressing this kind of variation in electrical characteristics.
By selectively performing ion implantation 40 of ions such as nitrogen to give a distribution to the dielectric constant of the gate oxide film, variations in electrical characteristics due to variations in film thickness are suppressed. Specifically, the ion implantation 40 the thickness of the gate oxide film 30 is in the thick portion.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location H01L 29/788 29/792 H01L 29/78 371

Claims (8)

[Claims] 1. A semiconductor substrate, first and second semiconductor layers formed on an upper surface of the semiconductor substrate and spaced apart from each other, and at least the first and second semiconductor layers of the upper surface of the semiconductor substrate. A gate oxide film formed on the sandwiched portion, and a gate electrode facing the semiconductor substrate via the gate oxide film, wherein the energy barrier formed by the gate oxide film and the upper surface of the semiconductor substrate is at least A semiconductor device elevated in the vicinity of the first semiconductor layer. 2. The gate oxide film is formed at least in the vicinity of the first semiconductor layer,
The first barrier layer has a relatively high energy barrier and a relatively high dielectric constant, and the first barrier layer is formed near the middle of the first semiconductor layer and the second semiconductor layer. The semiconductor device according to claim 1, further comprising a second film having a low dielectric constant. 3. The semiconductor device according to claim 2, wherein the first film is also formed in the vicinity of the second semiconductor layer. 4. The first film is substantially ONO (Oxi).
The semiconductor device according to claim 2, comprising a de-nitride-oxide film. 5. (a) a step of forming first and second semiconductor layers that are formed apart from each other on the upper surface of the semiconductor substrate; and (b) at least the first surface of the upper surface of the semiconductor substrate.
And a step of forming a gate oxide film formed on a portion sandwiched by the second semiconductor layer, and (c) selectively implanting impurities by ion implantation in at least the first semiconductor layer of the gate oxide film. A method of manufacturing a semiconductor device, comprising: a step of introducing; and (d) a step of forming a gate electrode facing the semiconductor substrate via the gate oxide film. 6. The method of manufacturing a semiconductor device according to claim 5, wherein the impurities include at least one of nitrogen, phosphorus and arsenic. 7. (a) a step of forming first and second semiconductor layers formed apart from each other on the upper surface of the semiconductor substrate; and (b) at least the first of the upper surfaces of the semiconductor substrate.
And a step of forming a gate oxide film formed on a portion sandwiched by the second semiconductor layer, and (c) nitrifying and oxidizing both ends of the gate oxide film using a gas containing nitrogen and oxygen. (D) forming a gate electrode facing the semiconductor substrate through the gate oxide film, and manufacturing a semiconductor device. 8. A method of manufacturing a semiconductor device, wherein a plurality of MOS structure elements are formed on a semiconductor substrate, the method comprising: (a) forming a gate oxide film on an upper surface of the semiconductor substrate; and (b) the gate. A step of ion-implanting impurities into a region where the film thickness is locally thick in the oxide film;
A method for manufacturing a semiconductor device, comprising: