JP2003133540A - Method for forming dot unit and method for manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for forming a dot unit containing Ge as a main component capable of simplifying steps and preventing characteristics of the quality of a device from being deteriorated. SOLUTION: The method for forming the dot unit comprises steps forming a lower oxide film 2 on an Si substrate 1, and forming an SiGe semiconductor thin film 3 on the film 2. The method further comprises steps of thermally oxidizing the substrate at 800 deg.C, and thereby forming an upper oxide film 4 from the SiGe semiconductor thin film 3. Thus, Ge included in the film 3 is segregated and aggregated near the interface between the oxide film 4 and the lower oxide film 2, and the dot unit 5 containing the Ge as the main component is formed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dot body forming method and a semiconductor device manufacturing method using the dot body.

[0002]

2. Description of the Related Art In the advanced information society of the 21st century, a huge amount of image and voice data will be handled even in portable information devices, so there is a need for high-capacity, high-speed nonvolatile memory with low power consumption. It is getting higher.

Ya-Chi from the University of California, Berkeley
n is a non-volatile memory, and is used as a metal-oxide film-semiconductor field effect transistor (MOSFET: Metal Ox).
ideSemiconductor Field Effect Transistor) with so-called “G” in which Ge quantum dots are embedded in the gate insulating film.
e Quantum Dot Memory ”in Reference 1 (International Elect
ron Devices Meeting 1998 Technical Digest, pp.115
(International Electron Devices
Meeting Technical digest 115 pages))
Have reported. Ge quantum dot memory is DRA
It is a memory device that has both the high speed of M and the non-volatility of a flash memory. The Ge quantum dot memory is capable of writing and erasing operations at high speed and at low voltage, and has a writing endurance capable of performing writing over 10 ⁹ times. At the present stage, the Ge quantum dot memory has been reported to have a retention time of 100,000 seconds or more, although it does not reach the data retention time of the flash memory of 10 years.

Here, a method of manufacturing the conventional Ge quantum dot memory described in the above-mentioned Document 1 will be described with reference to FIG.
A description will be given with reference to (a) to (g). FIG. 5 (a)-
FIG. 3G is a cross-sectional view showing a process up to forming Ge dots in the gate insulating film in the manufacturing process of the conventional Ge quantum dot memory.

First, in the step shown in FIG. 5A, Ge is ion-implanted into the Si substrate 101. Then, in the step shown in FIG. 5B, the oxide film 103 is formed on the substrate by heating the substrate to a temperature of 900 ° C. or higher and performing wet oxidation. At this time, a Ge segregation layer 102 in which Ge is segregated is formed at the interface between the oxide film 103 and the Si substrate 101.

Next, in the step shown in FIG. 5C, the oxide film 1 is formed.
03 is removed, and then the substrate is dry-oxidized at a temperature of 800 ° C. As a result, the Ge segregation layer 102 on the Si substrate 101 becomes the SiGe mixed crystal layer 102a, and the SiGe
An upper oxide film 104 is formed on the mixed crystal layer 102a. When forming the upper oxide film 104, Ge is Si
Since it is easy to segregate at the interface between the Ge mixed crystal layer 102a and the Si substrate 101, the G in the Ge mixed crystal layer 102a is easily separated.
e is difficult to diffuse into the upper oxide film 104.

Thereafter, in the step shown in FIG. 5D, when the substrate is kept at a low temperature of about 650 ° C. and wet-oxidized, Ge diffuses from the SiGe mixed crystal layer 102a into the upper oxide film 104 as the oxidation progresses. To produce Si _1-x Ge _x O ₂
The layer 105 is formed.

Next, in the step shown in FIG. 5E, the SiGe mixed crystal layer 102a and Si are oxidized by oxidizing the substrate.
_A lower oxide film 106 is formed between the _1-x Ge _x O ₂ layer 105. As a result, the Si _1-x Ge _x O ₂ layer 105 is interposed between the upper oxide film 104 and the lower oxide film 106.

Next, in the step shown in FIG. 5F, when the substrate is heat-treated in a nitrogen atmosphere at 900 ° C., Si
Ge atoms in the _1-x Ge _x O ₂ layer 105 aggregate to form G in the oxide film composed of the upper oxide film 104 and the lower oxide film 106.
The e-dot 107 is formed.

Next, in the step shown in FIG. 5 (g), nitrogen is ion-implanted into the substrate to perform heat treatment, so that SiGe remaining at the interface between the lower oxide film 106 and the Si substrate 101.
The mixed crystal layer 102a is electrically inactivated.

Through the above steps, G
An e-dot body is formed.

[0012]

DISCLOSURE OF THE INVENTION Problem to be Solved by the Invention
The conventional method for manufacturing a Ge quantum dot memory shown in FIG. 1 has the following problems.

First, in the conventional Ge quantum dot memory manufacturing process, the process such as repeating the oxidation process under different conditions many times was very complicated.

Further, even after the Ge dot memory is completed, the SiG film is formed between the Si substrate 101 and the lower oxide film 106.
e The mixed crystal layer 102a remains. Since many lattice defects are present in the SiGe mixed crystal layer 102a, confusion of carriers traveling in the channel and carrier trapping occur, which causes a problem that device characteristics are deteriorated.

The object of the present invention is to simplify the forming process,
Another object of the present invention is to provide a dot body in which deterioration of performance is suppressed and a manufacturing method thereof.

[0016]

A method of forming a dot body according to the present invention comprises a step (a) of forming an insulating layer in contact with at least a part of a conductor layer, and a semiconductor made of a compound semiconductor containing germanium on the insulating layer. Depositing a layer (b),
A step (c) of forming a plurality of dot bodies containing Ge as a main component and an oxide layer covering the dot bodies from the semiconductor layer by thermally oxidizing the semiconductor layer is included.

As a result, the dot body can be formed more easily than in the conventional dot body forming method. Further, since the semiconductor layer is formed on the conductor layer with the insulating layer sandwiched in the step (b), Ge is diffused and segregated toward the conductor layer when the semiconductor layer is thermally oxidized in the step (c). Can be prevented. Therefore, it is possible to obtain a dot body surrounded by an insulator.

The semiconductor layer is a SiGe polycrystal layer or SiG.
It is preferably an e-amorphous layer, a SiGeC polycrystalline layer, or a SiGeC amorphous layer.

After the step (b), a cap layer containing silicon as a main component is formed on the semiconductor layer, so that the semiconductor layer containing Ge at a high concentration is exposed on the substrate surface. Therefore, it is possible to prevent Ge contamination of the manufacturing line.

The method of manufacturing a semiconductor device according to the present invention provides a semiconductor device having a dot body which functions as a floating gate electrode and has Ge as a main component, a control gate electrode, and an impurity diffusion layer which functions as a source / drain. A manufacturing method, a step (a) of forming an insulating layer on a semiconductor substrate; a step (b) of forming a semiconductor layer made of a compound semiconductor containing Ge on at least a part of the insulating layer; Ge is removed from the semiconductor layer by thermally oxidizing the semiconductor layer.
A step (c) of forming a plurality of dot bodies mainly composed of and an oxide film covering the dot bodies.

As a result, a semiconductor device having a dot body can be manufactured more easily than in the conventional manufacturing method. Further, since the semiconductor layer is formed on the semiconductor substrate with the insulating layer sandwiched in the step (b), when the semiconductor layer is thermally oxidized in the step (c), Ge diffuses toward the conductor layer and segregates. Can be prevented. Therefore, it is possible to manufacture a semiconductor device in which deterioration of the interface between the semiconductor layer and the insulating layer does not easily occur.

After the step (c), a step of forming the control gate electrode on the oxide film is further included so that the insulating layer, the dot body, and the oxide film surrounding the dot body are sandwiched on the semiconductor substrate. The gate electrode can be formed with.

Prior to the step (a), the method further includes a step of forming the control gate electrode on the semiconductor substrate. In the step (a), a part of the semiconductor layer is formed on the side surface of the control gate electrode. And forming the insulating layer above the insulating layer in a region extending from above the side surface of the control gate electrode to above a portion of the semiconductor layer in the step (b). Thereby, in the step (c), a dot body and an oxide film covering the dot body are formed in a region extending from the side surface of the control gate electrode to part of the semiconductor layer with the insulating layer interposed therebetween. You can As a result, the dot body can be formed in the vicinity of the junction between the source region and the channel region formed on the semiconductor substrate, so that the dot body can be written efficiently.

The insulating layer is made of one of a silicon oxide film, a silicon oxynitride film, and a silicon nitride film, or is made of a silicon oxide film, a silicon oxynitride film, or a silicon nitride film. Can be made of a laminated film.

The semiconductor layer is a SiGe polycrystal layer, Si
Ge amorphous layer, SiGeC polycrystalline layer, or SiGeC
It is preferably an amorphous layer.

After the step (b), a cap layer containing silicon as a main component is formed on the semiconductor layer, so that when the semiconductor layer is thermally oxidized in the step (c), a high temperature is formed on the substrate surface. Since the semiconductor layer containing Ge in the concentration is not exposed, it is possible to prevent Ge contamination in the manufacturing line.

[0027]

(First Embodiment) In this embodiment, a method for forming a Ge quantum dot body and a method for manufacturing a Ge dot memory will be described.

First, a method of forming a Ge quantum dot body in this embodiment will be described with reference to FIGS. 1 (a) to 1 (e) and FIG.
Will be described with reference to. 1A to 1E are cross-sectional views showing a process of forming a Ge quantum dot body of the present embodiment, and FIG. 2 shows a dot body formed by the method of forming a quantum dot body of the present embodiment. It is a photograph figure.

First, in the step shown in FIG. 1A, the upper surface of the Si substrate 1 is pyrooxidized at 700 ° C. for 5 minutes to form a lower oxide film 2 having a thickness of about 2 nm on the Si substrate. To do.

Thereafter, in the step shown in FIG. 1B, Ge is contained on the lower oxide film 2 in the% order, and the thickness is about 1
A 0 nm SiGe semiconductor thin film 3 is formed. Specifically, S is placed in an ultra-high vacuum chamber with an ultimate vacuum of about 10 ^-8 Pa.
After introducing the i-substrate 1, certain conditions (disilane (Si
₂ H ₆ ) gas partial pressure: 9.3 × 10 ⁻³ Pa, germane (Ge
H ₄ ) gas partial pressure: 4.0 × 10 ^-2 Pa, substrate surface temperature 5
The SiGe semiconductor thin film 3 is formed by performing chemical vapor deposition at 50 ° C. at a deposition time of 3 minutes.

Then, in the step shown in FIG.
e The substrate on which the semiconductor thin film 3 is formed is thermally oxidized at 800 ° C. Then, of the elements constituting the SiGe semiconductor thin film 3, Si is oxidized to form the upper oxide film 4 made of silicon oxide, and Ge is expelled from the growing upper oxide film 4 and the lower oxide film 2 and the upper part. Segregation and agglomeration occur near the interface 6 with the oxide film 4. Then, as the segregation and aggregation of Ge progress with the progress of oxidation on the substrate, the dot body 5 containing Ge as a main component is formed. In the following, the oxide film composed of the lower oxide film 2 and the upper oxide film 4 is referred to as the first oxide film 7.
Call.

By the way, the following can be considered as a cause for forming the dot body 5 as described above. Since Ge hardly diffuses into the silicon oxide film, when the substrate is thermally oxidized, Ge contained in the SiGe semiconductor thin film 3 is expelled from the growing upper oxide film 4 and moves below the upper oxide film 4. However, since the lower oxide film 2 exists below the upper oxide film 4 and Ge does not easily diffuse into the lower oxide film 2, Ge stays near the interface 6 between the upper oxide film 4 and the lower oxide film 2. It is considered that when such Ge gathers in the vicinity of the interface 6 to some extent or more, the Ge is aggregated and becomes the Ge dot body 5.

Next, in the step shown in FIG. 1D, silane gas (SiH ₄ ) and nitrous oxide gas (N ₂ O) are used as raw materials on the upper oxide film 4 of the substrate by the low pressure chemical vapor deposition method. A second oxide film 8 made of silicon oxide and having a thickness of about 10 nm is formed by supplying it as a gas. By adjusting the thickness of the second oxide film 8, the first oxide film 7 and the second oxide film 8 are adjusted.
It is possible to adjust the thickness of the oxide film composed of.

Further, in the step shown in FIG. 1E, silane gas and phosphine gas are formed on the second oxide film 8 by a low pressure chemical vapor deposition method under certain conditions (silane gas (Si
H ₄ ) flow rate: 0.4 l / min, phosphine gas (PH
₃ ) Flow rate: 0.4 ml / min, pressure: 50 Pa, substrate temperature: 600 ° C.). Thereby, the polysilicon film 9 in which P is highly doped is formed.

Through the above steps, G in the present embodiment
An e-dot body is formed. In the present embodiment, it was confirmed from the photograph shown in FIG. 2 that the Ge dot body was certainly formed.

Next, a method of manufacturing a semiconductor memory device using the above-mentioned Ge dot body will be described with reference to FIGS. 3A to 3E are shown in FIG.
It is sectional drawing which showed the manufacturing process of the semiconductor memory device which uses the oxide film which has the Ge dot body formed in the process shown to (a)-(e) as a gate insulating film.

First, in the step shown in FIG.
A resist pattern for the gate electrode is formed on the substrate shown in (e) by photolithography. Then, by performing dry etching using the resist pattern as a mask, the gate electrode 9a is formed from the polysilicon film 9, the second oxide layer 8a is formed from the second oxide film 8, and the first oxide film 7 is formed. To form the first oxide layer 7a. Then, the resist pattern is removed. The first
Of the first oxide layer 7a functions as a tunnel oxide film, and the portion of the first oxide layer 7a composed of the upper oxide film 4 and the second oxide layer 8a function as a control oxide film. Function. Then, the dot body 5 becomes a floating gate.

Next, in the step shown in FIG. 3B, the substrate is dry-oxidized at 800 ° C. to form a third oxide film 1 having a thickness of 10 nm on the Si substrate 1 and the gate electrode 9a.
Form 0. Then, the gate electrode 9a is formed on the Si substrate 1.
The first impurity diffusion layer 11 is formed by ion-implanting P using the as a mask and performing heat treatment. The ion implantation is performed at an accelerating voltage of several tens of kV and a P dose of 10 ¹³ cm.
^-Perform under the condition that it is ² orders.

Then, in the step shown in FIG. 3C, a 200 nm-thickness silicon oxide film is deposited on the substrate by the chemical vapor deposition method, and then the silicon oxide film is dry-etched. As a result, the gate electrode 9a and the second oxide layer 8a are formed.
And the sidewall 12 made of silicon oxide is formed on the side surface of the first oxide layer 7a. During the dry etching in this step, a portion of the third oxide film 10 other than the portion located on the side surface of the gate electrode 9a is removed to form the protective oxide film 10a.

Next, in a step shown in FIG. 3D, arsenic is ion-implanted into the Si substrate 1 using the gate electrode 9a and the sidewall 12 formed on the side surface thereof as a mask to perform a heat treatment. The impurity diffusion layer 13 is formed. In addition, the ion implantation has an accelerating voltage of several tens of kV and As.
The condition is that the dose amount is on the order of 10 ¹⁵ cm ^-2 .

Next, in the step shown in FIG. 3 (e), silane gas (SiH ₄ ) and nitrous oxide gas (N ₂ O) are supplied onto the substrate and a thickness of about 400 nm is obtained by the low pressure chemical vapor deposition method. The interlayer insulating film 14 is formed. Then, the interlayer insulating film 14
After opening a contact window penetrating through and reaching the second impurity diffusion layer 13, an aluminum alloy film is deposited by the sputtering method, and the aluminum alloy film is further patterned to form the metal wiring 15. Through the above steps, the semiconductor memory element of this embodiment is formed.

The advantages obtained in the Ge dot body and the semiconductor memory device of this embodiment will be described below.

First, in this embodiment, after the lower oxide film 2 and the SiGe semiconductor thin film 3 are formed on the substrate,
The Ge dot body 5 can be formed by performing thermal oxidation. This process is simplified as compared with the conventional method for manufacturing a complicated Ge quantum dot.

By controlling the Ge concentration and the film thickness of the SiGe semiconductor thin film 3, the density and grain size of the Ge dot body 5 can be easily controlled.

Further, when the Ge dot body 5 is formed by thermal oxidation in the step shown in FIG. 1C, the lower oxide film 2 prevents Ge from diffusing toward the Si substrate 1 side.
It is possible to suppress deterioration of the interface quality between the i substrate 1 and the lower oxide film 2. Therefore, unlike the prior art, the characteristic deterioration of the semiconductor memory device due to the formation of the Ge dot body 5 is less likely to occur.

In addition, as compared with the prior art, the change in the film thickness of the lower oxide film 2 before and after the formation of the Ge dot body is small, so that the film thickness can be controlled with high accuracy.

In this embodiment, the case where the Ge dot body is formed in the gate insulating film of the n-channel MOSFET having the LDD structure (Lightly Doped Drain) or the extension structure has been described.
The dot body may be adapted to structures other than the LDD structure and the extension structure, and the p-channel MO
It may be adapted to SFET. In that case, for example, p
Channel type MOSFET and single drain structure MOS
The Ge dot body is applied to devices such as FETs.

In this embodiment, the lower oxide film 2 is an ultrathin silicon oxide film having a thickness of about 2 nm.
A silicon oxynitride film, a silicon nitride film, or a laminated film thereof may be used. Further, as the lower oxide film 2, a silicon oxide film having a thickness of 2 nm or more may be used. Thickness 2
When using an ultrathin silicon oxide film of about nm, ns
High-speed operation of the order is possible, but memory characteristics with slightly inferior data retention time are obtained. When an oxide film with a thickness of 2 nm or more is used, the operation speed becomes slower, but good data retention time over 10 years is achieved. To be achieved. In the case of the same element structure, there is generally a trade-off relationship between the operating speed and the data retention time, and it is possible to use them properly according to the application of the memory.

In the present embodiment, as the SiGe semiconductor thin film 3, the Ge concentration in Si is constant S in the depth direction.
Although the iGe single layer film is used, a film in which the Ge concentration changes in the depth direction may be used. In that case, the Ge quantum dot shape can be effectively controlled by changing the Ge concentration in the depth direction.

The SiGe semiconductor thin film 3 in this embodiment
A Ge cap-free silicon cap layer may be formed on. In that case, when thermal oxidation is performed in the step shown in FIG. 1C, SiG containing Ge at a high concentration on the substrate surface.
Since the e semiconductor thin film 3 is not exposed, it is possible to suppress Ge contamination of the manufacturing line.

In this embodiment, the second oxide film 8 is formed on the first oxide film 7. However, when the first oxide film 7 has a sufficient thickness, The second oxide film 8 may not be formed.

(Second Embodiment) In the present embodiment, the second embodiment
A method of manufacturing the Ge dot memory of No. 1 will be described.

First, a method of forming a Ge dot memory according to this embodiment will be described with reference to FIGS. 4A to 4F are cross-sectional views showing a manufacturing process of a semiconductor memory device using an oxide film having a Ge dot body as a sidewall insulating film of a gate electrode.

First, in the step shown in FIG. 4A, the upper portion of the Si substrate 21 is thermally oxidized to form a first oxide film 22 having a thickness of about 2 nm. On the first oxide film 22, the silane gas (SiH ₄ ) flow rate is 0.4 l / min, the phosphine gas (PH ₃ ) flow rate is 0.4 ml / min, and the pressure is 50 P.
a, the semiconductor film 23 is formed by performing the low pressure chemical vapor deposition method under the condition that the substrate temperature is 600 ° C.

Next, in the step shown in FIG. 4B, the substrate is heat-treated in a nitrogen atmosphere at 900 ° C. for 30 minutes. Then, a resist pattern is formed on the substrate, and the semiconductor film 23 and the first oxide film 22 are dry-etched using the resist pattern as a mask to form the gate electrode 24 and the gate insulating film 25. Subsequently, using the gate electrode 24 as a mask, phosphorus ions are implanted into the upper portion of the Si substrate 21, and then heat treatment for activating impurities is performed to form the first impurity diffusion layer 26. At this time, the acceleration voltage of phosphorus ion implantation is several 1
It is performed under the conditions of 0 KeV and a dose amount of 10 ¹³ cm ^-2 .

Thereafter, the upper part of the substrate is thermally oxidized at 850 ° C. to form the second oxide film 27 on the exposed portions of the Si substrate 21, the gate electrode 24 and the gate insulating film 25.

Next, in the step shown in FIG. 4C, after introducing the substrate into an ultrahigh vacuum chamber having an ultimate vacuum of 10 ^-8 Pa, the disilane (Si ₂ H ₆ ) gas partial pressure is 9. 3 x 10
^-3 Pa, germane (GeH ₄ ) gas partial pressure is 4.0 × 10
By performing chemical vapor deposition under the conditions of ⁻² Pa and substrate temperature of 550 ° C. for 3 minutes, the SiGe semiconductor thin film 28 having a thickness of about 10 nm is formed.

Then, in the step shown in FIG. 4D, the second oxide film 27 and the SiGe semiconductor thin film 28 are subjected to reactive ion etching to remove Si from the sidewalls of the gate electrode 24 and the gate insulating film 25. A protective oxide film 27a extending on a part of the substrate 21 and a sidewall insulating film 28a made of a SiGe semiconductor layer are formed thereon.

Then, in the step shown in FIG.
By thermally oxidizing the side wall insulating film 28a at a temperature of .degree.
b and the dot body 29 containing Ge as a main component are separated.
The process will be described in detail below.

The side wall oxide film 28b made of silicon oxide is formed by oxidizing Si contained in the side wall insulating film 28a.
Grows. On the other hand, Ge contained in the sidewall insulating film 28a
Has a property of being less likely to diffuse into the silicon oxide film, and is expelled from the growing sidewall oxide film 28b. Then, Ge is a sidewall oxide film 28b and a protective oxide film 27.
The dot body 29 is formed by segregating and aggregating at the interface with a. Then, the dot body 29 becomes a floating gate, and a portion of the protective oxide film 27a which is not in contact with the gate electrode 24 and is located between the dot body 29 and the Si substrate 21 functions as a tunnel oxide film.

Then, the second impurity diffusion layer 30 is formed on the substrate by implanting As ions using the gate electrode 24 and the sidewall oxide film 28b as a mask and performing heat treatment. The As ion implantation has an accelerating voltage of several tens ke.
V and dose amount is 10 ¹⁵ cm ^-2 .

Next, in the step shown in FIG. 4F, a thickness of 400 nm is obtained by a low pressure chemical vapor deposition method using silane gas (SiH ₄ ) and nitrous oxide gas (N ₂ O) as source gases.
The interlayer insulating film 31 is formed to some extent. Then, a contact hole reaching the second impurity diffusion layer 30 is opened in the interlayer insulating film 31. Then, an aluminum alloy film is deposited on the substrate by a sputtering method, and the aluminum alloy film is patterned to form the metal wiring 32.

The advantages obtained by the semiconductor memory device of this embodiment will be described below.

First, in the present embodiment, the sidewall insulating film 28 is sandwiched on the side surface of the gate electrode 24 with the protective oxide film 27a interposed therebetween.
After forming a, the dot body 29 is formed by performing thermal oxidation.
Can be formed. This process is simplified as compared with the conventional method for manufacturing a complicated Ge quantum dot.

Further, by controlling the Ge concentration and the film thickness of the sidewall insulating film 28a, it becomes easy to control the density and the grain size of the Ge dot body 29.

Further, when the dot body 29 is formed by thermal oxidation in the step shown in FIG. 4E, the protective oxide film 27a is formed.
As a result, diffusion of Ge to the Si substrate 21 side is prevented, so that deterioration of the interface quality between the Si substrate 21 and the sidewall oxide film 28b can be suppressed. Therefore, unlike the prior art, the characteristic deterioration of the semiconductor memory device due to the formation of the dot body 29 is less likely to occur.

Further, in this embodiment, in addition to the advantages obtained in the first embodiment of the present invention as described above, it is possible to achieve lower power consumption than in the first embodiment. There are advantages. The reason is shown below. In general,
The threshold voltage of the MOSFET is determined by how the energy band in the region near the source portion of the energy band in the channel region bends. Therefore, in the case where the dot body 29 is formed on the side wall of the gate portion, that is, near the junction between the channel region and the source portion as in the present embodiment, the dots are planarly formed under the gate portion. The threshold voltage can be effectively controlled by a smaller number of dots than when the body is formed. As a result, the current for writing electrons / holes in the dots can be reduced, and the power consumption can be further reduced.

In this embodiment, the LDD structure is used.
(Lightly Doped Drain) or the case where the Ge dot body 29 is formed in the gate sidewall oxide film 28b of the n-channel MOSFET having the extension structure has been described.
The Ge dot body of the present invention may be applied to a structure other than the LDD structure and the extension structure, and may be applied to a p-channel MOSFET. In that case, the Ge dot body is applied to a device such as a p-channel MOSFET or a single drain structure MOSFET.

Further, according to the second embodiment of the present invention, an extremely thin silicon oxide film having a thickness of about 2 nm which allows direct tunneling of electrons is used as the gate insulating film 25. In this case, a silicon oxide film having a thickness of 2 nm or more may be used. When an ultra-thin silicon oxide film with a thickness of about 2 nm is used, high-speed operation of the order of ns is possible, but memory characteristics with slightly inferior data retention time are obtained.
When an oxide film having a thickness of 2 nm or more is used, the operation speed becomes slow, but a good data retention time of more than 10 years can be achieved. In the case of the same element structure, there is generally a trade-off relationship between the operating speed and the data retention time, and which function is to be emphasized can be selectively used according to the application of the memory.

In the present embodiment, the second oxide film 27
Although the silicon oxide film is used as the above, a silicon oxynitride film, a silicon nitride film, or a laminated film thereof may be used instead.

In this embodiment, the SiGe semiconductor thin film 28 is a SiGe single layer film in which the Ge concentration in Si is constant in the depth direction, but a film whose Ge concentration changes in the depth direction may be used. Good. In that case, Ge in the depth direction
By changing the concentration to change the state of Ge aggregation and segregation, it becomes possible to effectively control the shape of the Ge quantum dots.

A silicon cap layer containing no Ge may be formed on the sidewall insulating film 28a in the present embodiment. In that case, when the thermal oxidation is performed in the step shown in FIG. 4D, the side wall oxide film 28b containing Ge at a high concentration is not exposed on the substrate surface, so that Ge contamination of the manufacturing line can be suppressed. It will be possible.

[0073]

According to the method of forming a dot body and the method of manufacturing a semiconductor device of the present invention, the steps can be simplified, and an oxide film is formed between the layer on which the dot body is formed and the Si substrate. By interposing it, it is possible to suppress the diffusion of Ge in the direction of the Si substrate, so that it is possible to prevent the deterioration of the interface quality.

[Brief description of drawings]

1A to 1E are cross-sectional views showing a process of forming a Ge quantum dot body according to a first embodiment.

FIG. 2 is a photographic diagram of a dot body formed by the method of forming a quantum dot body according to the first embodiment.

3A to 3E show manufacturing steps of a semiconductor memory device using an oxide film having a Ge dot body formed in the steps shown in FIGS. 1A to 1E as a gate insulating film. FIG.

4A to 4F are cross-sectional views showing a manufacturing process of a semiconductor memory device using an oxide film having a Ge dot body as a sidewall insulating film of a gate electrode.

FIGS. 5A to 5G are cross-sectional views showing steps of forming a Ge dot in a gate insulating film in the manufacturing steps of the conventional Ge quantum dot memory.

[Explanation of symbols]

1 Si substrate 2 Lower oxide film 3 Semiconductor thin film 4 Upper oxide film 5 dot body 6 interface 7 First oxide film 8 Second oxide film 8a Second oxide layer 9 Polysilicon film 9a Gate electrode 10 Third oxide film 10a protective oxide film 11 First Impurity Diffusion Layer 12 Sidewall 13 second impurity diffusion layer 14 Interlayer insulation film 15 Metal wiring 21 Si substrate 22 First oxide film 23 Semiconductor film 24 gate electrode 25 Gate insulation film 26 First Impurity Diffusion Layer 27 Second oxide film 27a protective oxide film 28 SiGe semiconductor layer 28a Side wall insulating film 28b Side wall oxide film 29 dot body 30 second impurity diffusion layer 31 Interlayer insulation film 32 metal wiring

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) H01L 29/792 (72) Inventor Kiyoyuki Morita 1006 Kadoma, Kadoma-shi, Osaka Matsushita Electric Industrial Co., Ltd. F Term (reference) 5F083 EP17 EP23 EP48 EP49 EP50 EP63 EP68 GA05 JA03 JA35 PR12 PR14 PR21 PR36 5F101 BA54 BD07 BH02 BH03 BH09 BH30

Claims (9)

[Claims] 1. A step (a) of forming an insulating layer in contact with at least a part of a conductor layer; a step (b) of depositing a semiconductor layer made of a compound semiconductor containing germanium on the insulating layer; A method for forming a dot body, comprising the step (c) of forming a plurality of dot bodies containing Ge as a main component and an oxide layer covering the dot body from the semiconductor layer by thermally oxidizing the layer. 2. The method for forming a dot body according to claim 1, wherein the semiconductor layer is a SiGe polycrystal layer, a SiGe amorphous layer,
A method for forming a dot body, which is a SiGeC polycrystalline layer or a SiGeC amorphous layer. 3. The method for forming a dot body according to claim 1, wherein a cap layer containing silicon as a main component is formed on the semiconductor layer after the step (b). Method of forming dot body. 4. A method of manufacturing a semiconductor device, comprising a dot body having Ge as a main component, which functions as a floating gate electrode, a control gate electrode, and an impurity diffusion layer which functions as a source / drain, comprising: a semiconductor substrate; A step (a) of forming an insulating layer thereon, a step (b) of forming a semiconductor layer made of a compound semiconductor containing Ge on at least a part of the insulating layer, and thermally oxidizing the semiconductor layer. A method of manufacturing a semiconductor device, comprising the step (c) of forming a plurality of dot bodies containing Ge as a main component from the semiconductor layer and an oxide film covering the dot bodies. 5. The semiconductor device manufacturing method according to claim 4, further comprising a step of forming the control gate electrode on the oxide film after the step (c). Manufacturing method. 6. The method of manufacturing a semiconductor device according to claim 4, further comprising a step of forming the control gate electrode on the semiconductor substrate before the step (a), wherein the step (a) includes Forming the insulating layer extending from a side surface of the control gate electrode to a part of the semiconductor layer, and in the step (b), forming an insulating layer from a side surface of the control gate electrode to a part of the semiconductor layer. A method of manufacturing a semiconductor device, comprising forming the semiconductor layer in the extending region with the insulating layer interposed therebetween. 7. The method of manufacturing a semiconductor device according to claim 4, wherein the insulating layer is one of a silicon oxide film, a silicon oxynitride film, and a silicon nitride film. Or a laminated film composed of any one of a silicon oxide film, a silicon oxynitride film, and a silicon nitride film. 8. The method of manufacturing a semiconductor device according to claim 4, wherein the semiconductor layer is a SiGe polycrystal layer, a SiGe amorphous layer, a SiGeC polycrystal layer, or a SiGeC non-crystal layer. A method for manufacturing a semiconductor device, which is a crystalline layer. 9. The method for manufacturing a semiconductor device according to claim 4, wherein after the step (b), a cap layer containing silicon as a main component is formed on the semiconductor layer. A method of manufacturing a semiconductor device, comprising: