KR0185461B1 - Field effect semiconductor device and its manufacture - Google Patents

Abstract

The semiconductor device of the present invention has an electrode having a polyside structure including a tungsten silicide layer having a silicon composition ratio of tungsten silicide having a composition ratio of 2.4 or less on its entire upper surface and an impurity-doped silicon layer formed under the tungsten silicide layer.

Description

Semiconductor device having electrode of polyside structure and manufacturing method thereof

1A to 1C are cross-sectional views showing a conventional step of forming a first MOSFET.

2A to 2D are cross-sectional views showing a conventional step of forming a second MOSFET.

3 is a graph showing the relationship between the composition ratio of silicon in the tungsten silicide obtained by the experiment and the impurity external diffusion rate.

4 shows the relationship between etching time (polyside structure) and impurity distribution in SIMS analysis.

FIG. 5 is a diagram showing a relationship obtained by experimenting with the flow rate of tungsten hexafluoride and the silicon composition ratio in tungsten silicide when SiH ₄ is made constant. FIG.

6A to 6F are views showing a manufacturing process of the first MOS transistor having the electrode of the present invention.

7A to 7E are views showing a manufacturing process of a second MOS transistor having an electrode of the present invention.

8 is a distribution diagram of silicon in tungsten silicide constituting the electrode of the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having, for example, a polysided electrode applied to a gate electrode of a MOSFET and a method of manufacturing the same.

In semiconductor devices, high speed operation of semiconductor devices is achieved by miniaturizing elements and reducing resistance of wirings and electrodes. For example, in a field-effect transistor (hereinafter referred to as FET), the gate electrode is made finer to submicron and lowered, so that the transistor can operate at higher speed. In order to reduce the resistance of the gate electrode and to secure the boundary between the gate electrode and the gate insulating layer, the gate electrode has a polyside structure of two layers of polysilicon layer and tungsten silicide layer instead of the polysilicon single layer structure. Tends to be employed.

1A to 1C and 2A to 2D are cross-sectional views illustrating a manufacturing process of a FET having a gate electrode having a general polyside structure.

FIG. 1A shows a state of ion implantation for forming a source region and a drain region of the FET, and FIG. 1B shows a state where the FET is covered with a high temperature silicon dioxide (hereinafter referred to as HTO) layer grown by CVD. . HTO is an oxide formed at a temperature of about 700 ° C. or higher.

1A to 1C, reference numeral 20 denotes a gate electrode, 21 a silicon substrate, 22 a source region, 23 a drain region, 24 a gate insulating layer, 25 an amorphous silicon layer, 26 a tungsten silicide layer, and 27 The silver first HTO layer, 27s is a sidewall formed by the first HTO layer 27, and 28 is a second HTO layer protecting the FET.

A FET having a gate electrode having a polyside structure is schematically formed through the following process.

First, a gate insulating layer 24 is formed by thermal oxidation on the surface of the silicon substrate 21, and an amorphous silicon layer 25 and a tungsten silicide (WSi _x ) layer 26 which are not coated thereon are formed, and then Phosphorus is doped into the amorphous silicon layer 25. The composition ratio x of silicon constituting the tungsten silicide (WSi _x ) layer 26 is about 2.55 when tungsten is 1. Thereafter, a multilayer film made of the gate insulating layer 24, the amorphous silicon layer 25, and the tungsten silicide layer 26 is patterned and left in the gate electrode formation region. The patterned amorphous silicon layer 25 and the tungsten silicide layer 26, ie, the patterned polyside structure layer, become the gate electrode 20. Subsequently, as shown in FIG. 1A, phosphorus (P +) is ion-implanted into the silicon substrate 21 using the gate electrode 20 as a mask, and the region into which phosphorus is introduced is the source region 22a having a low impurity concentration. ) And drain region 23a.

Next, as shown in FIG. 1B, after the first HTO layer 27 is formed by CVD at a high temperature of about 750 to 800 ° C., the first HTO layer 27 is formed by reactive ion etching (RIE). Anisotropically etch substantially vertically to form sidewalls 27s made of HTO. If phosphorus is ion implanted into the silicon substrate 21 using the gate electrode 20 and the sidewalls 27s as a mask, the region into which phosphorus is introduced is the source 23b and the drain region 22b having a high impurity concentration. do. The source and drain regions have an LDD structure. At the time of phosphorus ion implantation, impurities are also introduced into the amorphous silicon layer 25 constituting the gate electrode.

A second HTO layer 28 serving as a protective film is formed on the gate electrode 20, the sidewalls 27s, and the silicon substrate 21. The second HTO layer 28 has a function of maintaining a good insulation breakdown voltage between the wiring or electrode and the gate electrode 20 formed on the second HTO layer 28.

The manufacturing process of the 2nd FET shown to FIG. 2A-FIG. 2D has shown the process which did not completely cover the source region and the drain region by the HTO layer.

First, as shown in FIG. 2A, a gate insulating layer 24, an undoped amorphous silicon layer 25, and a tungsten silicide (WSi _x ) layer 26 are formed on the silicon substrate 21, followed by an amorphous silicon layer. Ion implantation is applied to (25). The composition ratio x of silicon constituting the tungsten silicide (WSi _x ) layer 26 is about 2.55 when tungsten is 1.

Next, as shown in FIG. 2B, the first HTO layer 29 is formed on the tungsten silicide layer 26 at a growth temperature of 750 ° C to 800 ° C.

Thereafter, a multilayer film made of the gate insulating layer 24, the amorphous silicon layer 25, the tungsten silicide layer 26, and the first HTO layer 29 is patterned and left in the gate electrode formation region. The patterned polyside structure layer becomes the gate electrode 20. Subsequently, phosphorus (P +) is ion implanted into the silicon substrate 21 using the gate electrode 20 as a mask, and the region into which the phosphorus is introduced is the source region 22a and the drain region 23a having a low impurity concentration. do.

Next, as shown in FIG. 2C and FIG. 2D, a second HTO layer 30 formed by CVD at a high temperature of about 750 to 800 ° C. is formed, and the second HTO layer 30 is formed. The second HTO layer 30 is anisotropically etched approximately vertically by reactive ion etching (RIE) to form sidewalls 30s of the second HTO layer 30. If phosphorus is ion implanted into the silicon substrate 21 using the gate electrode 20 and the sidewalls 30s as a mask, the region into which phosphorus is introduced is the source 22b and the drain region 23b having a high impurity concentration. do. The source and drain regions have an LDD structure.

However, it has been confirmed by the experiments of the present inventors that the silicon layer 25 constituting the above polycide structure has a high resistance due to heat when growing HTO. This is because impurities, as shown in FIGS. 1B, 1C, 2B, and 2C, diffuse from the amorphous silicon layer 25 to the outside by heat when the HTO layers 27 to 30 are formed.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device having an electrode having a polyside structure in which resistance is not easily reduced by heat, and a method of manufacturing the same.

According to the present invention, a polyside structure layer having a tungsten silicide layer having a tungsten silicide having a composition ratio of silicon to tungsten of 2.0 to 2.4 on the entire upper surface is formed on a semiconductor layer containing impurities, and the electrode is formed by the polyside structure layer. To form.

It has been confirmed by experiment that the use of a tungsten silicide layer having a composition ratio of silicon to tungsten of 2.4 or less has an effect of making it difficult to externally diffuse impurities therein by heat treatment after electrode formation. Difficulties of diffusion of impurities from the tungsten silicide layer to the outside have the effect of suppressing the diffusion of impurities from the silicon layer below to the outside thereof.

Therefore, even if the electrode having such a polycide structure is covered with an HTO film, the reduction of impurities in the silicon layer constituting the polycide structure is suppressed and the increase in resistance is prevented. As an electrode having such a polyside structure, for example, there is a gate electrode of a MOSFET. There is a remarkable effect when the growth temperature of the HTO film is 775 캜 or lower.

Setting the composition ratio of silicon to tungsten silicide to 2.4 or less is easily achieved by adjusting the flow rate ratio of the silane gas and tungsten hexafluoride. For example, when the flow rate of silane with respect to the flow rate of tungsten hexafluoride is 83 or less, a silicon composition ratio will be 2.4 or less. In this case, the growth temperature of the tungsten silicide layer is preferably in the range of 250 ° C to 380 ° C.

As for the tungsten silicide layer which comprises a polyside structure, it is important that the composition ratio of the silicon of the whole upper surface at least becomes 2.4 or less, More specifically, it is 2.0-2.4. Therefore, the tungsten silicide layer may have a two-layer structure, and the composition ratio of silicon in the upper layer may be 2.0 to 2.4, or the composition ratio of silicon in the tungsten silicide layer is changed continuously or stepwise so that the composition ratio of silicon on the top surface is 2.0 to 2.4. A structure may be used.

First, in order to investigate the cause of the change in the resistance value of the silicon layer under the polyside structure covered with the HTO film made of SiO ₂ , the change in the impurity content in the silicon layer was examined by experiment.

After forming a polyside structure of an amorphous silicon (a-Si) layer and a tungsten silicide (WSi _x ) layer, the HTO layer was formed on the polyside structure by chemical vapor deposition (CVD) at a high temperature of about 800 ° C. The high concentration of phosphorus (P +) introduced to bring the conductivity into the a-Si layer diffused outward, leaving only 5% of the original content. When the a-Si layer becomes high in resistance, when a signal voltage is applied to an electrode having a polyside structure, a high resistance of the a-Si layer becomes depleted, making it difficult to control the source / drain current. Occurs. In contrast, when the HTO layer was grown at 775 ° C, the residual amount of impurities (phosphorus) in the a-Si layer was about 35% as originally. Therefore, it was found that the escape of impurities in the a-Si layer depends on the growth temperature of the HTO layer.

The residual amount of impurities was determined by the intensity of impurities (phosphorus) measured by fluorescence X-rays.

The tungsten silicide layer was formed by CVD with a growth atmosphere pressure of 200 mTorr, using silane (SiH ₄ ) and tungsten hexafluoride (WF ₆ ) as the reaction gas, and a growth temperature of 350 ° C. In this case, the SiH ₄ flow rate was 1000 cc / min, and the WF ₆ flow rate was 8 cc / min. In addition, impurities in the a-Si layer were introduced by ion implantation, and the ion implantation was performed under conditions of an acceleration energy of 20 keV and a dose amount of 4 x 10 ¹⁵ atoms / cm 2.

In addition, in the case of impurity boron (B +), arsenic (AS +), and the like contained in the amorphous silicon layer, almost the same phenomenon occurs.

In order to investigate under what conditions the amount of impurities diffused outward in the silicon layer, which is such a polyside structure, was tested as follows.

First, a tungsten silicide film containing an impurity was formed to a thickness of 1600 kPa, and an HTO film was grown thereon. As a result of investigating how the content of silicon constituting the tungsten silicide layer and the growth temperature of the HTO film influence the amount of impurity diffusion from the tungsten silicide film, results as shown in FIG. 3 were obtained. 3 is a diagram showing the relationship between the composition ratio (horizontal axis) of silicon contained in tungsten silicide and the external diffusion rate (vertical axis) of impurities contained in tungsten silicide. The composition ratio of silicon constituting tungsten silicide is a ratio of the composition ratio of tungsten constituting tungsten silicide. The external diffusion rate of impurities means a percentage obtained by dividing the amount of impurities that have escaped from the tungsten silicide layer to the outside due to the growth of the HTO film by the amount of impurities before the growth of the HTO film.

According to the experimental results, when the composition ratio (x) of silicon contained in tungsten silicide was 2.4, it was found that any of the growth temperature of the HTO film was 750 ° C or 775 ° C, and the external diffusion rate of impurities (for example, phosphorus) was low. It turns out that the residual amount of impurities is increasing. On the other hand, as the composition ratio x of the silicon became larger than 2.4, the external diffusion rate of the impurities was increased under the conditions of the HTO film's saint temperature of 775 ° C, and many impurities escaped from the tungsten silicide film. When the growth temperature of the HTO film was 750 ° C, the external diffusion rate of impurities was suppressed to 16% or less when the composition ratio (x) of silicon was 2.4 to 2.55. At the growth temperature of 800 ° C., the external diffusion rate of the impurities exceeds 80%, but the smaller the composition ratio (x) of silicon is, the smaller the external diffusion rate is.

Next, a thermal oxide film (G-ox) is formed on the surface of the silicon substrate, and an impurity-containing a-Si layer, a tungsten silicide (WSi _x ) layer, and an HTO layer are sequentially formed on the HTO film. Secondary ion mass spectrometry (SIMS) analysis using sputter etching from the above resulted in the same results as shown in FIG. In Fig. 4, the horizontal axis represents the sputtering time, and the vertical axis represents the amount of residual impurities. Sputter time equivalently represents the depth from the HTO layer surface to the silicon substrate (Si-sub).

In this experiment, three types of samples were used in which the HTO layer was grown at 775 ° C, the impurities contained in a-Si were phosphorus, and the composition ratios of silicon in the tungsten silicide layer were 2.4, 2.55, and 2.8.

As is apparent from FIG. 4, when the composition ratio x of silicon of the tungsten silicide (WSi _x ) layer is 2.4, the amount of residual phosphorus in the a-Si layer and the WSi _x layer is large, and when x is 2.55, the a-Si layer and The residual amount of phosphorus in the WSi _x layer is reduced by about one order, and when x is 2.8, the residual amount of phosphorus in the WSi _x layer and on the a-Si layer is drastically reduced.

As is apparent from FIGS. 3 and 4, the growth temperature of the HTO film in order to suppress the removal of impurities in the a-Si layer when forming the HTO film in the polycide structure composed of the WSi _x layer and the a-Si layer. When the composition ratio of silicon in the WSi _x layer is 2.4 or less, the release of impurities from the a-Si layer can be suppressed. Under this condition, conductivity of practical size is secured in the a-Si layer.

5 is a diagram showing the relationship between the flow rate of WF ₆ and the silicon composition ratio _x of WSi _x when the WSi _x is grown. In FIG. 5, the horizontal axis represents the flow rate of WF ₆ , and the vertical axis represents the silicon composition ratio _x in WSi _x . However, the growth temperature of the WSi _x layer was constant at 360 ° C., the pressure was 200 mTorr, and the flow rate of SiH ₄ was 1000 cc / min.

5, it can be seen that the silicon composition ratio x of tungsten silicide decreases as the flow rate of WF ₆ increases. The flow rate of the WF ₆ will be increased (the flow rate of a villa or less, SiH ₄ / WF ₆₎ WF value obtained by dividing the flow rate of SiH ₄ at a flow rate of ₆ drops. That is, to a silicon composition ratio x constituting the WSi _x to less than 2.4, when the flow rate of the WF ₆ 12cc / min or less, in other words, there is a need to a flow rate ratio of SiH ₄ / WF ₆ to 83 below.

When the composition ratio of silicon is 2.4 or less, SiH ₄ / WF ₆ is 83 or less, whereby the ratio of silicon in tungsten silicide is reduced, and as a result, the external diffusion of impurities in the polyside structure is effectively suppressed. In addition, suppressing the diffusion of impurities in tungsten silicide has the effect of making it difficult to diffuse into the tungsten silicide of impurities in the silicon layer below, that is, the effect of suppressing the increase in the resistance of the silicon layer.

The relationship shown in FIG. 5 was similarly obtained even when the growth temperature of tungsten silicide was set in the range of 250 ° C. or higher to 380 ° C. or lower. When the temperature at which the tungsten silicide layer is grown is set in the range of 250 ° C. or higher and 380 ° C. or lower, the bulk resistance before annealing tungsten silicide becomes 1000 μm · cm or less, which is less than the bulk resistance of the impurity doped polycrystalline silicon. Technical effects such as low resistance of the polyside layer are produced.

When the growth temperature of the tungsten silicide layer was set in the range of 250 ° C. or higher and 380 ° C. or lower, the composition ratio of silicon in tungsten silicide decreased. This effectively suppresses the external diffusion of impurities from the polycide structure when the HTO layer is grown on the polycide structure. However, since the tungsten silicide layer containing a large amount of tungsten tends to peel off from the silicon layer below it, the composition ratio x of silicon needs to be 2.2 or more, preferably 2.4 or more. For example, when the HTO film is formed at 750 ° C. as is apparent from FIG. 3, the peeling is prevented and the external diffusion rate of silicon from WSi _x is reduced. Therefore, the composition ratio x of silicon is set to 2.55 or less. It is preferable.

In the case where tungsten silicide is formed using WF ₆ gas and SiH ₄ gas, when formed at a temperature in the range of 250 ° C. to 350 ° C., analysis shows that less fluorine is bound to silicon in the tungsten silicide layer. Could know.

As mentioned above, in this invention, the structure whose composition ratio of silicon of the surface layer of at least surface layer among these tungsten silicide layers was employ | adopted in the electrode of the polyside structure which consists of a silicon layer and a tungsten silicide layer. In this case, if the composition ratio of silicon in the tungsten silicide layer is continuously changed so as to decrease as it moves away from the silicon layer below, the effect of the tungsten silicide layer being hard to peel off from the silicon layer is also accompanied. The composition ratio changes, for example, from 2.55 to 2.4 or less continuously or stepwise from the lower surface of the tungsten silicide layer to the upper surface. According to this composition, the HTO layer is grown at 775 ° C. on the tungsten silicide layer. FIG. 7 also has an effect of suppressing diffusion of impurities from the polycide structure.

The silicon layer constituting the polyside structure was able to obtain the above-described results in either amorphous or polycrystalline.

In addition, SiO _{2 which} is an HTO layer is grown by using a mixed gas containing nitrogen dioxide (NO ₂ ) in a silane-based gas such as SiH ₄ and Si ₂ H ₆ .

Next, an example of a MOSFET employing a suitable polyside structure as a gate electrode for suppressing diffusion of impurities will be described.

[Example 1]

A process for forming a first MOS field effect transistor (MOSFET) having a gate electrode having a polyside structure will be described with reference to FIGS. 6A to 6F. First, the state shown in FIG. 6A will be described.

The surface of the silicon substrate 1 is thermally oxidized to form a gate insulating film 4 having a thickness of 120 mW, and an undoped amorphous silicon layer 5 is formed thereon by a thickness of 400 mW.

Subsequently, a first tungsten silicide (WSi _x ) layer 6 is formed on the amorphous silicon layer 5 at a thickness of 600 GPa and a second tungsten silicide (WSi _x ) layer 7 at least 100 GPa. The composition ratio x of silicon in the first tungsten silicide layer 6 is set to 2.55 in consideration of preventing peeling from the amorphous silicon layer 5 below and suppressing diffusion of impurities to the outside. The silicon composition ratio in the second tungsten silicide layer 7 is 2.4 or less in consideration of the effect of suppressing the removal of impurities. The polyside structure is formed by a plurality of layers from the amorphous silicon layer 5 to the second tungsten silicide layer 7.

When the first tungsten silicide layer 6 is grown, the atmospheric pressure is 200 mTorr, the flow rate of SiH ₄ is 1000 cc / min (1 l / min), and the flow rate of WF ₆ is ₈ cc / min. When the second tungsten silicide layer 7 is grown, the atmospheric pressure is 150 mTorr, the flow rate of SiH ₄ is 1000 cc / min, and the flow rate of WF ₆ is ₁₂ cc / min.

The growth temperature of tungsten silicide, that is, the heating temperature of the silicon substrate 1 is set within the range of 250 to 380 ° C.

Next, as shown in FIG. 6B, the gate insulating film 4 to the second tungsten silicide layer 7 are patterned using photolithography techniques, and the layer is left in the gate electrode formation region. The patterned amorphous silicon layer 5 and the first and second tungsten silicide layers 6, 7 become the gate electrode 8 of the MOSFET.

Subsequently, using the gate electrode 8 as a mask, phosphorus ions P + are implanted into the silicon substrate 1 under conditions of a dose amount of 1 × 10 ¹¹ atoms / cm 2 and an acceleration energy of 20 keV, followed by annealing. The source region 2a of low impurity concentration is formed on one side of the gate electrode 8 of the substrate 1, and the drain region 3a of low impurity concentration is formed on the other side. At the time of phosphorus ion implantation, impurities are also introduced into the a-Si layer 5 constituting the gate electrode 8.

Thereafter, as shown in FIG. 6C, the first HTO layer 9 made of SiO ₂ is grown by CVD at a growth temperature in the range of 700 ° C to 775 ° C. As shown in FIG. 6D, sidewalls 9s are formed on both sides of the gate electrode 8 by etching back the first HTO layer 9 by RIE.

Next, as shown in FIG. 6E, using the gate electrode 8 and the sidewalls 9s as a mask, the phosphorus dose to the silicon substrate 11 is 4 x 10 ¹⁵ atoms / cm 2 and the acceleration energy is 20 keV. By ion implantation and subsequent annealing, the source region 2b and the drain region 3b having high impurity concentration are formed in the silicon substrate 1 on both sides of the sidewall 9s and the gate electrode 8. In this case, impurities are introduced at high concentration into the a-Si layer 5 through the first and second tungsten silicide layers 6 and 7.

The source regions 2a and 2b and the drain regions 3a and 3b, which are divided into high ball pure water concentration and low impurity concentration, respectively, have an LDD structure.

Thereafter, as shown in FIG. 6F, the second HTO layer 10 is grown by the same method as the first HTO layer 9, and the second HTO layer 10 causes the gate electrode 8, The side wall 9s and the silicon substrate 1 are covered.

In the completed field effect transistor, the silicon composition ratio of the second tungsten silicide layer 7, which is the uppermost layer in the gate electrode 8, is 2.4, so that the first HTO layer 9 is evident from the above-described experimental results. And impurities in the first and second tungsten silicide layers 6 and 7 and the amorphous silicon layer 5 become difficult to diffuse to the outside during the growth of the second HTO layer 10. Therefore, the reduction of impurities in the amorphous silicon layer 5 is suppressed, and the resistance thereof is prevented from increasing.

As the polyside of the gate electrode 8, a structure similar to that of the second example described later may be adopted.

[Example 2]

A process for forming a second MOSFET having a gate electrode having a polyside structure will be described with reference to FIGS. 7A to 7E. First, the state shown in FIG. 7A will be described.

The surface of the silicon substrate 11 is thermally oxidized to form a gate insulating film 14 having a thickness of 120 mW, and an undoped amorphous silicon layer 15 is formed thereon at a thickness of 400 mW. A tungsten silicide layer 16 having a thickness of 600 kPa is formed on the amorphous silicon layer 15. As shown by the solid line in FIG. 8, the silicon composition ratio of the tungsten silicide layer 16 is changing linearly from 2.55 to 2.4 from bottom to top. A polycide structure is formed by the amorphous silicon layer 15 and the tungsten silicide layer 16.

In the case of growing the tungsten silicide layer 16, the flow rate of SiH ₄ is constant at 1000 cc / min, and the flow rate of WF ₆ is linearly changed from 7 cc / min to 12 cc / min with time. . As other growth conditions, the atmospheric pressure was 150 mTorr and the growth temperature was 350 ° C.

After the growth of the film, phosphorus ions P + are implanted into the amorphous silicon layer 15 through the WSi _x layer 16 under conditions of a dose amount of 4 x 10 ¹⁵ atoms / cm 2 and an acceleration energy of 20 keV.

Subsequently, as shown in FIG. 7B, the first HTO layer 17 made of SiO ₂ is grown on the tungsten silicide layer 16 by CVD at a growth temperature in the range of 700 ° C to 775 ° C.

Thereafter, as shown in FIG. 7C, the gate insulating film 14, the amorphous silicon layer 15, the tungsten silicide layer 16, and the HTO layer 17 are patterned and left in the gate electrode formation region. The patterned tungsten silicide layer 16 and the amorphous silicon layer 15 become the gate electrode 18.

Next, using the first HTO layer 17 on the gate electrode 18 as a mask, phosphorus (P +) is ionized on the silicon substrate 11 under the conditions of a dose amount of 1 × 10 ¹¹ atoms / cm 2 and an acceleration energy of 20 keV. By implantation and subsequent annealing, source region 12a and drain region 13a having a low impurity concentration including phosphorus are formed on both sides of gate electrode 17 in silicon substrate 11.

Thereafter, as shown in FIG. 7D, the second HTO layer 19 is grown by the same method as the first HTO layer 17, which is etched back using RIE to form sidewalls on both sides of the gate electrode 18. FIG. 20 is formed.

Next, as shown in FIG. 7E, phosphorus is applied to the silicon substrate 11 at a dose of 4 x 10 ¹⁵ atoms / cm 2 and an acceleration energy of 20 keV using the first HTO layer 17 and the sidewall 20 as a mask. By ion implantation and subsequent annealing, high concentration source region 12b and drain region 13b are formed in the silicon substrate 11 on both sides of the sidewall 20 and the gate electrode 17.

The source regions 12a and 12b and the drain regions 13a and 13b divided into the high impurity concentration and the low impurity concentration have LDD structures, respectively.

In the MOSFET of this example, when the first HTO layer 17 and the second HTO layer 19 are grown, the tungsten silicide layer 16 prevents the external diffusion of impurities (phosphorus) in the amorphous silicon layer 15 thereunder. It is effectively suppressed.

In the present embodiment, the residual amount of impurities (phosphorus) in the amorphous silicon layer 15 is determined by the intensity of phosphorus measured by fluorescent X-rays, and as a result, when the second HTO layer 19 is grown at 775 ° C, The residual amount was about 83%.

The diffusion of impurities (phosphorus) contained in the amorphous silicon layer 15 to the outside is suppressed as compared with the case where the residual amount of impurities when the composition ratio of silicon in the tungsten silicide layer is 2.55 is about 35% (prior art). It turned out that the effect to become remarkable becomes.

In this example, since the silicon composition ratio of the portion of the tungsten silicide layer 16 in contact with the amorphous silicon layer 15 is 2.55, and the content of tungsten is reduced, the amorphous silicon layer 15 and the tungsten silicide layer 16 are reduced. Adhesion with is improved.

As the structure of the gate electrode 18, a polyside structure as shown in the first example may be adopted.

[Other examples]

In the gate electrode of the above-described MOSFET, two layers of tungsten silicide layers (WSi _x ) having a silicon composition ratio x of 2.55 and 2.4 or less are used, and one layer of tungsten silicide layers in which x varies linearly from 2.55 to 2.4 or less. The case of using (WSi _x ) has been described. As indicated by the broken line and dashed-dotted line in FIG. 8, the composition ratio x may be a tungsten silicide layer (WSi _x ) in which _x changes stepwise from 2.55 to 2.4 or less, and x is a single layer having 2.4 or less. It may be comprised.

The impurities introduced in the polycide structure described above are not limited to phosphorus, but may be arsenic, boron, or the like.

In addition, in the above example, the case where the polyside structure is adopted as the gate electrode of the MOSFET has been described. However, the case where the polyside structure is employed in the lead-out electrode of the bipolar transistor, etc., is formed as described above. High resistance is suppressed.

In the above example, the HTO film is formed as the insulating film covering the electrode of the polycide structure, but the above-described results can be obtained even when the electrode is covered by the insulating film formed at a temperature of 700 ° C or higher.

In the above example, when forming the tungsten silicide layer, monosilane gas is used, but disilane (Si ₂ H ₆ ) and trisilane (Si ₃ H ₈ ) may be used. Impurities in the silicon layer of the polyside structure may be included when the silicon layer is grown using gases such as PH ₃ and AsH ₃ .

Claims (18)

A silicon layer including an impurity formed on the semiconductor layer via an insulating film; A first tungsten silicide layer formed on the silicon layer and having a composition ratio of silicon to tungsten greater than 2.4; A gate electrode of a gate insulation type field effect transistor having a polyside structure formed on the first tungsten silicide layer and comprising a second tungsten silicide layer having a composition ratio of silicon to tungsten of 2.0 to 2.4, and both sides of the gate electrode. And a source region and a drain region are formed in the semiconductor layer of the semiconductor device. The semiconductor device according to claim 1, wherein said second tungsten silicide layer has a thickness of 200 GPa or more. The semiconductor device according to claim 1, wherein said silicon layer is polycrystalline silicon or amorphous silicon. The semiconductor device according to claim 1, wherein said electrode is covered with an insulating film formed at a temperature of 700 to 775 캜. The semiconductor device according to claim 4, wherein said insulating film is a silicon oxide film. A silicon layer containing impurities formed over the semiconductor layer via an insulating film; A gate electrode of a gate insulation type field effect transistor having a polyside structure comprising a tungsten silicide layer in which the composition ratio of silicon to tungsten increases continuously or stepwise from 2.0 to 2.4 from the surface not in contact with the silicon layer. And a source region and a drain region are formed in the semiconductor layers on both sides of the gate electrode. 7. The semiconductor device according to claim 6, wherein the composition ratio of said silicon constituting said tungsten silicide layer varies from 2.0 to 2.4 to 2.55. The semiconductor device according to claim 6, wherein said silicon layer is polycrystalline silicon or amorphous silicon. The semiconductor device according to claim 6, wherein the electrode is covered with an insulating film formed at a temperature of 700 to 775 캜. The semiconductor device according to claim 9, wherein said insulating film is a silicon oxide film. Forming a silicon layer containing impurities on the semiconductor layer via an insulating layer; Forming a first tungsten silicide layer having a composition ratio of silicon to tungsten greater than 2.4 on the silicon layer; Forming a second tungsten silicide layer having a composition ratio of silicon to tungsten of 2.0 to 2.4 on the first tungsten silicide layer; Patterning at least the silicon layer and the first and second tungsten silicide layers to form a gate electrode of a gate insulation type field effect transistor having a polyside structure; And forming a source region and a drain region by introducing impurities into the semiconductor layers on both sides of the gate electrode. 12. The method of claim 11, wherein the second tungsten silicide layer is formed using a silane gas and a tungsten hexafluoride gas. The semiconductor of claim 11, wherein the second tungsten silicide layer is formed using a monosilane gas and a tungsten hexafluoride gas, and the flow rate of the monosilane gas is 83 times or less than the flow rate of the tungsten hexafluoride gas. Method of manufacturing the device. The method of manufacturing a semiconductor device according to claim 11, wherein said second tungsten silicide layer is grown at a temperature in the range of 250 [deg.] C to 380 [deg.] C. The method of manufacturing a semiconductor device according to claim 11, wherein after forming the electrode, the insulating film covering the electrode is vapor-grown at a temperature of 700 ° C or more and 775 ° C or less. The method of manufacturing a semiconductor device according to claim 15, wherein said insulating film is a silicon oxide film. Forming a silicon layer containing impurities on the semiconductor layer via an insulating layer; Forming a tungsten silicide layer on the silicon layer in which the composition ratio of silicon to tungsten increases continuously or stepwise from 2.0 to 2.4 from a surface not in contact with the silicon layer to a surface in contact; Patterning at least the tungsten silicide layer and the silicon layer to form a gate electrode of a gate insulation type field effect transistor having a polyside structure; And forming a source region and a drain region by introducing impurities into the semiconductor layers on both sides of the gate electrode. The tungsten silicide layer is formed by using monosilane gas and tungsten hexafluoride gas, and when forming the lower layer, the flow rate of monosilane gas is greater than 83 times the flow rate of tungsten hexafluoride gas. And the flow rate of the monosilane gas is 83 times or less than the flow rate of the tungsten hexafluoride gas immediately before the growth is stopped.