CA1168765A - Method for making short channel transistor devices - Google Patents
Method for making short channel transistor devicesInfo
- Publication number
- CA1168765A CA1168765A CA000374257A CA374257A CA1168765A CA 1168765 A CA1168765 A CA 1168765A CA 000374257 A CA000374257 A CA 000374257A CA 374257 A CA374257 A CA 374257A CA 1168765 A CA1168765 A CA 1168765A
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- Prior art keywords
- layer
- oxide layer
- oxide
- silicon dioxide
- silicon
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Levinstein, H.?. 28 METHOD FOR MAKING
SHORT CHANNEL TRANSISTOR
DEVICES
Abstract of the Disclosure An oxide coating on the top and side surfaces of a polycrystalline silicon gate electrode is anisotropically etched at the same time that an oxide coating on the source and drain regions is etched, whereby the oxide is completely removed from the source and drain regions but not from the top or side surface of the gate electrode.
SHORT CHANNEL TRANSISTOR
DEVICES
Abstract of the Disclosure An oxide coating on the top and side surfaces of a polycrystalline silicon gate electrode is anisotropically etched at the same time that an oxide coating on the source and drain regions is etched, whereby the oxide is completely removed from the source and drain regions but not from the top or side surface of the gate electrode.
Description
Levinstein, Il.J. 28 METHOD FOR MAICING
S~IORT CHI~NNEL TRA~SISTOR
DEVICES
5 Field of the Invention This invention relates to the field of semiconductor device fabrication, and more particularly to methods for making metal oxide semiconductor field effect transistor (MOSFET) devices.
10 Background of the Invention It is recognized in the art of semiconductor transistor device that short channels, are desirable in MOSFET devices in such devices, in order to achieve high frequency operation of the order of a GHz. By "short 15 channels" is meant those with source to drain lenqths of less than about 2 micron.
In the manufacture of short channel devices with polycrystalline silicon gate electrodes, it is difficult to control the length of the polycrystalline sllicon 20 ("polysilicon") layer defining the gate and hence the channel leng~h: this length is thus subject to fluctuatations from device to device in the usual techniques . . .
of mass fabrication of many such devices at the surface of a single crystal silicon wafer. Specifically, the actual 25 length of the channel is so small in many of the devices whose channels are supposed to be a micron in length that an undesirable "punch-through" (or "reach-through") of the depletion region of the drain to the source occurs during operation; thereby, performance of the device is de-30 graded. Moreover, the r~sistance of source terminal tothe gate region tends to be excessive in these shallow junction devices. -It would therefore be desirable to have a method for making short-channel transistors alleviating these problems.
35 Summary of the Invention This invention involves a process for fabricating a semiconductor field effect transistor at a major surface :``, - .~ .
, . . . . : ; ....................... .. ~ : .
' ~
` ~168765 o~ a silicon semiconductor body, said transistor having a polycrystalline silicon gate electrode which is insulated from said body and which is self-aligned between a pair of source and drain regions of said transistor, characterized by the step of anistropically etching of silicon dioxide on said body, at a time when the top and side surfaces of said silicon gate electrode are coated with first and second silicon dioxide layers, respectively, the first layer having a thickness greater than that of the second layer, and at the same time when said source and drain regions are coated with a third silicon dioxide layer, which is thinner than said first silicon dioxide layer, for an etching time interval which is sufficient to remove completely said third silicon dioxide layer from the source and drain regions thereby exposing the silicon body at said source and drain regions, said etching time interval being insufficient to remove completely the first and second silicon dioxide layers. By "anistropic"
etching is meant etching preferentially in the direction normal to the major surface of the body.
Brief Description of the Drawing This invention together with its features, advantages, and objects can be better understood from the following detailed description when read in conjunction with the drawing in which FIGS. 1-6 show in cross-section a sequence of various stages in the fabrication of a transistor device, specifically a MOSFET, in accordance with a specific embodiment of the invention.
Detailed Descr~
_ _ _ As shown in the sequence, FIGS 1-6, a short channel MOSFET device 20 ~FIG. 6) can be fabricated, in accordance with the invention, at a top major surface of a P-type (N-MOS technology) surface region or zone 10. As indicated in FIG. 1, this P-type region 10 is initially prepared with significant impurity doping to provide ,, . ~ . .
.
`
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. .
~ ~ 68~5 s~itable electrical conductivities at the respective interf~ces o~ this P-re~ion 10 with a relatively thick field oxi~e layer 11 and a relatively thin gate oxide layer 12, as known in the art. A polycrystalline silicon ("polysilicon") layer 13 (FIG. 1) is then deposited over the field and gate oxide layers 11 and 12, to a thickness typically in the range of about 35()0 to 5000 angstroms.
This polysilicon layer 13 is advantageously doped with significant donor impurities such as arsenic or phosphorus, particularly in the regions overlying the ultimate transistor devices and in regions of interconnections, in order to increase the electrical conductivity of the poly silicon to a range of values typically of about 10 to 10 ohms/square, suitable for a gate electrode in regions overlying the gate oxide where the polysilicon layer will function as a gate ele~trode; and, at the same time, this conductivity is suitable for electrically conductive interconnections in regions overlying the field oxide where the polysilicon layer will function as an electrical interconnection (FIG. 6). Then a silicon dioxide masking layer 14, typically having a thickness in the range of about 1000 to 2000 angstroms, is deposited on the exposed surface of the polysilicon layer by a conventional process such as oxidation in a dry atmosphere. By conventional photoresist, or electron beam or X-ray lithographic masking and etching, the oxide layer 14 and the poly-silicon layer 13 are removed except at locations where a polysilicon gate electrode layer 13 on the gate oxide 12 and a polysilicon interconnect layer 23 on the field oxide 30 11 are desired (FIG. 2). This gate electrode layer 13 will thus be coated on its top surface by a silicon dioxide gate masking layer 14' likewise, the polysilicon interconnecting layer 23 will thus be coated on its top surface with a silicon dioxide interconnect making : . ............ .
- , - - : ~ . ;.
- .
Levinstein~ ll J 28 7 ~ ~
layer 2~'. The width of the gate-electrode layer 13, in particular, can be as low as 0u8 micron, for short-channel devices.
Next, by thermal oxidation (FIG. 3), the 5 sidewalls of the polysilicon layers 13 and 23 are coated with thermally grown sidewall gate oxide layer 15 and sidewall interconnect oxide layer 2S, respectively.
Typically, the thickness of these oxide layers 15 and 25 is in the range of about 200 to 500 angstroms. Simultaneously 10 with the growth o~ the oxide layer 15 and 25, the respective thicknesses of the oxide layers 14'and 24', as well as the field oxide layer 11, will all increase somewhat as a result of the respective simultaneous thermal oxidation of the underlying silicon or polysilicon. In 15 case the length of the polysilicon layer 13 is less than what is desired for defining the length of the gate, a somewhat thicker oxide layer can be deposited on the sidewalls of the polysilicon, as by plasma deposition or low pressure chemical vapor deposition; so that the 20 resulting thicker sidewall oxide then supplies a lon~er mask against the subsequent diffusion o~ source and drain impurities, thereby reducing impurity underdiffusion in the gate region and thus increasing the source to drain distance, as is desired in such a case.
Next (FIG~ 4), the top surface of the body 10 is exposed to an anisotropic etching of the oxide layers, whereby the sidewall oxides 15 and 25 remain substantially intact while the oxide layers 14'and 241are reduced in thickness to become oxide layers 14 and 24, respectively;
and while the gate oxide layer 12 remains only in the gate region underIying the polysilicon layer 13 plus sidewall oxide 15, while the gate oxide layer 12 is completely removed in the regions between the sidewall oxide 15 and the field oxide 11, i.e~, in thé-~region~s ~f the ultima~e source and drain. For example, a chemically reactive sputter etching (backsputtering) process using fluoride ions in a plasma produced by CHF3 can be employed for this . , .
' ' ` ~. :' ' ~:
;8~6~
anistropic etching of the oxide layers. This back-sputtering process is terminated when the surface of the silicon bo~ 10 is exposed in the source and drain regions, or a short time thereafter, so that there stil] remains some oxide in the layers 1~ and 24 covering the top surface of the polysilicon electrocle layers 13 and 23, respectively. Since, the thickness of the masking oxide 14 is considerably greater than that of the gate oxide 12, a considerable margin thus exits to enable the remaining oxide layers 14 and 2~ to be of sufficient thickness, typically of about 1000 angstrom, to prevent the formation of silicide on the gate electrode 13.
Next, a donor impurity is introduced, as by ion implantation and diffusion, into the source and drain areas, to form diffused source and drain regions 10.1 and 10.2, respectively, (FIG. 5), contiguous with the surface of the silicon body. For example, a dose of arsenic is implanted at about 30 Kev and diffused to a concentration typically in the range of about 1019 to 102 per cubic centimeter. By "diffused" in this context is meant to include any thermal diffusion step either simultaneous with or subsequent to the impurity implantation step.
Then the top surface of the body 10 is subjected to a bombardment with a metal, such as titanium, which forms metal silicide layers 16, 17, typically of a thickness of a few hundred angstroms, at the exposed portions of the silicon. The metal which remains after bombardment on the surface of the oxide areas is removed by etching; for example titanium can be etched with ethylene-diamine-tetra-acetic-acid (EDTA). This etching, however, leaves intact the metal silicide layers 16, 17~ The amount of metal deposited on the oxide may be minimized by suitable adjustment of the various parameters of the metal bombardment.
... ~ . ............. .
.
.
. ~ :
' , Levinstein~ ll J 2~
Next~ the top surface of the body 10 is coated at selected areas by conventional deposition, masking, and etching techniques, with an insulating layer 22, such as tetra-ethyl-ortho-silicate, typically of a thickness in the 5 ranye of about 5000 to 10,000 angstroms. By further conventional techniques, metallization is then applied contacting the rnetal silicide layers 16 and 17, in order to form the respective electrode metallization contacts 19 and 21 for the source and drain; at the same time, this 10 metallization is also applied contacting the polysilicon layers 13 and 23 through apertures in the insulating layer 22, in order to form electrode metallization contacts 1~ and 28 for the gate and the interconnections.
It is obvious that reduced parasitic lateral resistance in lS the shallow source 10.1 and shallow drain 10.2 is afforded by the metal silicide layers 16 and 17, and that a reduced yate electrode overlap parasitic capacitance also results, as compared with more conventional methods.
~lthough the invention has been described in 20 terms of a specific embodiment, various modifications can be made without departing from the scope of the invention.
For example, instead of titanium, other transition metals can be used which form silicides, such as cobalt, or platinum, or tantalum. However, titanium or cobalt is 25 preferred in that these rnetals diffus~into silicon an thus, form more readily a desirable contact with the doped polysilicon layers.
~ ' ' ~ , : .
,
S~IORT CHI~NNEL TRA~SISTOR
DEVICES
5 Field of the Invention This invention relates to the field of semiconductor device fabrication, and more particularly to methods for making metal oxide semiconductor field effect transistor (MOSFET) devices.
10 Background of the Invention It is recognized in the art of semiconductor transistor device that short channels, are desirable in MOSFET devices in such devices, in order to achieve high frequency operation of the order of a GHz. By "short 15 channels" is meant those with source to drain lenqths of less than about 2 micron.
In the manufacture of short channel devices with polycrystalline silicon gate electrodes, it is difficult to control the length of the polycrystalline sllicon 20 ("polysilicon") layer defining the gate and hence the channel leng~h: this length is thus subject to fluctuatations from device to device in the usual techniques . . .
of mass fabrication of many such devices at the surface of a single crystal silicon wafer. Specifically, the actual 25 length of the channel is so small in many of the devices whose channels are supposed to be a micron in length that an undesirable "punch-through" (or "reach-through") of the depletion region of the drain to the source occurs during operation; thereby, performance of the device is de-30 graded. Moreover, the r~sistance of source terminal tothe gate region tends to be excessive in these shallow junction devices. -It would therefore be desirable to have a method for making short-channel transistors alleviating these problems.
35 Summary of the Invention This invention involves a process for fabricating a semiconductor field effect transistor at a major surface :``, - .~ .
, . . . . : ; ....................... .. ~ : .
' ~
` ~168765 o~ a silicon semiconductor body, said transistor having a polycrystalline silicon gate electrode which is insulated from said body and which is self-aligned between a pair of source and drain regions of said transistor, characterized by the step of anistropically etching of silicon dioxide on said body, at a time when the top and side surfaces of said silicon gate electrode are coated with first and second silicon dioxide layers, respectively, the first layer having a thickness greater than that of the second layer, and at the same time when said source and drain regions are coated with a third silicon dioxide layer, which is thinner than said first silicon dioxide layer, for an etching time interval which is sufficient to remove completely said third silicon dioxide layer from the source and drain regions thereby exposing the silicon body at said source and drain regions, said etching time interval being insufficient to remove completely the first and second silicon dioxide layers. By "anistropic"
etching is meant etching preferentially in the direction normal to the major surface of the body.
Brief Description of the Drawing This invention together with its features, advantages, and objects can be better understood from the following detailed description when read in conjunction with the drawing in which FIGS. 1-6 show in cross-section a sequence of various stages in the fabrication of a transistor device, specifically a MOSFET, in accordance with a specific embodiment of the invention.
Detailed Descr~
_ _ _ As shown in the sequence, FIGS 1-6, a short channel MOSFET device 20 ~FIG. 6) can be fabricated, in accordance with the invention, at a top major surface of a P-type (N-MOS technology) surface region or zone 10. As indicated in FIG. 1, this P-type region 10 is initially prepared with significant impurity doping to provide ,, . ~ . .
.
`
~, : , ' .
. .
~ ~ 68~5 s~itable electrical conductivities at the respective interf~ces o~ this P-re~ion 10 with a relatively thick field oxi~e layer 11 and a relatively thin gate oxide layer 12, as known in the art. A polycrystalline silicon ("polysilicon") layer 13 (FIG. 1) is then deposited over the field and gate oxide layers 11 and 12, to a thickness typically in the range of about 35()0 to 5000 angstroms.
This polysilicon layer 13 is advantageously doped with significant donor impurities such as arsenic or phosphorus, particularly in the regions overlying the ultimate transistor devices and in regions of interconnections, in order to increase the electrical conductivity of the poly silicon to a range of values typically of about 10 to 10 ohms/square, suitable for a gate electrode in regions overlying the gate oxide where the polysilicon layer will function as a gate ele~trode; and, at the same time, this conductivity is suitable for electrically conductive interconnections in regions overlying the field oxide where the polysilicon layer will function as an electrical interconnection (FIG. 6). Then a silicon dioxide masking layer 14, typically having a thickness in the range of about 1000 to 2000 angstroms, is deposited on the exposed surface of the polysilicon layer by a conventional process such as oxidation in a dry atmosphere. By conventional photoresist, or electron beam or X-ray lithographic masking and etching, the oxide layer 14 and the poly-silicon layer 13 are removed except at locations where a polysilicon gate electrode layer 13 on the gate oxide 12 and a polysilicon interconnect layer 23 on the field oxide 30 11 are desired (FIG. 2). This gate electrode layer 13 will thus be coated on its top surface by a silicon dioxide gate masking layer 14' likewise, the polysilicon interconnecting layer 23 will thus be coated on its top surface with a silicon dioxide interconnect making : . ............ .
- , - - : ~ . ;.
- .
Levinstein~ ll J 28 7 ~ ~
layer 2~'. The width of the gate-electrode layer 13, in particular, can be as low as 0u8 micron, for short-channel devices.
Next, by thermal oxidation (FIG. 3), the 5 sidewalls of the polysilicon layers 13 and 23 are coated with thermally grown sidewall gate oxide layer 15 and sidewall interconnect oxide layer 2S, respectively.
Typically, the thickness of these oxide layers 15 and 25 is in the range of about 200 to 500 angstroms. Simultaneously 10 with the growth o~ the oxide layer 15 and 25, the respective thicknesses of the oxide layers 14'and 24', as well as the field oxide layer 11, will all increase somewhat as a result of the respective simultaneous thermal oxidation of the underlying silicon or polysilicon. In 15 case the length of the polysilicon layer 13 is less than what is desired for defining the length of the gate, a somewhat thicker oxide layer can be deposited on the sidewalls of the polysilicon, as by plasma deposition or low pressure chemical vapor deposition; so that the 20 resulting thicker sidewall oxide then supplies a lon~er mask against the subsequent diffusion o~ source and drain impurities, thereby reducing impurity underdiffusion in the gate region and thus increasing the source to drain distance, as is desired in such a case.
Next (FIG~ 4), the top surface of the body 10 is exposed to an anisotropic etching of the oxide layers, whereby the sidewall oxides 15 and 25 remain substantially intact while the oxide layers 14'and 241are reduced in thickness to become oxide layers 14 and 24, respectively;
and while the gate oxide layer 12 remains only in the gate region underIying the polysilicon layer 13 plus sidewall oxide 15, while the gate oxide layer 12 is completely removed in the regions between the sidewall oxide 15 and the field oxide 11, i.e~, in thé-~region~s ~f the ultima~e source and drain. For example, a chemically reactive sputter etching (backsputtering) process using fluoride ions in a plasma produced by CHF3 can be employed for this . , .
' ' ` ~. :' ' ~:
;8~6~
anistropic etching of the oxide layers. This back-sputtering process is terminated when the surface of the silicon bo~ 10 is exposed in the source and drain regions, or a short time thereafter, so that there stil] remains some oxide in the layers 1~ and 24 covering the top surface of the polysilicon electrocle layers 13 and 23, respectively. Since, the thickness of the masking oxide 14 is considerably greater than that of the gate oxide 12, a considerable margin thus exits to enable the remaining oxide layers 14 and 2~ to be of sufficient thickness, typically of about 1000 angstrom, to prevent the formation of silicide on the gate electrode 13.
Next, a donor impurity is introduced, as by ion implantation and diffusion, into the source and drain areas, to form diffused source and drain regions 10.1 and 10.2, respectively, (FIG. 5), contiguous with the surface of the silicon body. For example, a dose of arsenic is implanted at about 30 Kev and diffused to a concentration typically in the range of about 1019 to 102 per cubic centimeter. By "diffused" in this context is meant to include any thermal diffusion step either simultaneous with or subsequent to the impurity implantation step.
Then the top surface of the body 10 is subjected to a bombardment with a metal, such as titanium, which forms metal silicide layers 16, 17, typically of a thickness of a few hundred angstroms, at the exposed portions of the silicon. The metal which remains after bombardment on the surface of the oxide areas is removed by etching; for example titanium can be etched with ethylene-diamine-tetra-acetic-acid (EDTA). This etching, however, leaves intact the metal silicide layers 16, 17~ The amount of metal deposited on the oxide may be minimized by suitable adjustment of the various parameters of the metal bombardment.
... ~ . ............. .
.
.
. ~ :
' , Levinstein~ ll J 2~
Next~ the top surface of the body 10 is coated at selected areas by conventional deposition, masking, and etching techniques, with an insulating layer 22, such as tetra-ethyl-ortho-silicate, typically of a thickness in the 5 ranye of about 5000 to 10,000 angstroms. By further conventional techniques, metallization is then applied contacting the rnetal silicide layers 16 and 17, in order to form the respective electrode metallization contacts 19 and 21 for the source and drain; at the same time, this 10 metallization is also applied contacting the polysilicon layers 13 and 23 through apertures in the insulating layer 22, in order to form electrode metallization contacts 1~ and 28 for the gate and the interconnections.
It is obvious that reduced parasitic lateral resistance in lS the shallow source 10.1 and shallow drain 10.2 is afforded by the metal silicide layers 16 and 17, and that a reduced yate electrode overlap parasitic capacitance also results, as compared with more conventional methods.
~lthough the invention has been described in 20 terms of a specific embodiment, various modifications can be made without departing from the scope of the invention.
For example, instead of titanium, other transition metals can be used which form silicides, such as cobalt, or platinum, or tantalum. However, titanium or cobalt is 25 preferred in that these rnetals diffus~into silicon an thus, form more readily a desirable contact with the doped polysilicon layers.
~ ' ' ~ , : .
,
Claims (13)
1. A process for fabricating a semiconductor field effect transistor at a major surface of a silicon semi-conductor body, said transistor having a polycrystalline silicon gate electrode which is insulated from said body and which is self-aligned between a pair of source and drain regions of said transistor, CHARACTERIZED BY
the step of anisotropically etching of silicon dioxide on said body, at a time when the top and side sur-faces of said silicon gate electrode are coated with, respectively, first and second silicon dioxide layers, the first layer having a thickness greater than that of the second layer, and at the same time when said source and drain regions are coated with a third silicon dioxide layer which is thinner than said first silicon dioxide layer, for an etching time interval which is sufficient to remove completely said third silicon dioxide layer from the source and drain regions thereby exposing the silicon body at said source and drain regions, said etching time interval being insufficient to remove completely the first and second silicon dioxide layers.
the step of anisotropically etching of silicon dioxide on said body, at a time when the top and side sur-faces of said silicon gate electrode are coated with, respectively, first and second silicon dioxide layers, the first layer having a thickness greater than that of the second layer, and at the same time when said source and drain regions are coated with a third silicon dioxide layer which is thinner than said first silicon dioxide layer, for an etching time interval which is sufficient to remove completely said third silicon dioxide layer from the source and drain regions thereby exposing the silicon body at said source and drain regions, said etching time interval being insufficient to remove completely the first and second silicon dioxide layers.
2. The process of claim 1 FURTHER CHARACTERIZED BY
the step of bombarding the said surface of the body with a transition metal which can form a silicide whereby the silicide of said metal is formed at said exposed source and drain regions.
the step of bombarding the said surface of the body with a transition metal which can form a silicide whereby the silicide of said metal is formed at said exposed source and drain regions.
3. The process of claim 2 in which the transition metal is removed by etching from the exposed oxide areas and in which a gate oxide layer portion of said third oxide layer intervenes between said polycrystalline layer and said major surface of the body.
4. The process of claims 2 or 3 in which said metal is titanium or cobalt.
Levinstein, H.J. 28
Levinstein, H.J. 28
5. The process of claims 1 or 2 or 3 in which a first thickness of the first silicon dioxide layer, which is less than the total thickness of said first silicon dioxide layer, is formed by a first thermal oxide growth step prior to forming the remaining thickness of said first silicon dioxide layer by a second thermal growth step during which the entire thickness of the second silicon dioxide layer is formed.
6. The process of claim 2 in which said source and drain regions are implanted with a significant impurity prior to said step of bombardment.
7. The process of claim 6 in which a first thickness of the first silicon dioxide layer which is less than the total thickness thereof is formed by a first thermal oxide growth step.
8. A method for making semiconductor apparatus, having a polycrystalline silicon gate electrode layer separated from a major surface of a semiconductive silicon body by a gate oxide layer, which comprise the steps of:
(a) forming a first oxide layer on a first portion of said major surface of the body;
(b) forming a first polycrystalline silicon gate electrode layer on a limited portion of said first oxide layer;
(c) forming a second oxide layer on a top, exposed surface of said polycrystalline silicon layer and a third oxide layer on a side, exposed surface of said first poly-crystalline layer, said second oxide layer being thicker than said first oxide layer;
(d) anisotropically etching said first, second, and third oxide layers to remove completely said first oxide layer in regions which are situated in the complement of said limited portion thereof and not to remove the third oxide layer nor to remove the gate oxide layer portion of the first oxide layer underlying the first polycrystalline layer and the third oxide layer.
(a) forming a first oxide layer on a first portion of said major surface of the body;
(b) forming a first polycrystalline silicon gate electrode layer on a limited portion of said first oxide layer;
(c) forming a second oxide layer on a top, exposed surface of said polycrystalline silicon layer and a third oxide layer on a side, exposed surface of said first poly-crystalline layer, said second oxide layer being thicker than said first oxide layer;
(d) anisotropically etching said first, second, and third oxide layers to remove completely said first oxide layer in regions which are situated in the complement of said limited portion thereof and not to remove the third oxide layer nor to remove the gate oxide layer portion of the first oxide layer underlying the first polycrystalline layer and the third oxide layer.
9. The method of claim 8 in which a second poly-crystalline silicon interconnect electrode layer is formed on a fourth field oxide layer simultaneously with the forming of said first polycrystalline silicon layer, said fourth oxide layer being located contiguous with a second portion of said major surface situated in the complement of said first portion thereof, said fourth oxide layer being sufficiently thicker than said first oxide layer that said fourth oxide layer is not completely removed by said etching.
10. The method of claim 9 in which a fifth oxide layer is formed on a side surface of said second poly-crystalline layer simultaneously with the forming of said third oxide layer on said side surface of the first polycrystalline gate layer.
11. The method of claim 9 in which said first, second, and third oxide layers are all essentially silicon dioxide.
12. The method of claim 11 which further comprises the step of bombarding the body with metal which forms a silicide at the major surface of the body where said first oxide layer has been completely removed by said etching.
13. The method of claims 9 or 10 which further comprises the step of bombarding the body with metal which forms a silicide at the major surface of the body where said first oxide layer has been completely removed by said etching.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US14112180A | 1980-04-17 | 1980-04-17 | |
| US141,121 | 1980-04-17 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1168765A true CA1168765A (en) | 1984-06-05 |
Family
ID=22494250
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000374257A Expired CA1168765A (en) | 1980-04-17 | 1981-03-31 | Method for making short channel transistor devices |
Country Status (1)
| Country | Link |
|---|---|
| CA (1) | CA1168765A (en) |
-
1981
- 1981-03-31 CA CA000374257A patent/CA1168765A/en not_active Expired
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