KR20000041397A - Method of forming gate electrode of high integrated memory device - Google Patents
Method of forming gate electrode of high integrated memory device Download PDFInfo
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- KR20000041397A KR20000041397A KR1019980057256A KR19980057256A KR20000041397A KR 20000041397 A KR20000041397 A KR 20000041397A KR 1019980057256 A KR1019980057256 A KR 1019980057256A KR 19980057256 A KR19980057256 A KR 19980057256A KR 20000041397 A KR20000041397 A KR 20000041397A
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- Prior art keywords
- tungsten silicide
- film
- silicon
- gate electrode
- forming
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- 238000000034 method Methods 0.000 title claims abstract description 28
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 claims abstract description 81
- 229910021342 tungsten silicide Inorganic materials 0.000 claims abstract description 81
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 49
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 49
- 239000010703 silicon Substances 0.000 claims abstract description 49
- 229910052751 metal Inorganic materials 0.000 claims abstract description 16
- 239000002184 metal Substances 0.000 claims abstract description 16
- 238000000151 deposition Methods 0.000 claims abstract description 10
- 239000000758 substrate Substances 0.000 claims abstract description 10
- 239000004065 semiconductor Substances 0.000 claims abstract description 8
- 238000005530 etching Methods 0.000 claims abstract description 6
- 238000010438 heat treatment Methods 0.000 claims description 14
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 7
- 239000000126 substance Substances 0.000 claims description 4
- 238000004519 manufacturing process Methods 0.000 claims description 2
- 238000000059 patterning Methods 0.000 claims description 2
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 abstract 1
- 229910021332 silicide Inorganic materials 0.000 abstract 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 abstract 1
- 239000010408 film Substances 0.000 description 60
- 239000010410 layer Substances 0.000 description 19
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 8
- 229920005591 polysilicon Polymers 0.000 description 7
- 239000010409 thin film Substances 0.000 description 5
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 230000008021 deposition Effects 0.000 description 3
- 230000010354 integration Effects 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 3
- 239000012535 impurity Substances 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 230000001052 transient effect Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28097—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a metallic silicide
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/32051—Deposition of metallic or metal-silicide layers
- H01L21/32053—Deposition of metallic or metal-silicide layers of metal-silicide layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
- H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
- H01L29/4933—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a silicide layer contacting the silicon layer, e.g. Polycide gate
Abstract
Description
본 발명은 반도체 메모리소자의 게이트전극(워드라인) 형성방법에 관한 것으로, 1Gb(giga bit)급 이상의 다이나믹램(Dynamic RAM, 이하 DRAM이라 칭함)과 같은 초고집적화와 고속 동작을 요구하는 반도체 메모리소자에서의 게이트전극 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a gate electrode (word line) of a semiconductor memory device. The present invention relates to a semiconductor memory device requiring ultra-high integration and high speed operation, such as 1Gb (giga bit) or more of dynamic RAM (DRAM). A method of forming a gate electrode in
현재 반도체 메모리소자는 크게 리드/라이트(read/write) 메모리와 리드전용메모리(ROM)로 구분할 수 있다. 특히 리드/라이트 메모리는 DRAM과 스태틱램(static RAM)으로 나뉘어진다. DRAM은 1개의 트랜지스터(transistor)와 1개의 커패시터(capacitor)로 1개의 단위 셀(cell)이 구성되어 집적도에서 가장 앞서고 있는 소자이다.Currently, semiconductor memory devices can be classified into read / write memory and read-only memory (ROM). In particular, the read / write memory is divided into DRAM and static RAM. DRAM is one of the most advanced devices in terms of integration because one unit cell is composed of one transistor and one capacitor.
한편, 고집적화의 진전으로 3년에 메모리의 용량이 4배씩 증가되어 이미 256Mb(mega bit) DRAM의 개발이 이루어졌고 1Gb(giga bit)에 대한 연구가 진행되고 있다. 이와 같이 DRAM의 집적도가 높아질수록 전기 신호를 읽고 기록하는 역할을 하는 셀의 면적은 1Gb의 경우 대략 0.08
이러한 문제를 해결하기 위해 메탈 리치 텅스텐실리사이드(metal-rich WSix)를 증착한후 하부 폴리실리콘과 반응시켜 텅스텐실리사이드의 그레인 사이즈(Grain Size)를 증가시켜 비저항을 낮추는 방법이 제안되어 있다. 그러나 이 경우 텅스텐실리사이드의 하부 폴리실리콘의 실리콘 소모가 너무 많고 또 분균일 하게 소모 되는 관계로 텅스텐실리사이드의 표면 및 텅스텐실리사이드와 폴리실리콘 간의 계면(Interface)이 러프(Rough)해져 후속 포토리소그라피(Photolithography) 및 식각(Etch) 공정에 많은 어려움을 준다. 또한 불균일한 폴리실리콘의 두께는 그 하부의 게이트산화막(Gate Oxide) 신뢰성에도 나쁜 영향을 줄 수 있다. 도1은 이러한 문제점을 갖는 종래기술에 따른 게이트전극 형성 단면도로서, 실리콘기판(1) 상에 게이트산화막(2), 폴리실리콘막(3), 및 저저항 텅스텐실리사이드막(4)이 형성된 상태로서, 폴리실리콘막(3)과 저저항 텅스텐실리사이드막(4)의 계면 및 저저항 텅스텐실리사이드막(4)의 표면이 매우 러프해져 있음을 보여주고 있다.In order to solve this problem, a method of depositing metal-rich tungsten silicide (metal-rich WSix) and reacting with lower polysilicon to increase the grain size of tungsten silicide to reduce the specific resistance has been proposed. However, in this case, since the silicon consumption of the lower polysilicon of tungsten silicide is too much and uniformly consumed, the surface of the tungsten silicide and the interface between tungsten silicide and polysilicon are roughened, and subsequent photolithography is performed. And Etch process gives a lot of difficulties. In addition, the non-uniform thickness of polysilicon may adversely affect the gate oxide reliability of the lower portion thereof. 1 is a cross-sectional view of a gate electrode forming according to the prior art having such a problem, in which a gate oxide film 2, a polysilicon film 3, and a low resistance tungsten silicide film 4 are formed on a silicon substrate 1; The interface between the polysilicon film 3 and the low resistance tungsten silicide film 4 and the surface of the low resistance tungsten silicide film 4 are very rough.
본 발명은 상술한 바와 같은 종래기술의 문제점을 해결하기 위하여 안출된 것으로써, 낮은 비저항을 가짐과 동시에 그 표면 및 실리콘과의 계면에서 매끈하고 균일한 양질의 텅스텐실리사이드막을 형성하기 위한, 고집적 메모리소자의 게이트전극용 텅스텐실리사이드막 형성방법을 제공하는데 목적이 있다.SUMMARY OF THE INVENTION The present invention has been made to solve the problems of the prior art as described above, and has a low specific resistance and at the same time a high density memory device for forming a smooth and uniform high quality tungsten silicide film at its surface and interface with silicon. It is an object to provide a method for forming a tungsten silicide film for a gate electrode.
도1은 종래기술에 따라 게이트전극을 형성했을때의 단면도,1 is a cross-sectional view when a gate electrode is formed according to the prior art;
도2a 내지 도2d는 본 발명의 일실시예에 따른 게이트전극 형성 공정을 나타내는 단면도.2A to 2D are cross-sectional views illustrating a gate electrode forming process according to an embodiment of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
203 : 실리콘막203 silicon film
204 : 실리콘 리치 텅스텐실리사이드막(Si-rich WSix)204: silicon rich tungsten silicide film (Si-rich WSix)
205 : 메탈 리치 텅스텐실리사이드막(Metal-rich WSix)205: metal rich tungsten silicide film (Metal-rich WSix)
상기 목적을 달성하기 위한 본 발명은, 고집적 메모리소자의 게이트전극용 텅스텐실리사이드막 형성방법에 있어서, 실리콘막 상에 비정질의 실리콘 리치 제1텅스텐실리사이드막을 증착하는 단계; 상기 제1텅스텐실리사이드막 상에 메탈 리치 제2텅스텐실리사이드막을 형성하는 단계; 및 열처리하여 상기 제1 및 제2 텅스텐실리사이드막을 상기 실리콘막과 반응시켜 저저항을 갖는 제3텅스텐실리사이드층으로 형성하는 단계를 포함하여 이루어지는 것을 특징으로 한다.According to an aspect of the present invention, there is provided a method of forming a tungsten silicide film for a gate electrode of a highly integrated memory device, comprising: depositing an amorphous silicon rich first tungsten silicide film on a silicon film; Forming a metal rich second tungsten silicide layer on the first tungsten silicide layer; And heat treating the first and second tungsten silicide layers to form a third tungsten silicide layer having a low resistance by reacting with the silicon film.
또한 본 발명은, 고집적 메모리소자 제조방법에 있어서, 반도체기판 상에 게이트절연막, 게이트전극용 실리콘막을 적층하는 단계; 상기 실리콘막 상에 비정질의 실리콘 리치 제1텅스텐실리사이드막을 증착하는 단계; 상기 제1텅스텐실리사이드막 상에 메탈 리치 제2텅스텐실리사이드막을 형성하는 단계; 상기 제2텅스텐실리사이드막 상에 마스크용 절연막을 형성하는 단계; 열처리하여 상기 제1 및 제2 텅스텐실리사이드막을 상기 실리콘막과 반응시켜 저저항을 갖는 제3텅스텐실리사이드층으로 형성하는 단계; 및 게이트 마스크 및 식각 공정으로 상기 절연막과 상기 제3텅스텐실리사이드막 및 상기 열처리시 반응하고 잔류하는 상기 실리콘막을 패터닝하는 단계를 포함하여 이루어진다.In addition, the present invention provides a method for manufacturing a highly integrated memory device, comprising: stacking a gate insulating film and a silicon film for a gate electrode on a semiconductor substrate; Depositing an amorphous silicon rich first tungsten silicide film on the silicon film; Forming a metal rich second tungsten silicide layer on the first tungsten silicide layer; Forming an insulating film for a mask on the second tungsten silicide layer; Heat treatment to react the first and second tungsten silicide films with the silicon film to form a third tungsten silicide layer having low resistance; And patterning the insulating layer, the third tungsten silicide layer, and the silicon layer reacting and remaining during the heat treatment by a gate mask and an etching process.
본 발명에서, 상기 열처리후에 상기 실리콘막은 500∼1000Å의 두께가 잔류하며, 상기 저저항 텅스텐실리사이드막은 750∼1500Å의 두께를 갖도록 상기 열처리와 각 박막의 증착 두께를 조절하는 것이 바람직하다.In the present invention, after the heat treatment, the silicon film has a thickness of 500 to 1000 GPa, and the low-resistance tungsten silicide film is preferably adjusted to the heat treatment and the deposition thickness of each thin film to have a thickness of 750 to 1500 GPa.
상술한 바와 같이 본 발명은, 종래 메탈 리치 텅스텐실리사이드 전극 공정의 문제를 해결하기위해, 본 발명에서는 텅스텐실리사이드 증착시 비정질상의 실리콘 리치 텅스텐실리사이드막을 증착한후 다시 그 위에 메탈 리치 텅스텐실리사이드막을 증착하고 열처리하는 것에 그 특징을 갖는다. 실리콘 리치 텅스텐실리사이드는 하부의 실리콘막과 과도한 반응을 억제할 수 있다. 그리고, 실리콘 리치 텅스텐 실리사이드막은 비정질 상태로 또한 충분히 얇을 경우 메탈 리치 텅스텐실리사이드막과 실리콘막과의 반응을 균일하게 조정할 수 있다. 이 결과 그레인 사이즈(Grain Size)가 크고 이에 의해 비저항이 낮으면서, 그 표면 및 실리콘과의 계면이 러프하지 않고 균일한 양질의 저저항 텅스텐실리사이드막 형성이 가능하다.As described above, in order to solve the problem of the conventional metal rich tungsten silicide electrode process, in the present invention, after depositing an amorphous silicon rich tungsten silicide film during tungsten silicide deposition, a metal rich tungsten silicide film is deposited thereon and heat treated. It has that characteristic. Silicon rich tungsten silicide can suppress excessive reaction with the underlying silicon film. When the silicon rich tungsten silicide film is in an amorphous state and sufficiently thin, the reaction between the metal rich tungsten silicide film and the silicon film can be uniformly adjusted. As a result, the grain size is large and the resistivity is low, thereby making it possible to form a uniform high quality low resistance tungsten silicide film without roughing the surface and the interface with silicon.
이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부된 도면을 참조하여 설명하기로 한다.DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.
도2a 내지 도2d는 본 발명의 일실시예에 따른 게이트전극 형성 공정을 나타내는 단면도이다.2A through 2D are cross-sectional views illustrating a gate electrode forming process according to an exemplary embodiment of the present invention.
먼저, 도2a를 참조하면, 실리콘기판(201)을 열산화시켜 게이트절연막(202)을 형성하고 도핑된 실리콘막(203)을 증착한 다음, 그 위에 비정질의 실리콘 리치(rich) 텅스텐실리사이드막(204)과, 메탈 리치 텅스텐실리사이드막(205)을 순서적으로 적층한다. 그리고 다시 화학기상증착(CVD)에 의해 절연막(206)을 증착한다.First, referring to FIG. 2A, the silicon substrate 201 is thermally oxidized to form a gate insulating film 202, and a doped silicon film 203 is deposited thereon, followed by an amorphous silicon rich tungsten silicide film ( 204 and the metal rich tungsten silicide film 205 are sequentially stacked. The insulating film 206 is then deposited by chemical vapor deposition (CVD).
실리콘 리치 텅스텐실리사이드막(204)은 SiH4및 WF6를 사용하여 비정질 상태로 50∼100Å 증착하고, 2.4∼2.8 정도의 화학정량(Strochiometry)을 갖도록 한다.The silicon rich tungsten silicide film 204 is deposited to 50 to 100 GPa in an amorphous state by using SiH 4 and WF 6 to have a chemical stoichiometry of about 2.4 to 2.8.
메탈 리치 텅스텐실리사이드막(205)은 300~1000Å의 두께와, 1.0∼2.0 정도의 화학정량을 갖도록 증착한다.The metal rich tungsten silicide film 205 is deposited to have a thickness of 300 to 1000 GPa and a chemical quantity of about 1.0 to 2.0.
절연막(206)은 SiO2, Si3N4또는 이들이 적층된 박막으로 이루어져 후속 식각 공정시 마스크 역할을 한다.The insulating layer 206 may be formed of SiO 2 , Si 3 N 4, or a thin film in which they are stacked to serve as a mask in a subsequent etching process.
그리고, 실리콘기판(201)은 매몰산화막을 갖는 SOI(silicon on insulator) 기판을 사용하거나, 에피택셜층이 설장된 실리콘 에피 웨이퍼를 사용 가능하다. 또한, 실리콘 이외에 화합물 반도체 기판 또는 기타 반도체 물질의 기판을 사용하는 것 역시 가능하다. 게이트절연막(202)은 산화막 또는 산화막과 질화막이 적층된 유전체를 사용하는 것이 가능하다. 도핑된 실리콘막(203)은 다결정실리콘 또는 비정질실리콘 또는 이들을 적층하여 형성할 수 있으며, 그 두께는 500∼1500Å의 두께로 증착한다.The silicon substrate 201 may use a silicon on insulator (SOI) substrate having a buried oxide film or a silicon epi wafer on which an epitaxial layer is mounted. It is also possible to use compound semiconductor substrates or substrates of other semiconductor materials in addition to silicon. As the gate insulating film 202, an oxide film or a dielectric in which an oxide film and a nitride film are stacked can be used. The doped silicon film 203 may be formed by laminating polycrystalline silicon or amorphous silicon or the like, and the thickness of the doped silicon film 203 is 500 to 1500 ∼.
이어서, 도2b를 참조하면, N2또는 NH3분위기, 900∼1100℃에서 열처리하여 두 층의 텅스텐실리사이드막(204, 205)을 하층의 도핑된 실리콘막(203)과 반응시켜 그레인 사이즈(Grain Size)가 증대되어 낮은 비저항을 갖는 저저항 텅스텐실리사이드막(207)을 형성한다. 이때 두 층의 텅스텐실리사이드막(204, 205)은 2.2 정도의 화학정량(Stoichiometry)을 갖는 단일층의 저저항 텅스텐실리사이드막(207)으로 변환된다. 열처리는 퍼니스(furnace)또는 급속열처리(RTP)로 실시 가능하다. 그리고, 상기 열처리후에 실리콘막(203)은 500∼1000Å의 두께가 잔류하며, 저저항 텅스텐실리사이드막(207)은 750∼1500Å의 두께를 갖도록, 상기 열처리와 각 박막의 증착 두께를 조절하는 것이 바람직하다.2B, two layers of tungsten silicide films 204 and 205 are reacted with a lower layer of doped silicon film 203 by heat treatment in an N 2 or NH 3 atmosphere at 900 to 1100 ° C. to obtain grain size (Grain). Size) is increased to form a low resistance tungsten silicide film 207 having a low specific resistance. At this time, the two layers of tungsten silicide layers 204 and 205 are converted into a single layer of low resistance tungsten silicide layer 207 having a stoichiometry of about 2.2. The heat treatment can be carried out by furnace or rapid heat treatment (RTP). After the heat treatment, the silicon film 203 may have a thickness of 500 to 1000 GPa, and the low-resistance tungsten silicide film 207 may have a thickness of 750 to 1500 GPa. Do.
이어서, 도2c를 참조하면, 게이트 마스크를 사용한 포토리소그라피 공정과 식각 공정에 의해 실리콘기판 상에 적층된 박막들을 패터닝한다. 이때 게이트절연막(202)은 과도식각에 의해 약간 또는 완전히 식각될 수 있다.Next, referring to FIG. 2C, the thin films stacked on the silicon substrate are patterned by a photolithography process and an etching process using a gate mask. In this case, the gate insulating layer 202 may be slightly or completely etched by the transient etching.
이어서, 도2d는 통상적인 방법으로 스크린 산화막(208) 형성, 저농도 불순물 이온주입, 게이트 측벽 스페이서절연막(209) 형성, 고농도 이온주입 공정 등을 실시하여 고집적메모리 소자의 MOSFET를 완성한다. 도면에서 불순물 이온주입에 의해 형성되는 소스/드레인 확산은 도시되어 있지 않다.Next, FIG. 2D illustrates the screen oxide film 208 formation, the low concentration impurity ion implantation, the gate sidewall spacer insulating film 209, the high concentration ion implantation process, and the like to complete the MOSFET of the highly integrated memory device. Source / drain diffusion formed by impurity ion implantation is not shown in the figure.
본 실시예에서 CVD 절연막(206) 증착 이전에 열처리를 실시하여 저저항 텅스텐실리사이드막(207)을 형성할 수 있다.In this embodiment, the low-resistance tungsten silicide film 207 may be formed by performing heat treatment before deposition of the CVD insulating film 206.
상술한 바와 같은 본 발명에 따르면, 게이트전극으로서 기존의 텅스텐실리사이드(WSix) 박막을 사용하면서도 비저항이 50μohm·㎝ 정도의 낮은 게이트전극을 형성할 수 있다. 실리콘 리치 텅스텐실리사이드는 하부의 실리콘막과 과도한 반응을 억제할 수 있고 실리콘 리치 텅스텐 실리사이드막은 비정질 상태로 또한 충분히 얇을 경우 메탈 리치 텅스텐실리사이드막과 실리콘막과의 반응을 균일하게 조정할 수 있다. 이 결과 그레인 사이즈(Grain Size)가 크고 이에 의해 비저항이 낮으면서, 그 표면 및 실리콘과의 계면이 러프하지 않고 균일한 양질의 저저항 텅스텐실리사이드막 형성이 가능하다.According to the present invention as described above, while using a conventional tungsten silicide (WSix) thin film as a gate electrode, it is possible to form a gate electrode having a low specific resistance of about 50μohm · cm. The silicon rich tungsten silicide can suppress excessive reaction with the underlying silicon film, and when the silicon rich tungsten silicide film is in an amorphous state and sufficiently thin, the reaction between the metal rich tungsten silicide film and the silicon film can be uniformly adjusted. As a result, the grain size is large and the resistivity is low, thereby making it possible to form a uniform high quality low resistance tungsten silicide film without roughing the surface and the interface with silicon.
본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.
본 발명에 따른 저저항 텅스텐 실리사이드막은 그 표면 및 실리콘과의 계면이 균일하고 매끈한 양질의 박막으로 형성되기 때문에, 256Mb 또는 1Gb급 이상의 DRAM에서 신뢰성 있는 소자를 형성할 수 있으며, 또한 저저항 게이트 형성에 의해 고집적 고속 동작의 메모리 소자 개발을 앞당길 수 있는 탁월한 효과를 갖는다.Since the low-resistance tungsten silicide film according to the present invention is formed of a high quality thin film whose surface and interface with silicon are uniform and smooth, it is possible to form a reliable element in a DRAM of 256Mb or 1Gb or more, and also to form a low-resistance gate. As a result, it has an excellent effect to accelerate the development of highly integrated high-speed memory devices.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100745604B1 (en) * | 2006-07-03 | 2007-08-02 | 삼성전자주식회사 | Semiconductor device and method of forming the same |
| KR100784099B1 (en) | 2006-05-30 | 2007-12-10 | 주식회사 하이닉스반도체 | Method for forming wiring in semiconductor device |
| KR101019700B1 (en) * | 2008-04-28 | 2011-03-07 | 주식회사 하이닉스반도체 | Method of manufacturing semiconductor device |
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1998
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100784099B1 (en) | 2006-05-30 | 2007-12-10 | 주식회사 하이닉스반도체 | Method for forming wiring in semiconductor device |
| KR100745604B1 (en) * | 2006-07-03 | 2007-08-02 | 삼성전자주식회사 | Semiconductor device and method of forming the same |
| KR101019700B1 (en) * | 2008-04-28 | 2011-03-07 | 주식회사 하이닉스반도체 | Method of manufacturing semiconductor device |
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