JP3313432B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having an impurity layer in which carriers are generated by a low-temperature process, and to a method of manufacturing a semiconductor device capable of generating carriers in the impurity layer by a low-temperature process.

[0002]

2. Description of the Related Art With miniaturization and high integration of MOS integrated circuit elements, polycrystalline silicon, gate electrodes, sources,
The area of the connecting portion for connecting the metal wiring to the drain diffusion layer or the like is very small. As a result, an increase in the contact resistance of the wiring is a major problem.

[0003] The contact resistance per unit area is generally determined by the difference in work function between a metal and a semiconductor and the concentration of electrically activated impurities in the semiconductor. To reduce the contact resistance, it is desirable that the difference between the work functions is small and that the impurity concentration in the semiconductor is high. Therefore, as a method for increasing the concentration of electrically activated impurities in a semiconductor, an impurity is ion-implanted into a semiconductor substrate, and then heat treatment is performed at a high temperature to recover crystallinity, thereby forming an activated impurity layer. A method is used.

[0004]

However, in the conventional method in which impurities are ion-implanted into a semiconductor substrate and then subjected to a high-temperature heat treatment in order to cause the impurities to function as donors or acceptors, the impurity concentration of the impurities exceeds the solid solution limit at the heat treatment temperature. The activation concentration could not be increased. For this reason, the values of the resistance of the impurity layer and the contact resistance cannot be sufficiently reduced. In addition, the use of the high-temperature heat treatment causes the impurities to diffuse inward, so that there is a problem that the impurity concentration is reduced and the junction of the diffusion layer is deepened.

Accordingly, it is an object of the present invention to provide a semiconductor device which realizes an impurity layer having a high degree of activation of an impurity diffusion layer and a shallow junction depth, and a method of manufacturing the same.

[0006]

In order to achieve the above object, a semiconductor device of the present invention contains at least a part of boron in the form of a cluster having an icosahedral structure composed of 12 boron atoms and having a carrier concentration of 4%. It is characterized by having an impurity layer of × 10 ²⁰ cm ⁻³ or more in a silicon layer .

Further, in the method of manufacturing a semiconductor device according to the present invention, boron is contained in a silicon layer, 1.3 × 10 ¹⁶ cm ⁻² at an acceleration voltage of 20 Kev, and 1.times.
1.8 × 10 in the case of 5 × 10 ¹⁶ cm ⁻² and 60 Kev
Step of ion-implanting in a high dose region not less than a straight line passing through each point of ¹⁶ cm ^-2 and forming an impurity layer such that at least a part of boron is contained as a form of a cluster having an icosahedral structure of 12 boron atoms. Performing a heat treatment on the impurity layer in a furnace atmosphere at 550 ° C. to 700 ° C. so that at least a part of the generated icosahedral clusters remains; And a step of forming.

[0008]

A cluster composed of 12 boron atoms having an icosahedral structure is formed in an impurity diffusion layer of a semiconductor, and this is used as an acceptor to generate holes. Further, as a method for forming a cluster made of boron, ion implantation containing boron or decomposition of a compound containing boron is used.

In this case, a hole conduction type impurity layer having a high carrier concentration can be formed by a process at a much lower temperature than the conventional heat treatment.

[0010]

Embodiments of the present invention will be described below. FIG. 1 shows an example of an element manufacturing process according to a semiconductor device manufacturing method according to the present invention. First, as shown in FIG. 1A, a CVD (Chemical
A 400 nm silicon dioxide film 2 formed by a vapor deposition method is deposited. Next, the connection holes are patterned as shown in FIG.
A contact hole 3 of 1 μm × 1 μm is formed. Using this silicon dioxide film 2 as a mask, boron ions B ⁺ are implanted into the single crystal silicon substrate 1 at room temperature at an acceleration voltage of 35 keV and a dose of 3 × 10 ¹⁶ cm ⁻² . By this ion implantation, as shown in FIG. 1C, an impurity diffusion layer 4 is formed in the opening portion of the semiconductor substrate 1. After this, a heating furnace,
Heat treatment is performed at 550 ° C. for 1 hour in a dry nitrogen atmosphere. A resistance heating furnace was used as the heating furnace. Thereafter, the surface of the semiconductor substrate is etched by about 100 nm with a mixed solution of hydrofluoric acid, acetic acid and nitric acid, and the impurity diffusion layer 4 is dug down by about 100 nm from the surface as shown in FIG. Next, as shown in FIG. 1E, 800 nm-thick aluminum is deposited on the substrate by, for example, a sputtering method to form a conductive layer 5 of a metal film. The conductive layer 5 is patterned according to the contact holes 3 to form electrodes.

When the contact resistance between the aluminum electrode formed by the method of this embodiment and the impurity diffusion layer was measured, it was 8 × 10 ⁻⁸ Ωcm ² . In order to investigate the effect of reducing the contact resistance by this method, boron is ion-implanted under the same conditions and then heat treatment is performed in a conventional nitrogen atmosphere (heat treatment temperature 900 ° C., heat treatment time 30
(No etching of the impurity diffusion layer 4), the contact resistance was measured to be 4 × 10 ⁻⁷ Ωcm ² . Therefore, in this embodiment, the contact resistance is significantly reduced.

Further, the contact resistance in the case you did not only etching of the semiconductor substrate surface with a mixed solution in this embodiment is 1 × 10 ^-7 Ωcm ^2, although compared with the case of performing etching was high resistance The contact resistance is reduced to 1/4 as compared with the conventional example. In addition, substantially the same contact resistance value can be obtained by measurement using contact holes of different sizes.

In this embodiment, after the boron ion implantation, if the heat treatment is not performed, but the surface of the impurity diffusion layer 4 is formed by etching the surface of the semiconductor substrate with the mixed solution to form a contact, The resistance value is 8 × 10 ⁻⁸ Ωcm ² , and the contact resistance value can be significantly reduced.

Next, the carrier concentration of the contact portion formed in the above embodiment, that is, the concentration distribution of the activated impurity in the depth direction is examined by hole measurement. As shown in FIG. It can be seen that under the conditions, a value of 6 × 10 ²⁰ cm ⁻³ was obtained near the surface. On the other hand, when the conventional heat treatment is performed in a nitrogen atmosphere at 900 ° C. for 30 minutes, only a value of about 1 × 10 ²⁰ cm ⁻³ is obtained as the carrier concentration of the contact portion.

Further, in order to investigate the relationship between the heat treatment and the etching after the ion implantation in detail, the same ion implantation conditions as those used in the above-described embodiment, that is, a single crystal silicon substrate was implanted with boron at an acceleration voltage of 35 keV and a dose of 3 × 10 ¹⁶ cm
After the ion implantation at ⁻² , the carrier concentration distributions before the heat treatment and when the heat treatment was performed at 550 ° C. for various times in a nitrogen atmosphere were examined. The result is shown in FIG.

According to this result, a high carrier concentration of about 6 × 10 ²⁰ cm ⁻³ is obtained at a depth of about 0.1 to 0.15 μm regardless of the presence or absence of the heat treatment and the heat treatment time. . When the heat treatment is not performed near the surface, the carrier concentration is 1 × 10 ¹⁹ cm ⁻³ or less.
By performing the heat treatment for one hour, a carrier concentration of 2 × 10 ²⁰ cm ⁻³ is obtained.

Therefore, in both cases of etching and non-etching, the surface carrier concentration of the impurity diffusion layer before contact formation is 2 × 10 ²⁰ cm ^−3.
With the above, a contact resistance value of 1 × 10 ⁻⁷ Ωcm ² or less, which is required for a further miniaturized semiconductor device in the future, can be realized.

FIG. 4 shows the carrier concentration of a sample in which boron was ion-implanted at a dose of 35 keV into a single crystal silicon substrate immediately after ion implantation and when heat treatment was performed at 550 ° C. for 1 hour in a nitrogen atmosphere. It shows the maximum carrier concentration obtained from the distribution measurement results. As a result, by setting the dose to 1.5 × 10 ¹⁶ cm ⁻² or more,
In both cases immediately after ion implantation and when heat treatment is performed at 550 ° C. for 1 hour in a nitrogen atmosphere, a region having a carrier concentration of 2 × 10 ²⁰ cm ⁻³ or more on the high concentration side across the transition region is formed. And a maximum carrier concentration of 4 ×
It can be seen that 10 ²⁰ cm ^-3 can be easily realized.

At 35 KeV, dose amount 1.5 × 10 ¹⁶ c
When boron is ion-implanted at m ^−2, the peak concentration of boron is 1.5 × 10 ²¹ cm ⁻³ , and in order to obtain a maximum carrier concentration of 2 × 10 ²⁰ cm ⁻³ or more, regardless of the acceleration voltage. 1.5 × 10 ²¹ as the boron peak concentration at the time of ion implantation
It can be said that cm ^-3 or more is necessary. At this time, it was found that 60% or more of the boron was a cluster composed of 12 borons.

Next, in order to examine the relationship between the acceleration voltage of ion implantation and the sheet resistance, the acceleration voltage was 35 keV and 20 kV.
For eV and 60 keV, the sheet resistance immediately after ion implantation was measured. The results are shown in FIG. 5 where the vertical axis represents the sheet resistance value and the horizontal axis represents the boron dose. From this figure, it can be seen that the accelerating voltage is 35 keV and the dose is 1.5 × 10 ¹⁶ cm.
^In order to obtain the same sheet resistance value as 5 × 10 ² Ω / □ obtained at ^-2 , the dose amount is 1.3 × 10 ¹⁶ cm ⁻² at the acceleration voltage of 20 keV, and 1.8 × 10c at the acceleration voltage of 60 keV.
It can be seen that a dose of m ^-2 is required. When the acceleration voltage of boron increases, the spread of the implanted boron in the depth direction increases. As shown in FIG. 6, the result that the dose required to obtain a low-resistance layer increases with an increase in the acceleration voltage indicates that the formation of the low-resistance layer is not caused by the dose of all the ion-implanted boron. , Depending on the concentration of boron present. Although the acceleration voltage is not particularly limited, for example, 5 to 100 KeV that is currently in practical use can be used.

FIG. 7 shows that boron was ion-implanted into a single-crystal silicon substrate at an acceleration voltage of 35 keV and a dose of 3 × 10 ¹⁶ cm ⁻² , and then the heat treatment time was set at 1 hour. 4 shows a carrier concentration distribution in the depth direction of the diffusion layer 4. The carrier concentration at a depth of about 0.1 to 0.15 μm from the surface of the impurity diffusion layer 4 decreases as the heat treatment temperature increases.

As can be seen from FIGS. 3 and 7, the highest carrier concentration is obtained when heat treatment is performed at a temperature of 600 ° C. or lower or no heat treatment is performed. Therefore, the high concentration of carriers on the outermost surface of the semiconductor substrate is realized by etching the substrate surface by about 100 nm after the heat treatment under this condition. As a result, in the present embodiment, the high carrier concentration layer 4 is formed in the contact portion of FIG.
It could be reduced to 10 ^-8 Ωcm ² .

Further, even if the heat treatment temperature is 700 ° C.,
The depth of the diffusion layer does not increase, and the maximum carrier concentration is 2 × 1.
0 ²⁰ cm ^-3 or more, and there is no particular problem in reducing the contact resistance. On the other hand, as shown in FIG.
When the heat treatment temperature is 700 ° C. or higher, the carrier concentration decreases due to inward diffusion and inactivation of boron. However, the value of the carrier concentration at 700 ° C. is superior to that obtained by annealing a low-dose ion-implanted layer of 1 × 10 ¹⁶ cm ⁻² or less at 700 ° C. as conventionally performed.

When silicon ions are implanted and the vicinity of the surface is made amorphous and boron ions are implanted, unlike the above embodiment, high carrier activation immediately after ion implantation and 1 × 10 ¹⁶ No significant change in electrical behavior from the cm ^-2 boundary is observed. Therefore, it is considered that ion implantation in a crystalline state (single crystal or polycrystal) is indispensable for forming a high carrier concentration layer at a low temperature.

As described above, the heat treatment temperature is 700 ° C. or less,
The reason why the remarkable effect that a carrier concentration is high and a shallow diffusion layer is formed when the temperature is preferably set to 600 ° C. or lower is further studied. First, in order to examine the state of boron, the acceleration voltage was fixed at 35 KeV, and the dose of boron was 3 × 10 ¹⁶ on the single crystal silicon substrate.
Ions were implanted at cm ⁻² , 5 × 10 ¹⁶ cm ⁻² and 1 × 10 ¹⁷ cm ⁻² , and the infrared absorption spectra at this time were measured.

FIG. 8 shows the measurement results. This figure displays three absorbance characteristic curve at each dose aligned around wave number 900 cm ^-1 and 740 cm ^-1. From this, it can be seen that the absorbance increases at specific wavenumbers (around 680, 800, and 930 cm ^-1 ) as the boron dose increases. Absorption at these wave numbers corresponds to a cluster of 12 borons having an icosahedral structure. This indicates that a part of the implanted boron is a cluster having an icosahedral structure composed of 12 boron atoms.

[0027] Silicon consisting of 12 boron atoms
As a structure in which clusters having a planar structure exist, the form schematically shown in FIG. 9 can be considered. That is, five silicon atoms forming a tetrahedral structure are removed from the lattice of single crystal silicon, and a cluster having an icosahedral structure is substituted therewith. In this case, the sizes of the five silicon atoms and the boron cluster having an icosahedral structure do not differ by as much as 10%.
A icosahedral cluster consisting of 12 borons has 12 unpaired electron pairs, whereas a single-crystal silicon lattice from which 5 atoms have been removed has 12 unpaired electrons and has no dangling bonds. Substitutions are possible.

In the implantation of boron ions in the spectral absorbance measurement, the silicon substrate was cooled with water to maintain the substrate temperature between room temperature and 80 ° C. Therefore, in order to examine the effect of the substrate temperature, the substrate was cooled with liquid nitrogen and boron ions were implanted. As a result, infrared absorption characteristics indicating the existence of a cluster made of boron could not be obtained. It is considered that the reason is that when the substrate is cooled, the ion-implanted layer becomes amorphous.

With respect to the semiconductor substrate before the heat treatment in which the impurity was implanted while maintaining the substrate temperature between room temperature and 80 ° C., the concentrations of boron and carriers in the depth direction from the substrate surface were measured. This is shown in FIG. As a result of obtaining the relationship between the carrier concentration and the boron dose amount by performing such carrier concentration measurement on samples having various dose amounts, FIG.
The characteristic curve shown in FIG. From these results, it can be seen that, by setting the boron dose amount to 1 × 10 ¹⁶ cm ⁻² , a high carrier concentration can be obtained in the hole conduction type, and the obtained carrier concentration is approximately １ ／ of the boron dose amount. You can see that.

Further, from the spectrum shown in FIG.
When the intensity of the absorption caused by the existence of the cluster consisting of 12 borons having a planar structure was examined with respect to the sheet carrier concentration, the intensity of the infrared absorption and the sheet carrier concentration were found as shown in FIG. They are almost proportional. This indicates that a cluster consisting of 12 borons functions as an acceptor.

From these results, it can be reasonably explained that a cluster consisting of 12 borons acts as a divalent acceptor. By the way, DWBullet, AIP Conf.
Proc., 170, 22 (1991), The electric origin of disorder
According to boron and boron-rich borides, it is shown that an icosahedral cluster composed of 12 borons is a divalent ion, and one cluster is contained in the impurity layer.
The assumption that an icosahedral cluster of two borons is formed and functions as a divalent acceptor is supported.

Next, in order to examine the relationship between the cluster and the heat treatment, boron ions were implanted into the substrate at 35 KeV and at a dose of 1 × 10 ¹⁷ cm ⁻² , without heat treatment, and 550 in a dry nitrogen atmosphere. ℃, 700 ℃ and 900
The concentration of the carrier in the depth direction was measured for the sample that had been subjected to the heat treatment at ° C. As a result, a carrier concentration characteristic curve shown in FIG. 13 was obtained. As the heat treatment temperature increases, the carrier concentration decreases. It is considered that the decrease in the carrier concentration with the increase in the heat treatment temperature is due to the fact that the cluster composed of 12 borons does not work as a bivalent acceptor. An icosahedral cluster of 12 borons, when combined with silicon, has 2 of the 12 borons.
It takes the structure of a compound called B ₁₀ Si _{2 in} which the individual replaces silicon. This compound is electrically neutral and does not function as an acceptor. Therefore, 2 of 12 borons
In order not to reduce the cluster of the 0-hedron structure, it is important that the heat treatment step after the doping is not higher than, for example, 700 ° C. at which a structural change with silicon proceeds. Note that B ₁₁ Si in which one of the 12 borons is replaced with silicon functions as a monovalent acceptor. Therefore, if the heat treatment condition is such that B ₁₁ Si remains, the carrier concentration can be increased. Is valid.

The relationship between a polycrystalline silicon film and a cluster having an icosahedral structure composed of 12 borons will be examined.
On a 300 nm thermal oxide film on a single crystal silicon substrate, L
A 400 nm polycrystalline silicon film was formed by P (low pressure) CVD, and boron was ion-implanted into the film at an acceleration voltage of 35 KeV and a dose of 1 × 10 ¹⁷ cm ⁻² . At this time,
It was confirmed that the state of boron also contained an icosahedral structure cluster consisting of 12 borons. Then, when the relationship between the boron dose amount and the sheet carrier resistance was examined, the result shown in FIG. 14 was obtained.

Comparing the characteristic of FIG. 14 which is a case of a polycrystalline film with the characteristic of FIG. 11 which is a case of a single crystal film, in the case of a polycrystalline film, the carrier concentration obtained with the same dose is lower. You can see that. This is because, although a cluster having an icosahedral structure composed of 12 borons has holes as acceptors, carriers generated by the presence of crystal grain boundaries in polycrystalline silicon are electrically inactivated. It is thought to be.

By utilizing the fact that a cluster having an icosahedral structure composed of 12 boron atoms can be generated in this polycrystalline film, low-resistance polysilicon wiring can be formed at a low temperature. For example, as shown in FIG. 15 of the second embodiment, the surface of a semiconductor device in which a silicon dioxide film 22 and a diffusion layer 23 are formed on the surface of single crystal silicon 21 (FIG. 15A) A non-doped (high resistance) polycrystalline silicon film 24 containing no impurities
nm (FIG. 3B). On top of this, a photoresist 25 is applied and patterned so that only the region where the resistance is desired to be reduced is exposed (FIG. 3C). This substrate is doped with boron at an acceleration voltage of 35 KeV and a dose of 1 × 10 ¹⁷ cm ^−2.
Ion implantation. As a result, only the region 26 into which boron ions are implanted becomes a low-resistance polycrystalline silicon film containing boron at a high concentration. In addition, polycrystalline silicon wiring can be performed by a low-temperature process in which the maximum temperature in the process does not exceed the deposition temperature of polycrystalline silicon. The specific resistance of polycrystalline silicon is 10 ^-1 Ωcm and 10 ⁵ Ωcm in the region where boron ion implantation is performed and the region where boron ion implantation is not performed.
And the values of the specific resistance are greatly different. Therefore, peeling of the non-ion-implanted region after boron ion implantation may or may not be performed depending on the element structure or the like. FIG. 3E shows an example in which patterning is performed so that only the low-resistance polycrystalline silicon film 26 remains.

Next, a case where a cluster having an icosahedral structure composed of 12 boron atoms is generated by using a mixed gas will be described. Using a mixed gas of disilane and diborane as a raw material, a silicon thin film containing boron is deposited by a LPCVD method on a silicon substrate from which a natural oxide film or the like on the substrate surface has been sufficiently removed. The deposition conditions at this time were a disilane flow rate of 100 SCCM and a diborane flow rate of 20 SCCM.
The pressure was 100 mTorr and the temperature was 570 ° C.

FIG. 16 shows the relationship between the boron concentration and the carrier concentration in the deposited film at this time. As shown by the solid line in the figure, when the boron concentration is low, the carrier concentration and the boron concentration match, but when the boron concentration is high,
The carrier concentration is lower than the boron concentration, which is about 1/6 of the boron concentration. This result can be explained by assuming that, as in the above-described example, boron forms a cluster of 12 and functions as a bivalent acceptor.
Also in this case, examination of infrared absorption confirmed the existence of a cluster consisting of 12 boron atoms.

When the deposition temperature was 540 ° C.,
The relationship between the boron concentration and the carrier concentration was as shown by the dotted line in FIG. As compared with the case where the deposition temperature is set to 570 ° C., the carrier concentration is extremely low in the region where the boron concentration is high. The difference is that when the deposition temperature is high, diborane is easily decomposed and a cluster of 12 borons is formed, whereas when the deposition temperature is low, diborane is not decomposed in the gas phase, and It is considered that the movement of atoms on the surface of the substrate hardly occurs, so that boron clusters are not formed.

In the first and second embodiments described above, boron is used as the impurity species for ion implantation. However, other ion species containing boron, for example, BF ⁺ , B
Even when F ₂ ⁺ or the like was used, the same effect was obtained.

In the first embodiment, the ion implantation and the heat treatment are performed after the silicon dioxide film is deposited, but the order may be reversed. Further, another etching method such as dry etching may be used for etching the silicon surface. The silicon dioxide film may be another thin film such as a silicon nitride film.

The metal used as the electrode is not limited to aluminum, but may be other metal such as copper, tungsten, titanium or the like, or a compound having conductivity. In particular, when a compound such as silicide containing silicon is used as an electrode or a base of an electrode, etching of the surface of a semiconductor substrate is performed by positioning an interface in a region where impurities are activated by a reaction with silicon during compound formation. Can be replaced with For example, after boron ion implantation, Ni is sputtered and heat-treated at 550 ° C. to alloy with the substrate Si.
What is necessary is just to form a Ni silicide layer. Also, the present invention
The present invention is also applicable to semiconductor / semiconductor contacts.

The method of forming a shallow high-concentration activated impurity layer shown in the first and second embodiments can be applied to the formation of a diffusion layer in a semiconductor manufacturing apparatus.

FIG. 17 shows a third embodiment of the present invention.
An example in which the present invention is applied to a manufacturing process of a MOS transistor having an LDD (Lightly Doped Drain) structure is shown. 17, portions corresponding to those in FIG. 1 are denoted by the same reference numerals.

As shown in FIG. 17A, for example, an n-type silicon substrate 1 having a plane orientation (100) and a specific resistance of 4 to 6 Ωcm is used, and an element isolation insulating film of about 0.6 μm is formed by a normal selective oxidation method. 2a is formed. Next, a gate oxide film 11 of 10 nm is formed by a thermal oxidation method. On this, a 100 nm impurity-doped polycrystalline silicon film 12 as a gate and a 300 nm tungsten silicide film 13 as a wiring layer are sequentially formed. In addition, LPC
A 150 nm silicon oxide film 14 is formed by the VD method. Thereafter, these laminated films are etched by a reactive ion etching method to pattern the gate electrode.

Then, boron ions are ion-implanted using the formed gate electrode as a mask to form a low-concentration p-type impurity layer 15 in the source and drain regions. The ion implantation conditions are, for example, an acceleration voltage of 10 keV and a dose of 5 × 10 5
¹³ cm ^-2 . The heat treatment after the ion implantation is performed at 700 ° C.
30 minutes.

Thereafter, as shown in FIG. 17B, a silicon oxide film 16 having a thickness of about 100 nm
To form This sidewall oxide film 16 has a thickness of 150 nm over the entire surface.
Is obtained by depositing a silicon oxide film by CVD and then etching the entire surface by anisotropic dry etching.

Next, as shown in FIG. 17C, boron ions were implanted into the p-type impurity layers 15 in the source and drain regions where the substrate was exposed, thereby forming a high concentration diffusion layer 4. The ion implantation conditions are, for example, an acceleration voltage of 35 keV,
The dose is 2 × 10 ¹⁶ cm ⁻² . No heat treatment was performed after ion implantation.

Thereafter, a 300 nm silicon oxide film 17 is deposited on the entire surface by CVD. Further, FIG.
As shown in FIG.
Is opened by anisotropic dry etching. The silicon surface exposed by the opening is dry-etched to 100
After etching, for example, silicon and copper are each added to a thickness of 0.1 nm.
800 nm of aluminum 5 containing 5% each was deposited (FIG. 8 (c) shows up to this step). After patterning the aluminum film 5 so as to be used as an electrode, a heat treatment was performed at 450 ° C. for 15 minutes in a nitrogen atmosphere containing 10% of hydrogen.

The etching of the silicon surface is performed in the first step.
May be performed by wet etching as in the embodiment.

When the OFF resistance and the contact resistance of the channel of this MOS transistor were measured, the device having a channel length of 0.8 μm, a channel width of 1.1 μm, and a contact diameter of 0.8 μm (one side) was 2,000.
Ω and 2Ω.

On the other hand, a source having an exposed substrate,
Boron ions are implanted into the drain region 15 by, for example, an ordinary acceleration voltage of 35 keV and a dose of 5 × 10 5.
And ¹⁵ cm ^-2, The heat treatment after the ion implantation is 850
When the temperature is 30 ° C. and 30 minutes, the OFF resistance and the contact resistance of the channel are 20
00Ω and 30Ω. Thus, according to the present invention,
The contact resistance value of the semiconductor element can be greatly reduced. The difference between the OFF resistance and the contact resistance of the channel becomes smaller as the element size is reduced. Approximately, when the element size is reduced to 1 / k, the OFF resistance of the channel does not change, whereas the contact resistance becomes k ² times. Therefore, for an element smaller than the element shown in this embodiment, the reduction of the contact resistance value by the present method is a more effective method. Further, since the process of the present invention is a low temperature process, it is also suitable for a so-called multilayer wiring board.

In this embodiment, the high-concentration impurity layer is formed directly on the surface of the single-crystal silicon substrate. However, a single-crystal silicon layer is further formed on the single-crystal silicon substrate by a CVD method or the like, and this is replaced with a new substrate. The present invention can be applied to such a case.

The present invention can be applied not only to the contact portion but also to a portion where a shallow, highly active junction is required.

[0054]

As described above, the semiconductor device of the present invention has an impurity layer contained in the form of an icosahedral structure composed of 12 boron atoms, so that a shallow and highly active diffusion layer is formed. It becomes possible. The method of manufacturing a semiconductor device according to the present invention includes a step of performing high-concentration doping on an impurity layer of a semiconductor substrate to generate an icosahedral cluster including 12 boron in the impurity layer. Thus, a shallow, highly active diffusion layer can be formed. In particular,
The performance of the next-generation LSI can be significantly improved.

[Brief description of the drawings]

FIG. 1 is a process chart showing an embodiment of the present invention.

FIG. 2 is a graph showing a distribution of a carrier concentration in a contact portion in a depth direction.

FIG. 3 is a graph showing carrier profiles before and after heat treatment at 550 ° C. for various times in a nitrogen atmosphere.

FIG. 4 is a graph showing the maximum carrier concentration obtained from the carrier concentration measurement results of the samples implanted with various doses immediately after ion implantation and when heat treatment was performed at 550 ° C. for 1 hour in a nitrogen atmosphere. .

FIG. 5 is a graph showing the relationship between the boron dose and the sheet resistance depending on the acceleration voltage of various ion implantations.

FIG. 6 is a graph showing a region where a low resistance layer is formed.

FIG. 7 is a graph showing the distribution of the carrier concentration in the depth direction when heat treatment is performed at various temperatures.

FIG. 8 is a graph showing a measurement result of an infrared absorption spectrum.

FIG. 9 shows a silicon crystal consisting of 12 boron atoms.
FIG. 3 is a schematic diagram showing a crystal structure in the case where a cluster having a planar structure exists.

FIG. 10 is a graph showing the concentration of boron and carriers injected into a substrate in the depth direction.

FIG. 11 is a graph showing a relationship between a sheet carrier concentration and a boron dose amount.

FIG. 12 is a graph showing the relationship between the intensity of absorption and the sheet carrier concentration caused by the presence of a cluster consisting of 12 boron atoms.

FIG. 13 is a graph showing the carrier concentration in the depth direction when heat treatment is performed at 550 ° C. to 900 ° C. for 1 hour in a nitrogen atmosphere.

FIG. 14 is a graph showing a relationship between a carrier concentration and a boron concentration in a polycrystalline silicon film.

FIG. 15 is a process chart showing an example in which the present invention is applied to low-temperature formation of low-resistance polycrystalline silicon wiring.

FIG. 16 is a graph showing a relationship between a carrier concentration and a boron concentration in a deposited film using a boron mixed gas.

FIG. 17 is a view showing a manufacturing process of an example in which the present invention is applied to the manufacture of a MOS transistor having an LDD structure.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Single crystal silicon 2 Silicon dioxide film 3 Contact hole 4 High impurity concentration region (high carrier concentration region) 5 Electrode (conductive layer) 11 Gate oxide film 12 Gate 13 Tungsten silicide film 14, 16, 17 Silicon oxide film 15 Low Concentration p-type impurity layer 21 Single-crystal silicon 22 Silicon dioxide film 23 Diffusion layer 24 Non-doped (high resistance) polycrystalline silicon 25 Photoresist 26 Low-resistance polycrystalline silicon substrate containing boron in high concentration

──────────────────────────────────────────────────続 き Continuation of front page (72) Inventor Masahiko Yoshiki 1 Komukai Toshiba-cho, Saiyuki-ku, Kawasaki-shi, Kanagawa Prefecture Toshiba R & D Center (56) References JP-A-55-165679 (JP, A) Appl. Phys. Lett. Vol., October 15, 1980. 37, No. 8, P727-729 (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 29/167 H01L 21/265 H01L 21/28 H01L 29/40 H01L 29/78 H01L 21/336

Claims (7)

(57) [Claims] An impurity layer containing at least a part of boron in the form of an icosahedral structure cluster of 12 borons and having a carrier concentration of 4 × 10 ²⁰ cm ⁻³ or more.
A semiconductor device included in a silicon layer . 2. The semiconductor device according to claim 1, wherein said silicon layer is a silicon substrate. 3. The semiconductor device according to claim 1, wherein said silicon layer is a polycrystalline silicon layer formed on a silicon substrate.
3. The semiconductor device according to claim 1. 4. The method according to claim 1, wherein the silicon layer contains boron and the accelerating voltage is 20.
1.3 × 10 ¹⁶ cm ^{−2 for} Kev, 1.5 × 10 ¹⁶ cm ⁻² for 35 Kev, 1.
Ion implantation is performed at a high dose region equal to or greater than a straight line passing through each point of 8 × 10 ¹⁶ cm ⁻² , and an impurity layer is formed so that at least a part of boron is contained as a form of a cluster having an icosahedral structure including 12 boron atoms. Forming, at 550 ° C. to 700 ° C., such that at least a part of the generated icosahedral cluster remains in the impurity layer.
A method of performing a heat treatment in an atmosphere in a furnace, and a step of forming a functional portion using the impurity layer. 5. The method according to claim 4, wherein the silicon layer is a silicon substrate, and the functional portion is a diffusion layer formed on a surface of the silicon substrate. 6. The method according to claim 5 , wherein a desired conductive layer is formed by etching the surface of the silicon substrate after ion implantation. 7. The method of manufacturing a semiconductor device according to claim 4, wherein said silicon layer is a polycrystalline silicon layer, and said functional portion is a wiring layer formed on said polycrystalline silicon layer. .