JP3023189B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[Object of the Invention]

[0002]

The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device having a shallow impurity layer.

[0003]

2. Description of the Related Art In recent years, as semiconductor devices have become more highly integrated, circuit miniaturization has been progressing, and miniaturization of basic elements such as field effect transistors (FETs) has become necessary. For example, in FET, as the gate is shortened,
It is also required that the source / drain region be formed shallow. In order to form the source / drain regions shallowly, a low-acceleration ion implantation method has been widely used.

By using this method, 0.1 μm
A shallow source / drain region can be formed,
A fine and high performance FET is realized. However, an impurity layer formed only by such an ion implantation method has a high resistance and a sheet resistance of 100Ω or more per unit area. FE
To increase the speed of T, it is necessary to reduce the sheet resistance of the impurity layer and make it easier for the drain current to flow. In order to reduce the sheet resistance of the impurity layer, a method of metallizing a part of the impurity layer has been proposed, and one of them is a method called salicide (Self Aligned Silicide).

[0005] This method will be described with reference to FIGS.

First, a field oxide film 2 is formed on an n-type silicon substrate 1, and a gate electrode 4 made of a polycrystalline silicon layer is formed in a separated element region via a gate insulating film 3 made of a silicon oxide film. After being formed and patterned by photolithography, a silicon oxide film as a side wall insulating film 5 is formed on the side wall of this gate by a side wall leaving method. The thickness of the sidewall insulating film is 15
It is set to 0 nm. Then, the natural oxide film is removed by high-temperature treatment of the substrate surface.
Is deposited (FIG. 15).

Then, at 800 ° C. in an inert gas atmosphere.
Lamp annealing is performed for 0 second to form a CoSi ₂ layer 7 at the interface with the silicon substrate 1 (FIG. 16).

[0008] Thereafter, as shown in FIG.
After the film 6 is removed with a hydrogen peroxide solution, boron as an impurity element is implanted into the CoSi ₂ layer 7 by ion implantation and heat treatment is performed, so that the shallow p + impurity diffusion layer 8 is self-aligned with respect to the gate electrode 4. Is formed, and further, an interlayer insulating film 9 is formed, a contact hole for exposing the surface of the diffusion layer 8 is formed in the interlayer insulating film 9, and then a wiring layer 10 is formed.

According to this method, a silicide having a thickness of about 150 nm can be formed, and the sheet resistance can be reduced to 1 to 3 Ω per unit area.

However, recent research has revealed that this method also has the following problems.

For example, to form a device having a gate length of 0.3 μm or less, the thickness of the diffusion layer needs to be 0.1 μm or less. However, since boron used for forming the p + diffusion layer has a larger diffusion coefficient than arsenic used for forming the n + diffusion layer, satisfying the above condition is particularly important for forming the p + diffusion layer. .

In order to form a shallow diffusion layer using boron as described above, it is necessary to perform a heat treatment at a low temperature of about 850 ° C., but as a result, the solid solubility of boron in the silicon substrate decreases. Therefore, the carrier concentration at the interface between silicide and silicon has a low value of 5 × 10 ¹⁹ cm ⁻³ or less.
As a result, the contact resistivity with respect to the p @ + diffusion layer is 1.times.1.
The value is as extremely large as 0 ^-4 Ωcm ^-2 or more, and there is a problem that good electrical connection cannot be made between the substrate diffusion layer and the upper metal wiring layer.

In order to reduce the contact resistance with respect to the p + silicon layer, it is effective to select a material having a low Schottky barrier height with respect to p − silicon. For example, a similar structure was formed using nickel instead of cobalt used in the above-described example, and the electrical characteristics were evaluated.
+ The contact resistivity to the diffusion layer is 1 × 10 ^-6 Ωcm ^-2
It became clear that it could be lowered. However,
A thin silicide film having a thickness of 100 nm or less formed by using nickel causes agglomeration to occur at a temperature of 850 ° C. or more, and is likely to be uneven due to facet formation at a silicide / silicon interface, which causes a reduction in device reliability. This is a new problem.

[0014]

As described above, in the conventional semiconductor device, when a shallow impurity layer of 0.1 μm or less is formed, the contact resistance is high because the impurity concentration at the interface between the metal compound and the semiconductor substrate is low. It has been difficult to make good electrical connection between the substrate diffusion layer and the upper metal wiring layer.

Further, when a material having a low Schottky barrier height is used to reduce the contact resistance, the flatness of the interface is deteriorated due to a cohesion phenomenon or the like, so that the reliability of the device is reduced.

The present invention has been made in view of the above circumstances, and has as its object to provide a method for forming a highly reliable semiconductor device having a shallow diffusion layer.

[Structure of the Invention]

[0018]

SUMMARY OF THE INVENTION Therefore, the first aspect of the present invention has been described.
In a method for manufacturing a semiconductor device including a step of forming a contact with a conductive type region formed on a semiconductor substrate, a composition ratio of a metal element to a substrate constituent element is 1 or more on a contact region on the substrate surface. A step of forming a certain first metal compound layer, a step of subsequently generating a nucleus of a second metal compound in which the composition ratio of the metal element to the constituent elements of the substrate is smaller than 1, and a step of subsequently performing a heat treatment on the first metal compound Changing the compound layer into a second metal compound layer.

According to a second aspect of the present invention, a first metal compound layer having a composition ratio of a metal element to a substrate constituent element of 1 or more is formed on a contact region on a substrate surface, and thereafter, the first metal compound layer is formed. An amorphous film containing a constituent element of the semiconductor substrate is formed on the layer, and then the first metal compound layer is formed by heat treatment using a second metal compound having a composition ratio of the metal element to the constituent element of the semiconductor substrate of less than 1 A heat treatment for changing the layer into a layer is performed.

[0020]

As described above, according to the method of the present invention, it is possible to generate nuclei of the second metal compound at a high density near the surface of the first metal compound layer before or after the formation of the conductive region. Therefore, unevenness of the nucleation does not cause unevenness at the interface between the first metal compound and the semiconductor substrate. The interface between the substrate and the metal compound layer is kept flat, and ohmic contact with the surface is improved. It is possible to keep good and to form a shallow conductivity type region.

Preferably, the thickness of the first metal compound is 1
The ion implantation is performed to a depth of not more than / 2.

By slightly mixing the surface of the first metal compound layer by ion implantation, the influence of the crystal grain boundaries is reduced, and as a result, the growth of the second metal compound layer is evenly distributed in the first metal compound layer. It is possible to proceed,
It is possible to suppress the generation of the unevenness of the interface due to the heterogeneous reaction, which is inevitable in the related art. At this time, it has been clarified that if the ion implantation depth is too large, ion implantation damage occurs and deteriorates bonding characteristics. Therefore, as a result of various studies, the best result can be obtained when the acceleration voltage is selected so that the ion implantation depth is about 1/2 or less of the first metal compound layer.

Preferably, nuclei of the second metal compound are generated by vapor phase growth of silicon. By performing vapor phase growth of silicon, the surface of the first metal compound (silicide) film changes to a uniform silicon-rich second metal compound film, which serves as a uniform nucleus to form the second metal compound film. According to a second aspect of the present invention, which is considered to grow uniformly, an amorphous film containing a constituent element of a semiconductor substrate is formed on the surface of the first metal compound layer, and then the first metal compound layer is formed by heat treatment. Is heat-treated to change the composition ratio of the metal element to the constituent element of the semiconductor substrate into a layer of the second metal compound smaller than 1. Therefore, it is possible to reduce the influence of crystal grain boundaries and perform uniform growth. It becomes possible.

[0024]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIGS. 1 to 5 are sectional views showing the steps of manufacturing a semiconductor device according to the first embodiment of the present invention.

First, as shown in FIG. 1, a field oxide film 12 having a thickness of 800 nm is formed on an n-type silicon substrate 11 having (100) as a main surface, and a gate insulating film and a gate insulating film are formed in an isolated element region. A 150 nm-thick highly doped polycrystalline silicon layer 14 a and a 150 nm-thick tungsten silicide layer 14 b are sequentially formed via a 10 nm-thick silicon oxide film 13. Further, a silicon oxide film 14c is formed on this upper layer by a CVD method, and is patterned using a resist pattern formed by a photolithography method as a mask. Thereby, the gate insulating film 13, the polycrystalline silicon film 14a and the tungsten silicide layer 14
The gate electrode consisting of b is formed. Next, a silicon oxide film 15 as a side wall insulating film is formed on the side wall of the gate. Here, after depositing a silicon oxide film over the entire surface with a thickness of 150 nm by the CVD method, an insulating film is left on the side wall by anisotropic etching.

Next, Ga ions are accelerated at an acceleration voltage of 200 ke.
V, ions were implanted into the substrate under the conditions of an implantation dose of 1 × 10 ¹⁵ cm ⁻² to make the surface of the silicon substrate 11 preamorphous, and an acceleration voltage of 25 keV and an implantation dose of 5 × 1
BF ₂ is implanted under the condition of 0 ¹⁵ cm ⁻² and heat treatment is performed at 1050 ° C. for 20 seconds to form a shallow p + diffusion layer 18 having a depth of 0.1 μm. Thereafter, the substrate is introduced into HF vapor to remove a natural oxide film growing on the surface of the p @ + diffusion layer.
After reducing the pressure to an ultra-high vacuum of ^-8 Torr or less, the substrate is
And heat for 10 minutes. By this heat treatment, the p + diffusion layer 18 is formed.
Carbon impurities remaining on the surface are removed to form a clean silicon surface. After the substrate temperature is returned to room temperature, a nickel layer 20 is formed to a thickness of about 30 nm by sputtering or electron beam evaporation (FIG. 2).

Subsequently, as shown in FIG. 3, while the substrate is kept in a vacuum, an annealing treatment is performed at about 500 ° C. for 15 minutes, so that only the exposed portion of the p + diffusion layer 18 has a NiSi crystal film (first film). (A metal compound layer 21). At this time, the nickel layer 20 on the field oxide film 12, on the sidewall insulating film 15 on the gate side wall, and on the silicon oxide film 14c still remains.

Thereafter, the substrate was returned to room temperature, taken out into the air, and subsequently etched in a solution of HCl: H ₂ O ₂ = 1: 1 to remain unreacted as shown in FIG. The nickel layer 20 is removed. As a result,
NiSi crystal film 21 crystallized only on p + diffusion layer 18
Are formed in a self-aligned manner.

After that, silicon ions are accelerated at an acceleration voltage of 20 ke.
V ions are implanted into the substrate under the conditions of an implantation dose of 1 × 10 ¹⁵ cm ⁻² . At this time, the implantation depth of silicon ions was about 1/2 of the NiSi layer 21, and did not reach the interface between NiSi and the silicon substrate. Thereafter, the substrate is annealed in argon at 500 ° C. for 30 minutes. As a result, the NiSi film 21 is completely changed to a NiSi ₂ film (second metal compound layer) 22.

Further, a 0.7 μm-thick silicon oxide film 19 is deposited as an interlayer insulating film by the CVD method, and further, a contact hole is formed in the silicon oxide film 19 so that the source and drain surfaces are exposed. Then, a titanium nitride layer 24 as a barrier metal layer and an aluminum silicon alloy layer 25 are laminated in this order, and the laminated film is patterned to form an electrode wiring as shown in FIG. 5, thereby completing a field effect transistor. At this time, the NiSi ₂ crystal film 2
No. ₂ has a complete epitaxial orientation with respect to the (100) silicon substrate, and it has been confirmed that the interface between the NiSi ₂ crystal film 22 and the silicon substrate 11 is steep and flat at the atomic level. The amount of erosion of the substrate at the interface was estimated to be 1 nm or less. When the contact resistance between the NiSi ₂ crystal film 22 and the p + diffusion layer 18 of the field effect transistor thus obtained was measured,
When the contact surface was a square having a side of 1 μm, the resistance was 23Ω. Also, the junction leak was almost the same as that of the reference without forming silicide.

The mechanism by which a good silicide film can be formed in a self-aligned manner by this method is considered as follows.

First, a detailed study of the growth process of NiSi ₂ revealed the following phenomena. By heat-treating the NiSi film, first the micronuclei of NiSi ₂ become NiS
Occurs during i. When heat treatment is further applied, the NiSi ₂ nuclei grow rapidly in a network along the crystal grain boundaries of NiSi, and thereafter the entire NiSi becomes NiSi _2, and the density of NiSi ₂ nuclei generated in NiSi is 100%.
It was also evident that the value was extremely coarse, about 1 to ² per μm ² . As a result of further continued studies, uneven growth of the NiSi ₂ in a NiSi became clear that would cause large irregularities on NiSi ₂ / Si interface. It goes without saying that such interface irregularities cause junction leakage.

In order to solve this problem, the present invention first forms a NiSi film in a self-aligned manner,
Is performed. And as a result of ion implantation, NiSi
High density NiSi ₂ nuclei can be formed near the surface of the film.

Further, by slightly mixing NiSi by ion implantation, the influence of crystal grain boundaries is reduced, and as a result, the growth of NiSi ₂ can proceed uniformly in the NiSi film, which is inevitable in the prior art. As a result, it was possible to suppress the occurrence of interface irregularities due to the heterogeneous reaction. At this time, it was found that if the implantation depth of Si ions was too large, ion implantation damage would occur in the diffusion layer below NiSi, and the bonding characteristics would be degraded. Therefore, as a result of various studies, it has been clarified that the best results can be obtained when the acceleration voltage is selected so that the ion implantation depth is about 1/2 or less of the NiSi film.

According to the prior art, the formation of NiSi ₂ requires a high-temperature heat treatment of about 800 ° C. or higher. However, according to the present invention, the NiSi ₂ nucleus is positively used by ion implantation in the NiSi film. Therefore, a good NiSi ₂ epitaxial growth film can be formed at a low temperature of about 500 ° C. As a result, a shallow impurity distribution in the diffusion layer is favorably maintained.

As described above, according to the method of the present invention, salicide having a steep and flat interface at an atomic level without substrate erosion can be easily formed at a low temperature.

Next, a second embodiment of the present invention will be described.

In this example, instead of ion implantation, SiH ₄
By performing annealing, a uniform Ni film is formed on the NiSi film surface.
Form Si ₂ nuclei.

First, a gate insulating film, a gate electrode, a gate sidewall insulating film, etc. are formed on the surface of an n-type silicon substrate, and then a p + diffusion layer 18 is formed, and crystallization is performed only on the p + diffusion layer 18. After the formed NiSi crystal film 21 is formed in a self-aligned manner, the unreacted Ni film is removed (FIG. 6). The steps so far are exactly the same as in the first embodiment.

Next, the substrate is washed with a 2% HF solution, spin-dried, and immediately introduced into a reduced-pressure vapor deposition apparatus.
Next, a mixed gas of N ₂ and SiH ₄ was introduced, and 0.1 Torr
Annealing was performed at 550 ° C. for 60 minutes under the following pressure.
As a result of analyzing this film using RBS, it was found that the surface of the NiSi film was changed to be silicon-rich (FIG. 7).

Thereafter, the introduction of the mixed gas of N ₂ and SiH ₄ was stopped, and N ₂ gas was introduced instead.
After annealing at 30 ° C. for 30 minutes, the NiSi crystal film 2
1 was completely changed to NiSi ₂ 22. And Example 1
Similarly, a 0.7 μm-thick silicon oxide film 19 is deposited as an interlayer insulating film by the CVD method, and a contact hole is formed in the silicon oxide film 19 so that the source / drain surface is exposed. Then, a titanium nitride layer 24 as a barrier metal layer and an aluminum silicon alloy layer 25 are laminated in this order, and the laminated film is patterned to form an electrode wiring as shown in FIG. 5, thereby completing a field effect transistor. When the contact resistance between the NiSi ₂ crystal film 22 of the field effect transistor thus obtained and the p + diffusion layer 18 was measured, good results were obtained as in Example 1. Also, the junction leak was almost the same as that of the reference without forming silicide.

In this example, after forming a NiSi film, NiH is obtained by performing SiH ₄ annealing instead of ion implantation.
Si film surface is changed to a uniform NiSi ₂ film, which becomes a uniform nucleation is believed to occur is uniform growth of the NiSi ₂ film.

Next, a third embodiment of the present invention will be described.

First, in the same manner as in Example 1, (100)
An 800 nm-thick field oxide film 12 is formed on an n-type silicon substrate 11 having a main surface of 10 nm, and a 10 nm-thick silicon oxide film 1 serving as a gate insulating film is formed in an isolated element region.
3, a polycrystalline silicon layer 14 a with a high concentration of 150 nm and a tungsten silicide layer 14 b with a thickness of 150 nm are sequentially formed. Thereafter, a silicon oxide film 14c is further formed on the upper layer by a CVD method, and is patterned using a resist pattern formed by a photolithography method as a mask. As a result, a gate electrode composed of gate insulating film 13, polycrystalline silicon film 14a and tungsten silicide layer 14b is formed.
Next, a silicon oxide film 15 as a side wall insulating film is formed on the side wall of the gate. Here, after depositing a silicon oxide film over the entire surface with a thickness of 150 nm by the CVD method, an insulating film is left on the side wall by anisotropic etching. Then, after the nickel layer 20 is formed by vapor deposition so as to have a thickness of about 30 nm, annealing is performed at about 500 ° C. for 15 minutes, so that the NiSi crystal film 21 is grown only on the exposed portion of the substrate. At this time, on the field oxide film 12, on the side wall insulating film 15 of the gate side wall, and on the silicon oxide film 14
The nickel layer 20 on c still remains.

Thereafter, the substrate was returned to room temperature, taken out into the atmosphere, and subsequently etched in a solution of HCl: H ₂ O ₂ = 1: 1 to remain unreacted as shown in FIG. The nickel layer 20 is removed. As a result,
A crystallized NiSi crystal film 21 is formed in a self-aligned manner.

Thereafter, BF ₂ ions are implanted into the substrate under the conditions of an acceleration voltage of 40 keV and an implantation dose of 1 × 10 ¹⁶ cm ⁻² . At this time, the implantation depth of silicon ions is
It should be near the interface between the Si layer and the silicon substrate.
Thereafter, the substrate was annealed in a nitrogen atmosphere at 500 ° C. for 20 hours. As a result, a shallow p + diffusion layer 18 having a depth of 0.08 μm was formed below the NiSi film 21. At this time, the specific resistance of the NiSi film 21 is almost the same as before annealing, and no NiSi ₂ film is formed (FIG. 10).

Next, the substrate is introduced into a low pressure vapor phase epitaxy apparatus,
After the substrate surface is cleaned by introducing F ₂ plasma under a pressure of 0.1 Torr or less, the substrate is cleaned in a CO gas atmosphere at 400 ° C.
Anneal at 10 ° C. for 10 minutes to remove F atoms on the substrate surface. Thereafter, in a mixed gas atmosphere of He and SiH ₄ ,
About 300 nm of amorphous silicon 20 was deposited. The substrate temperature at this time is 400 to 500 ° C. (FIG. 11).

Next, as a result of annealing at 750 ° C. for 15 minutes in a nitrogen atmosphere, the NiSi film 21 is completely NiSi ₂
It turned into a film 22 (FIG. 12).

Further, as a result of detailed examination of the formed NiSi ₂ film 22, the position of the NiSi ₂ / Si interface coincides with the position of the NiSi / Si interface formed first.
Si mainly reacts with amorphous silicon to form NiSi ₂
It became clear that was formed. This is because amorphous silicon is easier to diffuse nickel than single crystal silicon.

Thereafter, as shown in FIG. 13, a mixed gas plasma of CF ₄ and oxygen O ₂ was introduced to remove unreacted amorphous silicon. At this time, the formed NiSi
_{The second} film 22 was not etched at all, and NiSi ₂ was completely formed in a self-aligned manner. In addition, all the steps after the introduction of the substrate into the low pressure vapor phase epitaxy apparatus could be continuously performed.

Thereafter, as in the first and second embodiments, a 0.7 μm-thick silicon oxide film 19 is deposited as an interlayer insulating film, and the silicon oxide film 19 is exposed so that the source and drain surfaces are exposed. Then, a contact hole is formed.
Further, a titanium nitride layer 2 as a barrier metal layer
4 and an aluminum silicon alloy layer 25 are laminated in this order, and the laminated film is patterned to form an electrode wiring, thereby completing a field effect transistor (FIG. 14).

In this method, the NiSi film mainly reacts with the amorphous silicon deposited on the upper layer to form NiSi ₂ , so that it is possible to suppress the amount of erosion of the diffusion layer, and to form a shallow junction of 0.1 μm or less. High reliability can be ensured.

It was confirmed that the NiSi ₂ film thus formed was also favorably grown epitaxially on the silicon substrate, and the NiSi ₂ / silicon interface was flat.

Further, as a step of removing unreacted amorphous silicon, annealing is performed in an oxidizing atmosphere to convert all the unreacted amorphous silicon into a silicon oxide film, and then the silicon oxide portion is etched using an NH ₄ solution or the like. A removing step may be used.

The present invention is not limited to the embodiment described above. For example, in the above embodiment, the case where salicide is formed on the entire surface of the diffusion layer has been described. However, other than this, silicide that grows through a nucleation process such as cobalt silicide or rhodium silicide can be similarly performed.

In the case of forming nickel silicide, a NiSi film is formed as the first metal compound layer. However, a Ni ₂ Si or Ni ₃ Si film may be formed.

Further, when rhodium silicide is formed, Rh ₄ Si ₅ , Rh is used as the second metal compound layer.
_{A 3} Si ₄ film may be formed.

In addition, in the above embodiment, the vapor deposition method is used for forming the metal compound layer. However, the present invention is not limited to the vapor deposition method, and an ion beam deposition method, a sputtering method, or the like may be used.

[0060]

As described above, according to the present invention, the interface between the substrate and the metal compound layer is kept flat, the ohmic contact at the interface is kept good, and the shallow conductive region is formed. Becomes possible.

[Brief description of the drawings]

FIG. 1 is a manufacturing process diagram of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a manufacturing process diagram of the semiconductor device according to the first embodiment of the present invention.

FIG. 3 is a manufacturing process diagram of the semiconductor device according to the first embodiment of the present invention.

FIG. 4 is a manufacturing process diagram of the semiconductor device according to the first embodiment of the present invention.

FIG. 5 is a manufacturing process diagram of the semiconductor device according to the first embodiment of the present invention.

FIG. 6 is a manufacturing process diagram of the semiconductor device according to the second embodiment of the present invention.

FIG. 7 is a manufacturing process diagram of the semiconductor device according to the second embodiment of the present invention.

FIG. 8 is a manufacturing process diagram of the semiconductor device according to the second embodiment of the present invention.

FIG. 9 is a manufacturing process diagram of the semiconductor device according to the third embodiment of the present invention.

FIG. 10 is a manufacturing process diagram of the semiconductor device according to the third embodiment of the present invention.

FIG. 11 is a manufacturing process diagram of the semiconductor device according to the third embodiment of the present invention.

FIG. 12 is a manufacturing process diagram of the semiconductor device according to the third embodiment of the present invention.

FIG. 13 is a manufacturing process diagram of the semiconductor device according to the third embodiment of the present invention.

FIG. 14 is a manufacturing process diagram of the semiconductor device according to the third embodiment of the present invention.

FIG. 15 is a manufacturing process diagram of a conventional semiconductor device.

FIG. 16 is a manufacturing process diagram of a conventional semiconductor device.

FIG. 17 is a manufacturing process diagram of a conventional semiconductor device.

[Explanation of symbols]

Reference Signs List 1 silicon substrate 2 field oxide film 3 gate insulating film 4 gate electrode 5 sidewall insulating film 8 p + diffusion layer 9 silicon oxide layer 11 silicon substrate 12 field oxide film 13 gate insulating film 14a polycrystalline silicon layer 14b tungsten silicide layer 14c silicon oxide Film 15 sidewall insulating film 18 p + diffusion layer 19 silicon oxide layer 20 nickel layer 21 NiSi crystal film (first compound layer) 22 NiSi ₂ crystal film (second compound layer) 24 titanium nitride layer 25 aluminum silicon alloy layer

──────────────────────────────────────────────────続 き Continued on the front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) H01L 21/28 301 H01L 21/3205 H01L 21/336 H01L 21/768

Claims (4)

(57) [Claims] 1. A method of manufacturing a semiconductor device, comprising the step of forming a contact with a conductive type region formed on a semiconductor substrate, wherein a composition ratio of a metal element to a substrate constituent element is 1 on a contact region on the substrate surface. That's the first
A metal compound layer forming step of forming a metal compound layer, and thereafter, a nucleus of a second metal compound having a composition ratio of a metal element to a constituent element of the semiconductor substrate of less than 1 is generated on the surface of the first metal compound layer. A method for producing a semiconductor device, comprising: a nucleus generating step to be performed; and a heat treatment step of subsequently converting the first metal compound layer into a second metal compound layer by using heat treatment. 2. The method according to claim 1, wherein the nucleation step is an ion implantation step of implanting ions to a depth of の or less of the thickness of the first metal compound layer. A method for manufacturing a semiconductor device. 3. The method according to claim 1, wherein the nucleation step is performed by vapor phase growth of silicon. 4. A method for manufacturing a semiconductor device, comprising the step of forming a contact with a conductive type region formed on a semiconductor substrate, wherein a composition ratio of a metal element to a substrate constituent element is 1 on a contact region on the substrate surface. That's the first
A metal compound layer forming step of forming a metal compound layer, and thereafter, an amorphous film containing a constituent element of a semiconductor substrate is formed on the first metal compound layer, and then the first metal compound is formed by heat treatment. A heat treatment step of changing the layer to a layer of a second metal compound in which the composition ratio of the metal element to the constituent elements of the semiconductor substrate is smaller than 1.