JPH09102469A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a manufacturing method, for a semiconductor device, in which a low-temperature heat treatment can be executed when a silicide layer is formed and in which a contact resistance at a fine contact can be reduced. SOLUTION: An opening part 7 and an opening part 8 which reach a semiconductor substrate are formed in an insulating film 6, the surface of the semiconductor substrate which is exposed in the opening parts is made amorphous, a high-melting-point-metal film 13 is formed on the amorphous surface at bottom parts of the openings so as to be a film thickness of 3 to 10nm, and a high- melting-point metal silicide layer 15 is formed by a heat treatment. Alternatively, the surface of a semiconductor which is exposed in an opening part is made amorphous, and a high-melting-point-metal film is formed by a chemical vapor growth method.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device which forms an ohmic contact with a semiconductor substrate.

[0002]

2. Description of the Related Art In order to form a low resistance connection with a semiconductor substrate through an opening (contact hole) formed in an interlayer insulating film, a refractory metal film is formed and then reacted with the semiconductor substrate by heat treatment. A method of forming a silicide layer of a refractory metal film is used. In particular, in the case of a titanium film, the Schottky barrier is small for both N-type semiconductors and P-type semiconductors, so that low resistance connection can be formed with both types of semiconductors, and the reducing property is strong, and Since the silicide layer can be easily formed by reducing the natural oxide film, various methods relating to this have been proposed.

For example, in the 38th Spring Applied Physics Society Proceedings 30p-W-7, a titanium film having a thickness of 5 to 40 nm is formed on a silicon substrate, and after heat treatment, the contact resistance is measured. It has been reported that when the film thickness is 10 nm or less, the contact resistance sharply increases as the film thickness decreases.

On the other hand, in Japanese Unexamined Patent Publication No. 4-215424, arsenic is ion-implanted to make it amorphous so that the film thickness is 100 nm.
After forming the titanium film, the heat treatment at a low temperature of 500 ° C. or lower is disclosed.

[0005]

However, in the former method, the absolute value of the contact resistance becomes high because it is heat-treated in a single crystal state to form a silicide, and high-temperature heat treatment is required. The formed impurity region undesirably diffuses and adversely affects the device characteristics.

In the latter method, low-temperature heat treatment can be adopted, but the growth time is long because the titanium film is formed as thick as 100 nm, and many raw materials are required, resulting in high cost. Further, a thick silicide layer is formed by the amorphous silicon and the thick titanium film. However, if the refractory metal forming the silicide layer by reacting with silicon in an amorphous state is too thick, the contact resistance will increase. This is because the impurities in the diffusion layer are diffused into the thick silicide layer, the concentration of impurities in the diffusion layer, especially the impurity near the interface between the refractory metal silicide and the diffusion layer is reduced, and the contact resistance is increased. This tendency is particularly remarkable when the contact hole (opening formed in the interlayer insulating film) is a square fine contact having a diameter of 0.5 μm or less or a side of 0.5 μm or less.

On the other hand, the aspect ratio of the contact hole becomes higher as the integration of the LSI becomes higher, and for the contact hole having a high aspect ratio, a refractory metal or a refractory metal is formed on the bottom of the contact hole by a conventional method such as sputtering. It becomes difficult to form silicide sufficiently. Therefore, a study was conducted to suppress a decrease in coverage of the bottom of the contact hole by forming a refractory metal or refractory metal silicide by a chemical vapor deposition method (CVD method). However, when the surface of the diffusion layer at the bottom of the contact hole is a single crystal, the Ti film thickness formed by the P ⁺ diffusion layer and the N ⁺ diffusion layer is different. Therefore, when optimizing one film thickness for the other, There is a problem that if the film thickness is too thick, the leak current increases, and if it is too thin, the electrical resistance of the device deteriorates and the electrical characteristics of the device deteriorate.

Therefore, an object of the present invention is to provide a manufacturing method for a semiconductor device which can be heat-treated at a low temperature and can reduce the contact resistance particularly in a fine contact.

Another object of the present invention is to prevent the lowering of the coverage of the bottom of a contact hole having a high aspect ratio, and a film of refractory metal or refractory metal silicide due to the conductivity type of the surface of the diffusion layer at the bottom of the contact hole. It is an object of the present invention to provide a manufacturing method for a semiconductor device capable of suppressing a thickness difference and thereby obtaining a predetermined electric characteristic.

[0010]

A feature of the present invention is to form an insulating film having an opening (contact hole) reaching the semiconductor substrate on the semiconductor substrate, and forming a refractory metal film. A method of manufacturing a semiconductor device, comprising the step of reacting the semiconductor substrate with the refractory metal film by heat treatment to form a refractory metal silicide layer,
A semiconductor in which the surface of the semiconductor substrate exposed in the opening is made amorphous before forming the refractory metal film, and then the refractory metal film is formed in a thickness of 3 to 10 nm on the bottom of the opening. It is in the method of manufacturing the device. Here, as a method for amorphizing the surface of the semiconductor substrate, boron, boron fluoride (B
F ₂ ), phosphorus or arsenic ion implantation can be used. In this case, an element region is formed on the surface of the semiconductor substrate connected through the opening, and when the element region is an N-type diffusion layer, phosphorus or arsenic is ion-implanted so that the element region is a P-type diffusion layer. At this time, it is preferable to ion-implant boron or boron fluoride to amorphize the semiconductor substrate.

A plurality of the openings are provided, and a step of ion-implanting phosphorus or arsenic through the plurality of openings to amorphize the surface of each semiconductor substrate, and the plurality of openings. The element region to be connected is P
And ion implantation of boron or boron fluoride at a concentration higher than that of phosphorus or arsenic through only the opening of the mold diffusion layer. Alternatively, a plurality of the openings are provided, and a step of ion-implanting boron or boron fluoride through the plurality of openings to amorphize the surface of each semiconductor substrate, and the plurality of openings. The element region to be connected among them may be ion-implanted with phosphorus or arsenic at a higher concentration than the boron or boron fluoride through only the opening of the N-type diffusion layer.

Further, it is preferable that the refractory metal film is a titanium film, and it is more preferable that a step of forming a titanium nitride film on the entire surface by sputtering or chemical vapor deposition after forming the titanium film is further included. After a tungsten film is entirely grown on the titanium nitride film by chemical vapor deposition, the tungsten film is entirely etched until the titanium nitride film is exposed to leave the tungsten film only in the opening. Can be included. Moreover, the heat treatment for forming the silicide layer is performed for 40 times.
It can be performed at a low temperature of 0 to 500 ° C.

As described above, according to the present invention, the refractory metal film is formed on the surface of the semiconductor substrate which has been made amorphous, and the refractory silicide layer is formed. Therefore, the formation can be performed by the low temperature heat treatment. As a result, adverse effects on other element regions can be suppressed. Further, since the film thickness of the refractory metal film is set to 3 nm or more, the film thickness of the refractory metal silicide layer necessary to reduce the contact resistance can be obtained.
Since the thickness is set to 10 nm or less, many P-type and N-type impurities diffuse into the refractory metal silicide layer that is too thick, and the impurity concentration in the P-type diffusion layer and the N-type diffusion layer decreases to reduce the contact resistance. It is prevented from rising.

FIG. 9 shows the result of the experimental study conducted by the inventor of the present invention. Fig. 9 shows P when the contact hole is 0.5 μm
^The contact resistance to the ⁺ type diffusion layer is shown to depend on the Ti film thickness at the bottom of the contact hole.

When a silicide layer is formed by heat-treating the surface of the single crystal silicon substrate and the Ti film, the contact resistance decreases as the film thickness of the Ti film increases, as shown by the data in which the X mark is connected by a chain line. ing. It is a conventional recognition that the contact resistance decreases as the film thickness increases.

On the other hand, when a silicide layer is formed by heat treating the surface of the amorphous silicon substrate and the Ti film, the film thickness of the Ti film is Is more than 10 nm or less than 3 nm, the contact resistance rapidly increases, and a low contact resistance is 10 nm when the film thickness is 3 nm or more.
It can be seen that the range is as follows.

Still another feature of the present invention is the step of forming an opening (contact hole) reaching the semiconductor substrate in the insulating film on the semiconductor substrate, and a refractory metal or a refractory metal on the semiconductor substrate exposed in the opening. In a method of manufacturing a semiconductor device including a step of forming a refractory metal silicide, the surface of a semiconductor substrate exposed in the opening is made amorphous, and then the refractory metal is deposited on the bottom of the opening by chemical vapor deposition. Alternatively, it is a method for manufacturing a semiconductor device in which a refractory metal silicide is formed. Here, the method for making the surface of the semiconductor device amorphous is preferably ion implantation, and in this case, boron, boron fluoride (BF ₂ ), phosphorus or arsenic can be used. The refractory metal is preferably titanium (Ti), in which case Ti can be formed at a forming temperature of 600 ° C. or lower by reducing TiCl ₄ .

As described above, according to the present invention, since the refractory metal or the refractory metal silicide is formed by the chemical vapor deposition method, it is possible to suppress the lowering of the coverage of the bottom of the opening (contact hole) having a high aspect ratio. Since the surface of the semiconductor substrate is made amorphous prior to this formation, the difference in film thickness of the refractory metal or refractory metal silicide due to the conductivity type is suppressed,
This makes it possible to obtain predetermined electrical characteristics.

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings.

1 and 2 are cross-sectional views showing the main steps in the manufacturing method according to the first embodiment of the present invention.

[0021] First, in FIG. 1 (A), the selectively formed silicon oxide film 3 on the main surface of the P-type silicon substrate 1, as an element region, N ^- -type diffusion layer 2 is formed, N ^- -type diffusion layer A P ⁺ -type diffusion layer 4 is formed in the inner part 2 and an N ⁺ -type diffusion layer 5 is formed in another part. In addition, the P ⁺ type diffusion layer 4 and the N ⁺
The mold diffusion layer 5 is partitioned by the silicon oxide film 3 and separated by the silicon oxide film 3.

A BP with a thickness of 1.5 μm is formed on this semiconductor substrate.
The SG film 6 is formed as an interlayer insulating film by the CVD method, and is formed by the ordinary lithography technique and dry etching technique.
First and second contact holes (openings) 7 and 8 having a diameter of 0.5 μm reaching the P ⁺ type diffusion layer 4 and the N ⁺ type diffusion layer 5, respectively, are formed in the BPSG film 6. When the P ⁺ -type diffusion layer 4 and the N ⁺ -type diffusion layer 5 are small and there is no margin for alignment of the contact holes 7 and 8, FIG.
As shown in (A), the contact holes 7 and 8 protrude from these diffusion layers 4 and 5.

Next, in FIG. 1B, boron fluoride (BF ₂ ) is added through the first contact hole 7 in a state where the inside of the second contact hole 8 and its periphery are masked by the photoresist film 9. Ions are implanted into the surface of the ⁺ type diffusion layer 4 and the substrate surface around it. The ion implantation conditions are 5 × 10 ¹⁴ / accelerating energy of 10 to 30 keV.
The implantation amount is from cm ² to 5 × 10 ¹⁵ / cm ² . At this time, the substrate surface exposed in the first contact hole 7 becomes amorphous due to the damage caused by the ion implantation of BF ₂ . That is, the surface of the P ⁺ type diffusion layer 4 becomes the amorphous silicon layer 10 shown by x in the figure.

Next, in FIG. 1C, after the photoresist film 9 is removed, the inside of the first contact hole 7 and its periphery are masked with the photoresist film 11, and the second contact hole 8 is passed through. Phosphorus is ion-implanted into the surface of the N ⁺ type diffusion layer 5 and the substrate surface around it. The conditions for ion implantation are acceleration energy of 10 to 70 keV and an implantation amount of 3 × 10 ¹⁴ / cm ² to 1 × 10 ¹⁵ / cm ² . Also at this time, the substrate surface exposed in the second contact hole 8 becomes amorphous due to the damage of phosphorus ion implantation. That is, the surface of the N ⁺ type diffusion layer 5 becomes the amorphous silicon layer 12 shown by x in the figure.

Next, in FIG. 2A, after removing the photoresist film 11, a Ti film (titanium film) 13 and a TiN film (titanium nitride film) 14 are formed by a sputtering method.
Are sequentially formed.

The Ti film 13 is determined to have a thickness of 3 to 10 nm on the bottoms of the contact holes 7 and 8. For example, assuming that the aspect ratio of the collimator plate disposed between the target of the sputtering device and this semiconductor substrate (semiconductor wafer) is 3, the coverage ratio at the bottom of the contact holes 7 and 8 (film thickness at the bottom of the hole / flat portion) (Film thickness on (top surface of BPSG film))
Is about 13%, the thickness may be 23 to 77 μm in the flat portion. The collimator plate is a plate provided with a large number of holes. By passing through these holes, only the sputtered particles close to the normal line of the substrate are allowed to pass and collide with the semiconductor substrate.

The TiN film 14 prevents the Ti film 13 from being nitrided at the time of annealing which is the next step, and also serves as a barrier film when W (tungsten) grows at the next step. And the film thickness is approximately 10 at the flat portion.
It may be formed to 0 nm. Without this TiN film 14, the Ti film 13 is nitrided by the heat treatment in the next step, so that a thicker Ti film is required.

Next, as shown in FIG. 2B, heat treatment is performed in a nitrogen atmosphere at 400 to 500 ° C. for 10 to 60 minutes.

As a result, the Ti film 13 reacts with the P ⁺ type diffusion layer 4 and the N ⁺ type diffusion layer 5 at the bottoms of the contact holes 7 and 8 to form a titanium silicide layer 15.

Further, by this heat treatment, the crystallinity of the amorphous layers 10 and 12 is recovered to become substantially single crystal and electrically activated, and the single crystal P-type diffusion layer 4 is also formed at the position misaligned. ′ And N type diffusion layer 5 ′ are formed so as to be continuously connected to P ⁺ type diffusion layer 4 and N ⁺ type diffusion layer 5, respectively. This prevents the first and second contact holes 7 and 8 from protruding from the P-type diffusion layer and the N-type diffusion layer, respectively, and does not deteriorate the device characteristics.

The electrical activation rate is 400 to 500 ° C. when the high temperature annealing at about 850 ° C. is 100%.
The low temperature annealing of 10 to 50% is as low as about 10 to 50%, and the reverse current of the junction may be about 10 times higher. However, in a normal semiconductor device, such a current does not cause a problem in electrical characteristics.

Next, in FIG. 2C, tungsten (W) 16 is formed on the entire surface of the TiN film 14 by chemical vapor deposition to a thickness of about 0.5 μm, and the contact holes 7,
After burying 8, the TiN film 14 on the upper surface is etched to expose the tungsten film 16 only inside the contact holes 7 and 8. After that, an Al alloy film 17 in which Cu (copper) of 0.5% is added to Al (aluminum) is formed to a thickness of about 0.5 μm by a sputtering method, and is formed by an ordinary lithography technique and dry etching technique.
The Al alloy film 17, the TiN film 14, and the Ti film 13 are patterned into desired shapes to form Al wiring.

As described above, the Ti film is formed on the bottom of the contact hole to have a thickness of 3 nm or more and 10 nm or less, because the Ti silicide layer required to reduce the contact resistance when the Ti film is thinner than 3 nm is used. The contact resistance cannot be reduced sufficiently because the film thickness is too thin.
When the thickness is thicker than nm, the Ti silicide layer is too thick and a large amount of P-type or N-type impurities are diffused into the Ti silicide layer, so that the impurity concentration in the P-type diffusion layer or the N-type diffusion layer, especially This is because the impurity concentration in the connection portion of these diffusion layers may decrease and the contact resistance may increase, and it is substantially necessary to form the contact hole having a high aspect ratio to a thickness of more than 10 nm by the sputtering method. Because it is difficult. In particular, the resistance of fine contacts connected to the P-type diffusion layer tends to increase. According to the present invention, a contact resistance of about 150Ω for the P-type diffusion layer and about 100Ω for the N-type diffusion layer can be obtained.

Next, a manufacturing method of the second embodiment of the present invention will be described with reference to FIGS. In FIGS. 3 and 4, the same or similar parts as those in FIGS. 1 and 2 are designated by the same reference numerals.

First, the process of FIG. 3A is similar to the process of FIG.

However, in FIG. 3 (B), phosphorus is removed through both the first and second contact holes 7 and 8.
Ion implantation is performed with an acceleration energy of keV and an implantation amount of 3 × 10 ¹⁴ / cm ² or more. By this ion implantation, the surfaces of the P ⁺ type diffusion layer 4 and the N ⁺ type diffusion layer 5 exposed in the contact holes 7 and 8 and the substrate surface around them become amorphous silicon 20 shown by x in the figure.

When the implantation amount of phosphorus is smaller than 3 × 10 ¹⁴ / cm ² , the amorphous silicon layer 20 is not formed. Therefore, the implantation amount is set to 3 × 10 ¹⁴ / cm ² or more.

Next, in FIG. 3C, a photoresist film 21 is formed in and around the second contact hole 8.
In a state of being masked by, through the first contact hole 7 to the surface of the P ⁺ type diffusion layer 4 and the substrate surface around it, boron at an acceleration energy of 20 to 50 keV.
Ion implantation is performed with an implantation amount of 5 × 10 ¹⁵ / cm ² .

Since boron is light, the silicon substrate cannot be amorphized unless the implantation amount is 1 × 10 ¹⁶ / cm ² or more, but here, the silicon substrate is amorphized by the phosphorus ion implantation in the previous step, and the amorphous silicon layer is formed. Since 20 is formed, 1
An injection amount smaller than × 10 ¹⁶ / cm ² is sufficient, but FIG.
The diffusion layer 4 formed on the surface of the diffusion layer 4 or at a position displaced from the diffusion layer 4 by increasing the implantation amount of phosphorus in the step (B)
Must be kept in mold.

Next, in FIG. 4A, after removing the photoresist film 21, a Ti film 13 and a TiN film 14 are sequentially formed by a sputtering method as in the case of FIG. 2A. T
The i film 13 has a thickness of 3 to 10 nm at the bottom of the contact holes 7 and 8.
The thickness of the TiN film 14 is about 100 nm in the flat portion.

Next, in FIG. 4B, heat treatment is performed in a nitriding atmosphere at 400 to 500 ° C. for 10 to 60 minutes to form a Ti silicide layer 19 on the bottoms of the contact holes 7 and 8. By this heat treatment, the amorphous layer 20 becomes a single crystal, and phosphorus and boron are electrically activated, so that the single crystal P-type diffusion layer 4'and the N-type diffusion layer 5'are also P ^+. The structure is formed so as to be continuously connected to the type diffusion layer 4 and the N ⁺ type diffusion layer 5, respectively.

In this second embodiment, since boron is ion-implanted as a P-type impurity, the amorphous layer 17 is made into a single crystal at a lower temperature and in a shorter time than the boron fluoride of the first embodiment. , Electrically active is possible. The reason is that in boron fluoride, fluorine blocks these conversions.

Next, in FIG. 4C, similarly to FIG. 2C, after filling the contact holes 7 and 8 with tungsten 16, an Al alloy film 17 is formed, and an Al alloy film 17 and
The TiN film 14 and the Ti film 13 are patterned into a desired shape to complete Al wiring.

In the second embodiment, the number of photoresist films is one less than that in the first embodiment.
It has advantages that the number of steps can be reduced and the manufacturing cost can be reduced.

Next, referring to FIGS. 5 to 7, the third embodiment of the present invention will be described.
The manufacturing method of the embodiment will be described. 5 to 7
In FIG. 1, the same or similar parts as in FIGS. 1 and 2 are designated by the same reference numerals.

First and second contact holes 7 and 8 respectively reaching the P ⁺ type diffusion layer 4 and the N ⁺ type diffusion layer 5 formed on the P type silicon substrate 1 are formed in the BPSG film 6 (see FIG. A)), and using the photoresist film 9 as a mask, BF ₂ is ion-implanted through the first contact hole 7 to form an amorphous silicon layer 10 (FIG. 5).
(B)) First embodiment until phosphorus is ion-implanted through the second contact hole 8 using the photoresist film 11 as a mask to form the amorphous silicon layer 12 (FIG. 5C). 1 (A) to 1 (C).

However, in the third embodiment, as shown in FIG.
In (A), 10 to 30 at a temperature of 800 to 900 ° C.
When the heat treatment is performed in nitrogen for a minute, the amorphous silicon layers 10 and 12 become single crystals, and the ion-implanted BF
The boron and phosphorus of ₂ are electrically activated by almost 100%, and the first contact hole 7 protrudes from the P-type region by the P-type diffusion layer 4 ′ at a position displaced from the P ⁺ -type diffusion layer 4. And the second contact hole 8 is N-type due to the N-type diffusion layer 5'at a position displaced from the N ⁺ -type diffusion layer 5.
It is in a state where it does not overflow from the mold area.

Next, referring to FIG. 6B, the first and second
BF ₂ into which arsenic is implanted through the contact holes 7 and 8 of FIG. 5 at an acceleration energy of 30 keV and larger than 2 × 10 ¹⁴ / cm ² and only through the first contact hole 7 in the step of FIG. 5B. Ion implantation with a much smaller implantation amount than that. By this arsenic ion implantation, the bottom surfaces of the first and second contact holes 7 and 8 become the amorphous silicon layer 22 shown by x in the figure again.

When arsenic is ion-implanted, 2 × 10 ¹⁴ /
If the implantation amount is smaller than cm ² , the amorphous layer cannot be formed on the surface of the silicon substrate. On the other hand, if the implantation amount is larger than the ion-implanted BF _2, the first layer including the surface of the P ⁺ -type diffusion layer 4 is formed. The surface of the substrate in the contact hole 7 is N
It becomes a mold.

Next, referring to FIG. 6C, the first and second
Similar to the above embodiment, the Ti film 13 and the TiN film 14 are sequentially formed by sputtering. The Ti film 13 is formed on the bottoms of the contact holes 7 and 8 to a thickness of 3 to 10 nm.
The N film 14 has a flat portion with a thickness of about 100 nm.

Then, in FIG. 7A, heat treatment is performed at 400 to 500 ° C. for 10 to 60 minutes in a nitrogen atmosphere,
A Ti silicide layer 25 is formed on the bottom of the contact hole. By this heat treatment, the amorphous layer 22 becomes a single crystal. Even if the ion-implanted arsenic is electrically activated by this heat treatment, the P ⁺ -type diffusion layer 4 and the P-type diffusion layer 4 ′ at the displaced position remain P-type.

Next, referring to FIG. 7B, the first and second
In the same manner as in the above embodiment, after filling the contact holes 7 and 8 with tungsten 16, an Al alloy film 17 is formed,
The Al alloy film 17, the TiN film 14, and the Ti film 13 are patterned into desired shapes to complete Al wiring.

In the third embodiment, since the phosphorus of the N ⁺ type diffusion layer 5 and the P ⁺ type diffusion layer 4 are electrically activated by almost 100%, the reverse current of the junction is generated in the middle step. This is almost the same as the level of bonding by the manufacturing method in which high-temperature heat treatment is performed without forming an amorphous material. Therefore, the method of this embodiment is effective for a device that requires a small reverse current.

In the third embodiment, arsenic is ion-implanted to form the amorphous layer 22. However, when the contact resistance to the P ⁺ type diffusion layer is increased by this method, arsenic is used instead of arsenic. It is better to ion-implant BF ₂ . Alternatively, BF ₂ is ion-implanted into the surface of the P ⁺ -type diffusion layer and its periphery through the first contact hole, and phosphorus is ion-implanted into the surface of the N ⁺ -type diffusion layer and its periphery through the second contact hole. Then, the lowest contact resistance can be obtained for both the P ⁺ type diffusion layer and the N ⁺ type diffusion layer.

Next, a manufacturing method according to the fourth embodiment of the present invention will be described with reference to FIG. In this fourth embodiment,
This is a case where there is a margin in alignment between the contact hole and the diffusion layer connected thereunder.

In FIG. 8A, the P-type silicon substrate 3
1. A silicon oxide film 33 is selectively formed on the main surface of No. 1, an N ⁻ type diffusion layer 32 is formed as an element region, a P ⁺ type diffusion layer 34 is formed in the N ⁻ type diffusion layer 32, and An N ⁺ type diffusion layer 35 is formed at the location. The P ⁺ type diffusion layer 34 and the N ⁺ type diffusion layer 35 are partitioned by the silicon oxide film 33 and are separated from each other by the silicon oxide film 33.

A BP with a film thickness of 1.5 μm is formed on this semiconductor substrate.
The SG film 36 is formed as an interlayer insulating film by the CVD method,
The P ⁺ -type diffusion layer 34 and the N ⁺ are formed on the BPSG film 36 by the usual lithography technique and dry etching technique.
First and second contact holes (openings) 37 and 38 reaching the type diffusion layer 35 are formed.

P ⁺ type diffusion layer 34 and N ⁺ type diffusion layer 35
Has a large plane area and has a margin for alignment, and the contact holes 37 and 38 do not protrude from the diffusion layers 34 and 35.

In such a case, in the next FIG. 8B, arsenic is added to the first and second layers as in the case of the third embodiment.
Ion implantation through the contact holes 37 and 38, or BF ₂ ion implantation through the first and second contact holes 37 and 38 to form the amorphous silicon layer 39 at the bottom of the contact holes.
At this time, the implantation amount of arsenic is smaller than the P-type impurity amount in the P ⁺ -type diffusion layer 34, and the implantation amount of BF ₂ is smaller than the N-type impurity amount in the N ⁺ -type diffusion layer 35. The subsequent formation of the Ti film and the TiN film, the heat treatment, and the wiring formation are the same as those in the first to third embodiments.

10 and 11 are sectional views showing the main steps in the manufacturing method according to the fifth embodiment of the present invention.

FIGS. 10A, 10B and 10C are shown in FIG.
The same as (A), (B), and (C). That is, a silicon oxide film 3 is formed as a field insulating film on the main surface of the P-type silicon substrate 1, an N ⁻ type diffusion layer 2 is formed as an element region, and a P ⁺ type diffusion layer is formed in the N ⁻ type diffusion layer 2. 4 is formed, and an N ⁺ type diffusion layer 5 is formed in another place, and the P ⁺ type diffusion layer 4 and the N ⁺ type diffusion layer 4 are formed on the BPSG film 6 which is an interlayer insulating film.
First and second contact holes (openings) 7 and 8 respectively reaching the type diffusion layer 5 are formed (FIG. 10).
(A)). Next, with the photoresist film 9 masking the inside of the second contact hole 8 and the periphery thereof, boron fluoride (B
The surface of the P ⁺ -type diffusion layer 4 exposed in the first contact hole 7 by ion implantation of F ₂ ) into the surface of the P ⁺ -type diffusion layer 4 and the surrounding substrate surface is an amorphous ( It becomes an amorphous silicon layer 10 (FIG. 10).
(B)). Next, after removing the photoresist film 9, phosphorus in the N ⁺ type diffusion layer 5 is removed through the second contact hole 8 in a state where the inside of the first contact hole 7 and its periphery are masked by the photoresist film 11. The surface of the N ⁺ type diffusion layer 5 exposed in the second contact hole 8 by ion implantation into the surface and the substrate surface around it becomes an amorphous silicon layer 12 shown by x in the figure (see FIG. 10 (C)).

Next, in FIG. 11A, after the photoresist film 11 is removed, a Ti film (titanium film) 41 is formed by plasma chemical vapor deposition (plasma CVD method).

Substrate heating temperature 450 ° C. to 600 ° C., film forming pressure 1 to 100 Torr, TiCl 45 to 20 sccm,
H ₂ 1000~2000sccm, Ar200~500
It is performed under the condition of sccm. The growth film thickness of Ti is 3 to 20 nm
It is.

At the bottom of the contact hole, Ti silicide 15 grows and an amorphous layer is present on the surface of the diffusion layer.
There is no delay time from the flow of ₄ to the growth of Ti 41, and the P ⁺ type diffusion layer 4 and the N ⁺ type diffusion layer 5 can form the Ti silicide layer 15 having the same thickness. Ti4
When the coverage of No. 1 is 100%, the growth film thickness of the Ti silicide layer 15 is about 7.5 to 50 nm.

Subsequently, the TiN film 42 is formed by the LPCVD method. The conditions at this time are the substrate heating temperature of 450 ° C.
650 ° C., film forming pressure 1 to 100 Torr, TiCl ₄ 2
0~50sccm, NH ₃ 50~100sccm, N ₂
2000-5000 sccm, TiN film thickness is 3
0 to 50 nm.

Next, in FIG. 11B, similarly to FIG. 2C, after tungsten (W) is formed on the entire surface of the TiN film 42 by the chemical vapor deposition method and the contact holes 7 and 8 are buried, Etching is performed until the TiN film 42 on the upper surface is exposed, the tungsten film 16 is left only inside the contact holes 7 and 8, and an Al alloy film 17 is formed.
7, TiN film 42, and Ti film 41 are patterned into desired shapes to form Al wiring.

As described above, in this embodiment,
Since the surface of the Si substrate exposed in the contact hole is amorphous and active, there is no delay time until Ti grows while flowing TiCl ₄ , and P ⁺ Si and N ⁺ Si form a Ti film of equal thickness. This makes it possible to suppress deterioration of the electrical characteristics of the device.

P ⁺ Si of delay time until Ti grows
The difference between N ⁺ Si and N ⁺ Si is more remarkable when the growth temperature is lower,
The effect of the present invention is more remarkable as the growth temperature of Ti is lower, and particularly the effect is large at 600 ° C. or lower.

Further, since the Ti film 41 is formed by the CVD method in this embodiment, the Ti film 41 has better coverage than the sputter method, and even the bottom of the contact hole having a high aspect ratio can easily be formed with 10 nm Ti (25 nm for Ti silicide). ) Can be formed, and the film thickness of the Ti film 41 at the contact bottom is not particularly required to be 10 nm or less.
It is better to set it to nm or less.

On the other hand, unlike FIG. 12, the single crystal P ⁺ exposed at the bottom of the contact hole is not subjected to the steps of FIGS. 10B and 10C after the contact hole is opened, unlike the present invention. -Type diffusion layer surface and single crystal N ⁺
Ti film on the surface of the diffusion layer of TiC by chemical vapor deposition
6 is a graph showing the film thickness of a Ti film when formed by reducing l ₄ , wherein the film thickness on the surface of the P ⁺ type diffusion layer (P ⁺ ) and the film thickness on the surface of the N ⁺ type diffusion layer (N ⁺ ) You can see that and are very different. This is because the delay time from the flow of TiCl ₄ to the growth of Ti differs between P ⁺ Si and N ⁺ Si. Therefore, when optimizing one film thickness, if the other film thickness is too thick, leakage current increases or electric resistance increases, and if it is too thin, the electric resistance also increases. Have the problem of doing.

Although Ti has been exemplified as the refractory metal in each of the above embodiments, the same effect can be expected with other refractory metals.

[0072]

As described above, according to the present invention, a refractory metal film is formed on the surface of an amorphous semiconductor substrate to form a refractory silicide layer. The heat treatment can be performed at a low temperature of 400 to 500 [deg.] C., which can suppress adverse effects on other element regions already formed.

Further, since the film thickness of the refractory metal film is set to 3 nm or more, the film thickness of the refractory metal silicide layer necessary to reduce the contact resistance can be obtained, and the film thickness of the refractory metal silicide layer is set to 10 nm or less. It is prevented that a large amount of P-type or N-type impurities are diffused therein, the impurity concentration in the P-type diffusion layer or the N-type diffusion layer is reduced, and the contact resistance is increased.

Further, according to the present invention, since the refractory metal or refractory metal silicide is formed by the chemical vapor deposition method, it is possible to suppress the lowering of the coverage of the bottom of the opening (contact hole) having a high aspect ratio. Since the surface of the semiconductor substrate is made amorphous prior to this formation, it is possible to suppress the film thickness difference between the refractory metal or refractory metal silicide on the P-type diffusion layer and the N-type diffusion layer. Predetermined device electrical characteristics can be obtained.

[Brief description of the drawings]

FIG. 1 is a sectional view illustrating a method of manufacturing a semiconductor device according to a first embodiment of the present invention in the order of steps.

FIG. 2 is a cross-sectional view showing a step subsequent to FIG. 1 in order;

FIG. 3 is a cross-sectional view showing a method of manufacturing a semiconductor device according to a second embodiment of the present invention in the order of steps.

FIG. 4 is a cross-sectional view showing a step subsequent to FIG. 3 in order;

FIG. 5 is a sectional view illustrating a method of manufacturing a semiconductor device according to a third embodiment of the present invention in the order of steps.

FIG. 6 is a sectional view sequentially showing a step following that shown in FIG. 5;

FIG. 7 is a cross-sectional view showing a step that follows the step of FIG. 6 in order.

FIG. 8 is a cross-sectional view showing the method of manufacturing a semiconductor device according to the fourth embodiment of the present invention in the order of steps.

FIG. 9 is a diagram showing the effect of the present invention.

FIG. 10 is a cross-sectional view showing the method of manufacturing a semiconductor device according to the fifth embodiment of the present invention in the order of steps.

FIG. 11 is a cross-sectional view showing a step subsequent to FIG. 10 in order;

FIG. 12 is a diagram showing a disadvantage of a manufacturing method different from that of the present invention.

[Explanation of symbols]

1,31 P-type silicon substrate 2,32 N ^- type diffusion layer 3,33 Silicon oxide film 4,34 P ⁺ type diffusion layer 4 ′ P type diffusion layer formed at a shifted position 5,35 N ⁺ type diffusion layer 5'N-type diffusion layer formed at a shifted position 6,36 BPSG film 7,37 First contact hole (opening) 8,38 Second contact hole (opening) 9,11,21 Photoresist film 10, 12, 20, 22, 39 Amorphous silicon layer 13 Ti film Titanium film 14 TiN film (titanium nitride film) 15, 19 Ti silicide layer 16 Tungsten film 17 Al alloy film 41 Ti film 42 TiN film

Front page continuation (72) Inventor Kouji Urabe 5-7-1, Shiba, Minato-ku, Tokyo Inside NEC Corporation (72) Inventor Yoshiaki Yamada 5-7-1, Shiba, Minato-ku, Tokyo NEC Stock company

Claims (16)

[Claims] 1. A step of forming an insulating film having an opening reaching a semiconductor substrate on the semiconductor substrate, a step of forming a refractory metal film, and a heat treatment to react the semiconductor substrate with the refractory metal film. And a step of forming a refractory metal silicide layer to produce a semiconductor device,
Amorphizing the surface of the semiconductor substrate exposed in the opening before forming the refractory metal film, and then forming the refractory metal film to a thickness of 3 to 10 nm on the bottom of the opening. A method for manufacturing a semiconductor device, comprising: 2. The method of manufacturing a semiconductor device according to claim 1, wherein the method of amorphizing the surface of the semiconductor substrate is ion implantation. 3. The method for manufacturing a semiconductor device according to claim 2, wherein the ion implantation is boron, boron fluoride (BF ₂ ), phosphorus or arsenic ion implantation. 4. An element region is formed on the surface of a semiconductor substrate connected through the opening, and when the element region is an N-type diffusion layer, phosphorus or arsenic is ion-implanted, and the element region is P-type. The method for manufacturing a semiconductor device according to claim 3, wherein in the case of a diffusion layer, boron or boron fluoride is ion-implanted to amorphize the semiconductor substrate. 5. A plurality of the openings are provided, and phosphorus or arsenic is ion-implanted through the plurality of openings to amorphize the surface of each semiconductor substrate.
A step of implanting boron or boron fluoride at a concentration higher than that of the phosphorus or arsenic ion implantation through the opening of the P-type diffusion layer in the connected element region among the plurality of openings. The method for manufacturing a semiconductor device according to claim 3. 6. A plurality of said openings are provided, and a step of ion-implanting boron or boron fluoride through said plurality of openings to amorphize the surface of each semiconductor substrate; The element region to be connected among the openings of (1) is ion-implanted with phosphorus or arsenic at a higher concentration than the ion implantation of boron or boron fluoride through only the opening of the N-type diffusion layer. The method for manufacturing a semiconductor device according to claim 3. 7. The method of manufacturing a semiconductor device according to claim 1, wherein the refractory metal film is a titanium film. 8. The method of manufacturing a semiconductor device according to claim 7, further comprising the step of forming a titanium nitride film on the entire surface by sputtering or chemical vapor deposition after forming the titanium film. 9. The method of manufacturing a semiconductor device according to claim 8, wherein a heat treatment temperature for forming the refractory metal silicide layer is 400 to 500 ° C. 10. A tungsten film is entirely grown on the titanium nitride film by a chemical vapor deposition method, and then the tungsten film is entirely etched until the titanium nitride film is exposed to expose the tungsten film only in the opening. 10. The method for manufacturing a semiconductor device according to claim 8, further comprising a step of leaving a film. 11. A semiconductor including: a step of forming an opening reaching a semiconductor substrate in an insulating film on the semiconductor substrate; and a step of forming a refractory metal or refractory metal silicide on the semiconductor substrate exposed in the opening. In the method of manufacturing the device, after the semiconductor substrate surface exposed in the opening is made amorphous, the refractory metal or refractory metal silicide is formed on the bottom of the opening by chemical vapor deposition. And a method for manufacturing a semiconductor device. 12. The method of manufacturing a semiconductor device according to claim 11, wherein the method of amorphizing the surface of the semiconductor device is ion implantation. 13. The method of manufacturing a semiconductor device according to claim 12, wherein the ion implantation is boron, boron fluoride (BF ₂ ), phosphorus or arsenic ion implantation. 14. The refractory metal is titanium (Ti).
14. The method of manufacturing a semiconductor device according to claim 11, 12, or 13. 15. The method of manufacturing a semiconductor device according to claim 14, wherein the Ti is formed by reducing TiCl ₂ . 16. The method of manufacturing a semiconductor device according to claim 15, wherein the formation temperature of Ti is 600 ° C. or lower.