JP2944125B2 - Semiconductor device - Google Patents

Description

The present invention relates to a semiconductor device, and more particularly to an improvement in a semiconductor device having a shallow impurity layer.

(Prior Art) In recent years, large-scale integrated circuits (LSIs) are frequently used in important parts of computers and communication devices. One way to increase the performance of a single LSI is to use an L
The goal is to increase the degree of integration of LSI by miniaturizing the basic SI elements. Therefore, in MOS field-effect transistors, the gate length has been reduced and the source and drain regions have been made thinner. As a method for forming shallow source and drain regions, a low acceleration ion implantation method is widely used.
By this method, a shallow source / drain region of about 0.1 μm is formed. However, the impurity diffusion layer formed by the low-acceleration ion implantation method has a sheet resistance of 100 Ω /
It is a high value of □ or more. In order to increase the speed of the fine MOS field effect transistor, it is necessary to reduce the sheet resistance of the source and drain impurity layers. Therefore, a salicide method of forming a metal compound layer in a self-aligned manner on the source and drain impurity layers has been considered.

FIG. 13 is a process sectional view for explaining salicide. First, on the surface of the silicon substrate 31, an element formation region is limited by a field oxide film 32, a gate electrode portion is formed in this region, and a spacer 35 having a width of about 150 nm is formed on a side wall of the gate electrode. Next, a thickness of 40 to 50 nm is applied to the surface of the substrate 1.
A degree of cobalt (Co) film 36 is deposited (FIG. 13 (a)). Then, the film is heated by lamp annealing to form a cobalt silicide (CoSi ₂ ) film 37 (FIG. 13 (b)).
Thereafter, the unreacted Co film 36 is removed by etching. The implanted impurity element into CoSi ₂ film 37 by an ion implantation method, the shallow source by heat treatment, drain impurity layer diffusion layers 38 _1, 38 ₂ are formed. Finally, the substrate 1 is covered with an insulating film 39 to form a contact hole,
40 is formed and completed (FIG. 13 (c)).

When a MOS field effect transistor is actually formed by this method, a thin silicide film having a thickness of about 150 nm can be formed.
The sheet resistance has a low value of 1 to 3 Ω / □. However, in order to form a P-type impurity diffusion layer by this method, an attempt is made to manufacture a MOS field-effect transistor having a short gate length using an element having a larger diffusion coefficient than arsenic (As) such as boron (B). The following problems occur.

The solid solubility of B in Si is generally higher than 1100 ° C. than other elements. However, in order to form a shallow P-type impurity diffusion layer by the above-described method, heat treatment must be performed at a low temperature of about 850 ° C. after ion implantation of B, so that the solid solubility of B in Si decreases. I do. As a result, the carrier concentration at the interface between the silicide film and the Si substrate is a low value of 5 × 10 ¹⁹ cm ⁻³ or less, and the contact resistivity with the P-type impurity diffusion layer is 1 × 10 ⁻⁴ Ω · cm ² or more. This is an extremely large value. This makes it impossible to make good electrical contact between the substrate diffusion layer and the extraction electrode. The reason is that when the process temperature becomes lower than 900 ° C., the solid solubility of B in Si becomes 10 ²⁰ cm.
This is because the Schottky barrier at the electrode-Si interface becomes dominant in the contact resistance since it is ^-3 or less. According to the field emission tunnel theory, it is expected that the contact resistance is reduced by almost one digit only by lowering the Schottky barrier by 0.05 V.

Therefore, in order to reduce the contact resistivity between the P-type impurity diffusion layer and the silicide film, a metal having a lower Schottky barrier than the P-type impurity layer may be used as a material metal of the silicide film. As such a material, instead of Co, Ni
Was used to evaluate the electrical characteristics of a MOS field-effect transistor manufactured in the same manner as in the conventional example. According to this, the contact resistivity between the P-type impurity layer and the Ni silicide film is about 2
It was confirmed to be reduced to × 10 ⁻⁶ Ω · cm ² . But Ni
850 ℃ for thin silicide film less than 100nm
Under the environment of the above temperature, the aggregation phenomenon is likely to occur, so that the film thickness distribution becomes non-uniform, and in some cases, the film becomes discontinuous. As a result, there is a problem that it becomes difficult to manufacture an ultra-fine LSI with high reliability because the allowable range of the fluctuation of the process temperature generated in the manufacturing process is narrowed.

(Problems to be Solved by the Invention) As described above, in the conventional manufacturing of a semiconductor device by the salicide method, when the depth of the impurity layer diffusion layer is set to 0.1 μm or less, the contact resistivity between the substrate diffusion layer and the extraction electrode increases, which is favorable. It has been difficult to make a proper electrical connection. Further, when a metal silicide film having a low Schottky barrier height is used to lower the contact resistivity, there is a problem that the heat resistance of the silicide film is reduced.

An object of the present invention is to provide a salicide structure semiconductor device in which the contact resistivity is reduced without lowering the heat resistance.

[Structure of the Invention] (Means for Solving the Problems) In order to achieve the above object, a semiconductor device according to the present invention includes a semiconductor substrate of a first conductivity type and selectively formed on a surface of the substrate. In a semiconductor device having an impurity layer of a second conductivity type and a metal compound layer including a constituent element of the substrate formed on the surface thereof in self-alignment with the impurity layer, the metal compound layer includes first and second impurity layers. And the height of the Schottky barrier of the first compound formed by the first metal element and the constituent elements of the substrate with respect to the substrate includes the second metal element and the structure of the substrate. The first metal element and the second metal element are mixed such that the melting point of the first compound is lower than that of the second compound formed by the element and the melting point of the first compound is lower than that of the second compound. Selected and said The distribution of the first metal element and the second metal element in the group metal compound layer is such that the first metal element becomes excessive on the interface side between the substrate and the metal compound layer, and the second metal element Is set to be excessive on the surface side of the metal compound layer.

(Function) According to the present invention, the height of the Schottky barrier at the interface between the metal compound layer and the impurity diffusion layer decreases, and the melting point of the metal compound layer on the substrate surface side increases. Therefore, the contact resistivity between the substrate diffusion layer and the extraction electrode can be reduced without lowering the heat resistance.

(Examples) Hereinafter, details of the present invention will be described with reference to the illustrated examples. 1 (a) to 1 (f) are process cross-sectional views showing a manufacturing process of a first embodiment in which the present invention is applied to a MOS transistor. First, as shown in FIG. 1A, an 800 nm thick field oxide film 2 for element isolation is formed on the surface of an n-type Si substrate 1 having (100) as a main surface by thermal oxidation. A gate oxide film 3 having a thickness of 10 nm, a polycrystalline silicon layer 4 having a thickness of 150 nm, a tungsten silicide (WSi _2.8 ) layer 5 having a thickness of 150 nm 5, and a CVD-SiO ₂ film 6 are formed in an element formation region formed by the oxide film 2.
Are sequentially deposited to form a laminated film, and the laminated film is etched to form a gate electrode. Further forming the SiO ₂ film 7 it is provided a CVD-SiO ₂ film having a thickness of 150nm on the surface of the substrate 1 on the side surfaces of the gate electrode is processed by anisotropic etching or the like. Next, as shown in FIG. 1B, an alloy film 8 of Ni and Co having a thickness of 20 nm is formed on the entire surface of the substrate by a sputtering method or the like. At this time, it was confirmed that the composition ratio between Ni and Co in the alloy film 8 was uniform, and the atomic number composition ratio r was 1: 1. Thereafter, annealing is performed at 650 ° C. for 30 minutes in a nitrogen atmosphere to form a Ni—Co alloy silicide film 9 having a thickness of about 70 nm as shown in FIG. 1C. Ni-Co formed at this time
The atomic composition ratio r of silicon to metal in the alloy silicide film 9 was 2. Next, unreacted Ni—Co alloy film 8
Was removed at room temperature by wet etching using a mixed aqueous solution of HCl, H ₂ O ₂ and H ₂ O at a ratio of 1: 1: 6, and a 70 nm thick Ni-Co alloy silicide film was formed on the source and drain regions. 9 is formed in a self-aligned manner. Thereafter, as shown in FIG. 1 (d), B ions are accelerated at an acceleration energy of 25 keV and a dose of 1 × 10 ¹⁶ c.
It is implanted into the Ni—Co alloy silicide film 9 with m− ² .
At this time, the range of B ions was about 50 nm. Then, Si
After depositing an SiO ₂ film 10 of about 300 nm on the surface of the substrate 1 by CVD, lamp annealing is performed at 1050 ° C. for 20 seconds to form source and drain diffusion layers 11 ₁ and 11 ₂ (FIG. 1). (E)). Finally, a 0.7 μm thick CVD-
Depositing a SiO ₂ film 10 on the Si substrate 1, and a contact hole TiN film 13 ₁ and the Al · Si alloy 13 ₁ laminated film of the electrode 13
To complete the MOS transistor (FIG. 1 (f)).

The Ni-C of the MOS transistor formed as described above
o The density distribution of Ni and Co elements in the alloy silicide film 9 in the depth direction was examined. FIG. 2 is a diagram showing the results of evaluation by AES (Auger electron spectroscopy). This shows that Ni is distributed more on the substrate side and Co is distributed more on the surface side. Further, as a result of the SIMS analysis, the source / drain diffusion layers 11 ₁ , 11 ₂
Has a thickness of about 0.1 μm and an interface impurity concentration of 3 × 10 ¹⁹ to 8 × 10
It was confirmed to be a P ⁺ -type impurity diffusion layer of ¹⁹ cm ^-3 . Also
Ni—Co alloy silicide film 9 and source / drain diffusion layers 11
_1, 11 a contact resistance between the ₂ was 23Ω was measured by the contact area of 1 [mu] m ^2.

Next, as a result of evaluating a contact resistivity after forming a Co silicide film instead of the Ni-Co alloy silicide film 9,
The value was 1000 Ω or more at a contact area of 1 μm ² , and the MOS transistor using the Co silicide film did not operate normally.

Next, in order to evaluate the heat resistance, the Ni-Co alloy silicide film, the Ni silicide film, and the Co silicide film were subjected to RT in an N ₂ atmosphere.
A (Rapid Thermal Anneal) was performed. FIG. 3 shows the result. From this, 850 for Ni silicide film
It can be seen that the resistance value suddenly increases at a temperature of not less than ℃ and there is no sufficient heat resistance. On the other hand, it can be seen that the Ni—Co alloy silicide film and the Co silicide film do not change their resistance values up to 950 ° C. and have high heat resistance.

Next, the atomic composition ratio r (Co / (Ni
+ Co)), and the same evaluation was performed by manufacturing a MOS transistor using the Ni—Co alloy film. FIG. 4 is a diagram showing the results of evaluating the contact resistance between the Ni—Co alloy silicide film and the source / drain diffusion layers for a contact surface of 1 μm ² . From this, it was found that the contact resistance hardly changed even when the atomic number composition ratio r was changed, which was in good agreement with that of the NiSi ₂ single layer film.

FIG. 5 shows the results obtained by measuring the dependence of the Schottky barrier height between the P-type Si and the Ni—Co alloy film on the atomic composition ratio r. From this, it can be seen that the graph showing the dependence of the Schottky barrier height on the atomic composition ratio r is similar in shape to that of the contact resistance shown in FIG. From the above, it is considered that the Ni-Co alloy silicide film becomes excessive in Ni at the interface with the P-type impurity layer regardless of the atomic composition ratio r of the Ni-Co alloy film.

FIG. 6 is a graph showing the heat resistance of the Ni—Co alloy silicide film with respect to the atomic composition ratio r. From this, even if r is 0.05, Ni
The heat resistance of the -Co alloy silicide film is 50 times higher than that of the Ni silicide film.
It turns out that it is higher than ° C. This is because a large amount of Co is distributed in the vicinity of the surface of the Ni—Co alloy silicide film, so that the cohesion of Ni, which is largely distributed in the vicinity of the interface, is suppressed. A similar effect can be obtained by forming a laminated film of a Ni ₂ Si ₂ film and a CoSi ₂ film. However, such a complete two-layer film
The change in the distribution of Co and Co in the depth direction is steep, and the stress is large. On the other hand, in the present embodiment, since the change in the density distribution of Ni and Co in the depth direction is continuous as shown in FIG. 2, there is no stress, and since Co is present near the interface, sufficient heat resistance is obtained. Is obtained.

FIG. 7 is a process sectional view showing the manufacturing process of the MOS transistor of the second embodiment. First, a field oxide film 2 and gate electrodes 3 to 7 are formed as shown in FIG. Next, Ar was introduced into a vacuum device with an ultimate vacuum of 1 × 10 ⁻⁵ Pa.
Pressure is set to 0.5 ~ 2Pa and the Si substrate 1
A 10 nm thick Ni film 14 and a 10 nm thick Co film 15 are sequentially deposited on the surface. Since this step is continuously performed in a vacuum, the natural oxide film is unlikely to grow on the interface between the Ni film 14 and the Co film 15 (FIG. 7B). Thereafter, annealing is performed at 650 ° C. for 30 hours in a nitrogen atmosphere in the same manner as in the first embodiment, and about 70 n
The m-Ni-Co alloy silicide film 9 is formed. Then, the unreacted Ni-Co laminated film 16 is removed by wet etching using a mixed aqueous solution of HCl, H ₂ O ₂ and H ₂ O at a ratio of 1: 1: 6, and the thickness of the source region and the drain region is reduced. A Ni-Co alloy silicide film 9 of about 70 nm is formed in a self-aligned manner. The atomic ratio of silicon to metal of the Ni-Co alloy silicide film 9 formed at this time was 2 (FIG. 7 (c)). After this,
B ions are implanted into the Ni—Co alloy silicide film 9 at an acceleration energy voltage of 25 keV and a dose of 1 × 10 ¹⁶ cm ⁻² (FIG. 7D). Then, CV is applied to the entire surface of the Si substrate 1.
After depositing a SiO ₂ film 10 of about 300nm by Process D, 1050 ° C., 20
The lamp is annealed for 2 seconds (FIG. 7 (e)). Finally after the CVD-SiO ₂ film 12 having a thickness of 0.7μm is deposited on the substrate 1 surface as an interlayer insulating film, a TiN film 13 ₁ and the Al · Si alloy 13 ₂ by opening the contact hole on the source region and the drain region The MOS transistor is completed by arranging the electrodes 13 of the laminated film (FIG. 7 (f)).

The density distribution, contact resistivity and heat resistance of the Ni and Co elements in the Ni—Co alloy silicide film 9 formed as described above were examined. As a result, it was confirmed that the distribution of Ni and Co in the Ni—Co alloy silicide film 9 was large on the substrate interface side and the surface side, respectively, as in the first example. Also Ni
In the MOS transistor manufactured by the above method by reversing the deposition order of the film and the Co film, the distribution of Ni and Co elements in the Ni-Co alloy silicide film in the depth direction is the same as that of the first embodiment. Was confirmed.

The reason why the metal distribution in the formed Ni-Co alloy silicide film shows the same distribution regardless of the deposition method and the deposition order of the Ni-Co laminated film is considered as follows. Ni film to Si
In the step of annealing after deposition on a substrate, the phase transition generally occurs with Ni ₂ Si, NiSi, NiSi ₂
In the step of annealing after forming Co on Si, generally, as the annealing temperature increases, Co ₂ Si, Co
Phase transition occurs in the order of Si and CoSi ₂ . Ni ₂ Si, NiSi, NiSi ₂
Are lower than the formation temperatures of Co ₂ Si, CoSi, and CoSi ₂ , respectively. For example, Ni ₂ Si, the initial reaction phase of the Ni / Si system, is Ni
/ Although Si system the formed upon heating at 100 to 200 ° C., Co ₂ Si is
Not formed unless the Co / Si system is heated above 350 ° C. This is because the silicide formation temperature is generally lower in the Ni / Si system than in the Co / Si system. Therefore, when the Ni-Co alloy film is annealed, the reaction between Si and Ni proceeds first on the Si substrate surface where Ni and Co coexist, so
Ni is large and Co is distributed on the surface side. On the other hand, when the Co-Ni laminated film is annealed, the temperature rises,
When Ni comes into contact with Si, the vicinity of the Si interface is Ni-excessive,
When the surface side has excess Co and Co contacts Si, Ni-
Interdiffusion progresses due to the chemical potential gradient generated between Co and Ni gathers at the Si interface, Ni excess near the Si interface, Co excess on the Si surface side, showing the same Ni-Co distribution as in the case of Ni-Co alloy film .

Next, as a result of evaluating the contact resistivity of the Co—Ni laminated film, it was confirmed that the same tendency as the contact resistance characteristic with respect to the contact surface of 1 μm ² shown in FIG. 4 was observed. Further, regarding heat resistance, since two phases of NiSi ₂ and CoSi ₂ generally have the same face-centered cubic lattice structure, the atomic composition ratio of metal (Ni + Co) and Si in the Ni—Co alloy silicide film is r ( Si /
When the metal (metal) is 2, the bond with the Co excess layer near the Ni excess layer is completely continuous as a crystal and has no boundary.
As a result, the entire Ni—Co alloy silicide film can have high heat resistance like a CoSi ₂ film.

In the above embodiment, after forming the Ni / Co alloy silicide film 9, the shallow source / drain diffusion layers 11 ₁ and 11 ₂ are formed by the post doping method. However, the shallow source / drain diffusion layers 11 ₁ and 11 ₂ are formed. After the Ni-Co alloy silicide film 9
It is needless to say that the same effect can be obtained by forming.

FIG. 8 is a process sectional view showing the manufacturing process of the MOS transistor of the third embodiment. First, a field oxide film 2 and gate electrodes 3 to 7 are formed as shown in FIG. Next, Ge ions are implanted into the Si substrate 1 under the conditions of an acceleration energy of 200 keV and a dose of 1 × 10 ¹⁵ cm ^{−2 to make} the surface of the Si substrate 1 preamorphous. Then, BF ₂ is ion-implanted at an acceleration energy of 25 keV and a dose of 5 × 10 ¹⁵ cm ⁻² , and then annealed at 1050 ° C. for 20 seconds to obtain a 0.1 μm.
P ⁺ type source / drain diffusion layers 11 ₁ and 11 ₂ having a shallow m are formed (FIG. 8B). Next, the Si substrate 1 is carried into a sample introduction chamber 20 of a CVD apparatus as shown in FIG.
After the internal pressure is reduced by the exhaust pump,
It is carried into 21. Here, the pressure in the pretreatment chamber 21 is reduced to 1 Torr, active species generated by plasma discharge using SF ₆ and H ₂ O as source gases are introduced, and the back surface of the Si substrate 1 is heated to 100 ° C. by the infrared lamp 22. On the other hand, the surface of the Si substrate 1 is irradiated with ultraviolet light by an ultraviolet lamp 23a. The active species react with SiO _{2 on} the surface of the Si substrate 1 to form SO ₃ HF, so that SiO ₂ is etched away at high speed. As a result, the natural oxide film on the Si substrate 1 is removed, and the clean
A Si surface is obtained. This removal of the natural oxide film may be performed by a treatment using HF vapor. This Si substrate 1 is carried into the growth chamber 24 and the back surface is heated to 700 ° C. by the infrared heater 25. After that, the Ni (C
₆ H _{5) 2 gas, Co (C 6 H 5)} 2 gas and the SiH ₄ gas mixed gas of is supplied from the nozzle 26 at a pressure 0.1 Torr. N at this time
i (C ₆ H ₅ ) ₂ gas, Co (C ₆ H ₅ ) ₂ gas flow rate (Co (C ₆ H ₅ )
₂ / Ni (C ₆ H ₅ ) ₂ ) was varied with the deposited film thickness as shown in FIG. As a result, a Ni-Co alloy silicide film 9 having a thickness of about 70 nm was formed in a self-aligned manner on the exposed Si portion on the surface of the Si substrate 1 (FIG. 8C). Thereafter, a MOS transistor is completed through a process similar to that of the second embodiment.

At this time, Ni in the depth direction in the Ni—Co alloy silicide film 9 is formed.
When the distribution of -Co was examined, it was the same as that of the first example. It was also found that the contact resistance and heat resistance were as good as in the first and second embodiments. Furthermore, the Ni-Co alloy silicide film 9 was thermally stable without agglomeration even after annealing at 850 to 900 ° C for 1 to 2 hours. Next, as a result of detailed evaluation of the interface shape between the Ni—Co alloy silicide film 9 and the source / drain diffusion layers 11 ₁ and 11 ₂ , the source / drain diffusion layers 11 ₁ and 11 11 is moreover the interface roughness was not observed erosion to ₂ has been kept to 50Å or less, Ni-Co alloy silicide film 9 that exhibits a good epitaxial growth at the interface was confirmed. In this example, Ni
The flow ratio of (C ₆ H ₅ ) ₂ gas, Co (C ₆ H ₅ ) ₂ gas and SiH ₄ gas is not limited to that shown in FIG.
The metal distribution in the material can be adjusted within a range in which a desired heat resistance can be obtained.

FIG. 11 is a process sectional view showing the manufacturing process of the MOS transistor of the fourth embodiment. First, FIGS. 11 (a) and (b)
As shown in FIG. 6, the field oxide film 2 and the gate electrode 3 are formed, and the P ⁺ type source / drain diffusion layers 11 ₁ and 11 of shallow 0.1 μm are formed.
The steps from the formation of _{2 to} the step of carrying it into the CVD apparatus and removing the natural oxide film on the surface of the Si substrate 1 are the same as in the third embodiment. Next, the Si substrate 1 is carried into the growth chamber 24 shown in FIG. 9, and the Si substrate 1 is heated to 600 ° C.
The Si ₂ H ₆ gas of SCCM and the H ₂ gas of 1000 SCCM are introduced, and the Si substrate 1 is irradiated with ultraviolet light having an output of 1.2 W / cm ² by the ultraviolet lamp 23b. As a result, the Si film 17 having a thickness of 70 nm is selectively formed only on the exposed portions of the substrate 1. Then lowering the substrate 1 temperature is 400 ° C., and introduced into growth chamber 24 flow rate 5 SCCM, a gas mixture of Ni (C ₆ H _{5) 2} gas and H ₂ gas pressure of 0.1 the pressure 0.1 Torr, Si film 17 A Ni film 14 having a thickness of 10 nm is selectively deposited only on the portion. Thereafter, the introduction of Ni (C ₆ H ₅ ) ₂ gas was stopped, and instead, Co (C
₆ H _{5) 2} gas and flow rate 5 SCCM, selectively depositing a Co film 15 by introducing the H ₂ gas pressure 0.1 on only the Ni film 14. Then, annealing is performed at 650 ° C for 30 minutes in a nitrogen atmosphere, and about 70n
An m-Ni-Co alloy silicide film 9 is formed in a self-aligned manner (FIG. 11D). In addition, a selectively formed Ni film 1
4, Co film 15 reacts with selectively formed Si17,
Erosion by Ni-Co alloy silicide film 9 source, the drain diffusion layer 11 _1, 11 ₂ was observed. After this, the first
Through the same process as in the embodiment, a MOS transistor is completed (FIG. 11 (e)).

It was confirmed that the fourth embodiment also exhibited the same good FET characteristics as the first to third embodiments.

FIG. 12 shows a fifth embodiment. This embodiment is different from the previous embodiment in that a CVD-SiO ₂ film 12 is deposited on the surface of the Si substrate 1 after the steps up to FIG. 8 (c) or FIG. 11 (d) to form contact holes. The point is that an electrode 18 of a tungsten layer or the like is directly provided instead of disposing the electrode by opening it.

The present invention is not limited to the above embodiment. For example, in the fourth embodiment, when forming the silicide alloy layer 5, the heat treatment is performed after depositing the Ni film 14 and the Co film 15, but the formation of the Ni film 14 and the Co film 15 and the heat treatment may be performed simultaneously. good.

In the third, fourth, and fifth embodiments, the Si source, Ni source gas, and Co source gas are SiH ₄ , Ni (C ₆ H ₅ ) ₂ , Co (C
₆ H ₅₎ is not limited to _two. For example, SiH ₂ Cl ₂ as a Si supply source, NiCl ₂ , NiBr ₂ , Ni (C ₂
H ₃ O ₂ ) ₂ , NiF ₂ , Ni (NO ₃ ) ₂ , NiSO ₄ , CoBr ₂ , Co (C ₂ H ₃ O ₂ ) ₂ ,
CoCO ₃ , CoF ₂ , Co (NO ₃ ) ₂ , CoSO ₄ , CoCl ₂ , Ni (Co) ₄ , NiCo ₃
It is possible to use a raw material gas obtained by evaporating, decomposing, and sublimating Ni salts and Co salts such as the above. Further, the composition ratio of Ni and Co can be changed appropriately as in the first and second embodiments.

As described above, according to the present embodiment, the electrical connection between the Si substrate 1 and the electrode is made via the Ni-Co alloy silicide film having a low Schottky barrier height on the Si substrate side and a high heat resistance on the Si surface side. As a result, a good electrical connection can be made between the Si substrate and the electrode even if the source and drain diffusion layers become 0.1 μm or less. As a result, the size of the MOS field effect transistor can be reduced, and a highly integrated semiconductor device can be provided.

In each of the above embodiments, Ni and Co were selected as a combination of silicide metals. However, the present invention is not limited to the combination of these metals. Table 1 shows examples of this combination.

A combination of metals such as a silicide alloy film formed of a combination of Ni and Co (combination example A) having a low Schottky barrier height on the Si substrate side and a high heat resistance on the Si surface side, for example, combination example B , C, D, etc.
In this case, the same effect as in combination example A is expected.

The semiconductor substrate is not limited to Si, but may be another group IV semiconductor such as Ge, or a compound semiconductor such as GaAs or InP.

[Effects of the Invention] As described above, according to the present invention, it is possible to obtain a salicide structure semiconductor device including a silicide film having low contact resistivity and high heat resistance.

[Brief description of the drawings]

FIG. 1 is a process sectional view showing a MOS transistor manufacturing process according to the first embodiment, and FIG. 2 is a diagram showing N in a Ni—Co alloy silicide film.
FIG. 3 shows the distribution of i and Co elements in the depth direction, and FIG.
FIG. 4 shows the heat resistance of the alloy silicide film, FIG. 4 shows the contact resistivity of the Ni—Co alloy silicide film, and FIG.
FIG. 6 shows the Schottky barrier height of the Ni—Co alloy silicide film, FIG. 6 shows the heat resistance of the Ni—Co alloy silicide film, and FIG. 7 shows the process of manufacturing the MOS transistor of the second embodiment. FIG. 8 is a process cross-sectional view showing a manufacturing process of the MOS transistor according to the third embodiment, FIG. 9 is a schematic configuration diagram schematically showing a CVD apparatus according to the third and fourth embodiments, FIG. 10 is a diagram showing a flow rate of a source gas, FIG. 11 is a process sectional view showing a manufacturing process of the MOS transistor of the fourth embodiment, FIG. 12 is a sectional view of the MOS transistor of the fifth embodiment. FIG. 13 is a process cross-sectional view showing a manufacturing process of a conventional MOS transistor. 1 .... n-type silicon substrate, 2 .... field oxide film, 3
…… Gate oxide film, 4 …… Silicon polycrystalline layer, 5 …… Tungsten silicide (WSi _2.8 ) layer, 6,7,12 …… CVD-SiO
₂ films, 8 ...... Ni-Co alloy film, 9 ...... Ni-Co alloy silicide film, 10 ...... SiO ₂ film, 11 ₁ ...... source diffusion layer, 11 ₂ ...... drain diffusion layer, 13 ₁ ...... TiN Film, 13 ₂ … Al / Si alloy, 14
…… Ni film, 15… Co film, 16… Ni-Co laminated film, 17… Si
Layer, 18 ... tungsten electrode, 20 ... sample introduction chamber, 21 ...
... Pretreatment chamber, 22 ... Infrared lamp, 23a, 23b ... Ultraviolet lamp, 24 ... Growth chamber, 25 ... Infrared heater, 26 ... Nozzle, 27 ... Gas supply unit.

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H01L 21/28-21/288 H01L 21/336 H01L 21/44-21/445 H01L 29/40-29 / 51 H01L 29/78

Claims (2)

(57) [Claims] 1. A semiconductor substrate of a first conductivity type, an impurity layer of a second conductivity type selectively formed on a surface of the substrate, and the substrate self-aligned with the impurity layer and formed on the surface thereof. A metal compound layer containing first and second metal elements, wherein the first metal element layer includes a first metal element and a first metal element and a first metal element. The height of the Schottky barrier of the compound with respect to the substrate is lower than that of the second compound formed by the second metal element and the constituent elements of the substrate;
The first metal element and the second metal element are selected such that the melting point of the first compound is lower than that of the second compound, and the first metal element in the metal compound layer is selected. And the distribution of the second metal element is such that the first metal element is excessive at the interface side between the substrate and the metal compound layer, and that of the second metal element is on the surface side of the metal compound layer. A semiconductor device set to be excessive. 2. The semiconductor device according to claim 1, wherein said first metal element and said second metal element are selected so as to form an all-solid solution with each other.