JP2886174B2 - Method for manufacturing semiconductor device - Google Patents

Description

The present invention relates to a method for manufacturing a semiconductor device having a shallow impurity layer.

(Prior Art) In recent years, large-scale integrated circuits (LSIs) formed by integrating a large number of transistors, resistors, and the like on a semiconductor substrate have been frequently used in important parts of computers and communication devices. This L
Improving the integration degree of SI is one of the recent important issues, and it is necessary to miniaturize a basic element of LSI, for example, a field effect transistor (FET). To reduce the occupied area by shortening the gate length of the FET, it is required to form the source / drain regions shallowly so as not to change the threshold voltage. A conventional method for forming such a FET will be described with reference to FIG.

First, a field oxide film (2) is formed on an n-type silicon substrate (1) having a main surface of (100) of 4 to 5 Ωcm. A gate oxide film in a region surrounded by the oxide film (2) (3 _1),
Doped polycrystalline silicon layer (3 _2), a tungsten silicide layer (3 ₃₎ and the SiO ₂ film (3 ₄₎ is processed by etching the gate electrode shape obtained by stacking, SiO ₂ film (3 ₅ further to the side walls ) To form the gate electrode (3). After this DC
300Å Ni (4 ₁ ) over the entire surface by magnetron sputtering
It is deposited (FIG. 6 (a)).

Then 400 ° C., exposed together with the substrate into N ₂ gas at 30 min conditions, NiSi ₂ layer (5 _7), to form a (6 _7). By this heat treatment, the bottoms of the NiSi ₂ layers (5 ₇ ) and (6 ₇ ) have irregular shapes,
It comes into contact with the underlying substrate (1) over a wide area (FIG. 1 (b)).

Further, B ions are accelerated at an acceleration voltage of 10 KeV and a dose of 5 × 10
^The whole surface is implanted under the condition of ¹⁵ cm ^-2 and NiSi ₂ layer (5 ₇ )
(6 ₇₎ is contained B ion (FIG. 6 (c)).

Thereafter, 900 ° C., by exposing each substrate to N ₂ gas at 30 min conditions, NiSi ₂ layer _{(5 7), (6 7} ) P + -type layer B the underlying thermally diffused (5 ₆ ), (6 ₆₎ is formed. Thus, a source region (5) and a drain region (6) are formed, and FE
T is completed (FIG. 6 (d)).

Thus, P ⁺ -type layer (5 _6), (6 ₆₎ the low resistance NiSi ₂ layer on (5 _7), (6 ₆₎ is provided, moreover the NiSi ₂ layer (5 _7), (6 ₇ ) Is in contact with the P ⁺ -type layers (5 ₆ ) and (6 ₆ ) at the uneven bottom of a large area, so that even if the source / drain regions (5) and (6) are made thinner, Since the resistance of the FET is kept low, the structure of this FET is suitable for miniaturization.

However, NiSi ₂ layer (5 _7), after the formation of the (6 _7), and this in diffusion source, B was thermally diffused downward of the silicon substrate (1), P ⁺ -type layer (5 _7), ( to form a 6 _7), the P ⁺ -type layer is absolutely NiSi ₂ layer (5 _8), (6 ₈₎
Is formed deeper than the position. Therefore, in such a source / drain region, the total thickness of the NiSi ₂ layer as the alloy layer and the P ⁺ type layer as the impurity layer is the depth of these regions.

Therefore, in order to form these source / drain regions shallowly, the total thickness of the impurity layers of the alloy layer may be reduced, but if the thickness is further reduced, the resistance of these regions increases, and a thinner layer Conversion was extremely difficult. Unless the source / drain regions can be made thinner, high integration and high speed of the FET cannot be expected.

(Problems to be Solved by the Invention) In the conventional semiconductor device, the total thickness of the alloy layer and the impurity layer of the conductivity type provided thereunder is equal to the depth of the source / drain region, and therefore, the alloy layer is thinner than this. There is a problem that the resistance in this region becomes high.

The present invention has been made in view of the above problems, and has as its object to form a shallow impurity layer and to easily form a semiconductor device having a structure suitable for lowering resistance.

[Configuration of the invention]

(Means for Solving the Problems) In order to solve the above object, the present invention provides an alloy layer comprising a first semiconductor layer constituent element and a metal on a first semiconductor layer. The composition ratio of the first semiconductor layer constituent element is equal to the first semiconductor element in a thermal equilibrium state in the alloy layer.
A step of including an impurity exhibiting a composition ratio of the semiconductor layer constituent elements, and then, at the interface between the first semiconductor layer and the alloy layer, the first semiconductor layer constituent element and the impurity in the alloy layer. A method of manufacturing a semiconductor device, comprising the step of: depositing a second semiconductor layer containing:

Further, according to the present invention, there is provided a step of forming a first alloy layer comprising the first semiconductor layer constituent element and a metal on a first semiconductor layer, and forming the first semiconductor layer constituent element on the first alloy layer. A phase transition step of forming a second alloy layer having a large composition ratio of the first semiconductor layer constituent element, and adding an impurity exhibiting a conductivity type in the first semiconductor layer to the second alloy layer. A second element containing the first semiconductor layer constituent element component and the impurity component in the second alloy layer at an interface between the first semiconductor layer and the second alloy layer. And a reverse phase transition step of depositing the semiconductor layer.

Further, according to the present invention, a step of forming an insulating film on a silicon substrate, a step of forming a laminated film on a portion where a gate electrode is to be formed on the silicon substrate, and forming a metal silicide film on the exposed silicon substrate A step of further introducing silicon into the metal silicide film; a step of introducing an impurity exhibiting a conductivity type in silicon into the metal silicide film; Depositing the impurity-containing silicon layer from the metal silicide film.

(Operation) After forming an alloy layer on the surface of the substrate, the layer is made to have a semiconductor-rich composition, and the alloy layer is recrystallized by heat treatment. In this recrystallization process, a semiconductor to be an impurity layer is deposited on the substrate. The depth serving as the bottom of the impurity layer is provided at the same depth as the depth of the bottom of the alloy layer provided first, and is not formed deeper. When the above process is performed by intentionally adding a semiconductor component to the alloy, the total thickness of the alloy layer and the impurity layer is low because the alloy layer is formed to be higher than the alloy layer provided first. The thickness can be kept enough for

(Examples) Details of the present invention will be described along with examples.

FIG. 1 is a sectional view showing a field effect transistor according to a first embodiment of the present invention in the order of manufacturing steps.

First, a semiconductor substrate, for example, 5Ωcm with (100) as the main surface
A field oxide film (2) having a thickness of 0.6 μm is formed on the n-type silicon substrate (1) by thermal oxidation. A gate oxide film in a region to 100Å thickness surrounded by the membrane (3 _1), polycrystalline silicon (3 ₂₎ doped, tungsten silicide formed by DC magnetron sputtering (WSi _2.5) film (3 ₃₎ and 500Å thick CVD-SiO ₂ film (3 ₄₎ are sequentially laminated, and which form what was processed into a gate shape by etching. Next, using the laminated film and the field SiO ₂ film (2) as a mask, Ge ions are accelerated at 30 keV and a dose is 5 × 10 ¹⁴ cm ^−2, and BF ₂ ions are accelerated at 10 keV and a dose is 1 × 10 ¹⁴ cm. ^Under the condition of ^-2 , each is implanted into the substrate ( ₁ ) to form impurity implantation layers (5 ₁ ) and (6 ₁ ) having a thickness of 500 mm. On the side walls of the laminated film was processed into the following gate shape to form a 0.1μm thick SiO ₂ film ₍₃₅₎ (FIG. 1 (a)).

Then deposited by 1000Å thick palladium (Pd) layer (4 ₁₎ for example, a DC magnetron sputtering method (FIG. 1 (b)).

Furthermore, by performing heat treatment at 300 ° C for 30 minutes, 1400
Pd ₂ Si layer of Å thick (5 ₃₎ to form a (6 _3). (4 ₂₎ is Pd layer which did not react (FIG. 1 (c)).

Thereafter, the unreacted Pd layer (4 ₂ ) is selectively removed with a KI + I ₂ solution, and is further subjected to a heat treatment at 730 ° C. or more, for example, at 750 ° C. for 30 minutes, whereby the Pd ₂ Si layers (5 ₃ ), (6) ₃₎ PdSi layer (5 _4), (6 ₄₎ and the phase spread as made, are re-formed in the silicon-rich layer. At this time, the substrate (1) is slightly eaten and Pd
Si layer _(4), the bottom somewhat deeper (6 ₄₎ (FIG. 1 (d)).

Then, the acceleration voltage 10 keV, a dose of 1 × 10 ¹⁶ cm ^-2 at implanting B ions PiSi layer containing an impurity (5 ₅₎ to form a (6 ₅₎ (FIG. 1 (e)).

After this, heat treatment is performed at 650 ° C for 60 minutes to obtain PdS
i layer (5 _5), by reverse phase transfer (6 _5), a silicon layer (5 ₆₎ containing B, and (6 ₆₎ with deposited on a silicon substrate (1), Pd ₂ Si layer (5 ₇ ) And ( ₆₇ ). In order to cause this reverse phase transition, 600 to 700 ° C. is preferable. This allows P ⁺
The mold source region (5) and the drain region (6) are completed.
The silicon layer (5 _6), (6 ₆₎ for depositing in the seed of the silicon substrate (1), PdSi (5 _5), (6 ₅₎ and compared the shape and depth of the bottom hardly changes. The silicon layer (5 _6), (6 ₆₎ and Pd ₂ Si layer (5 _7), (6 ₇₎ interface for irregularities is in the a low resistance of the contact area is wide source and drain regions of the interlayer Suitable for. Observation of these irregularities with a microscope revealed that the depth from the peak to the valley was 100 mm or more.

Such a silicon layer (5 _6), (6 ₆₎ despite formed shallowly, Pd ₂ Si layer (5 _7), (6 ₇₎ the silicon layer so is formed raised and Pd ₂ Si The total thickness of the layers is large, and the resistance of the source / drain regions is kept low (FIG. 1 (f)).

Finally, the entire surface is made of SiO ₂ as an interlayer insulating film by CVD.
Forming a film (7), an opening is provided on the source region (5) and drain region (6), Pd ₂ Si layer (5 _7), to form an electrode wiring Al (8) leading to (6 ₇₎ Thus, the FET is completed (FIG. 1 (g)).

When the cross section of the FET thus formed was examined by an electron microscope, the depth of the intermediate concentration layers (5 ₂ ) and (6 ₂ ) was 500
And the source / drain regions (5) and (6) were formed as shallow as about 1000 ° from the surface of the n-type substrate. Like this
In the FET, the drain current can be made to flow in a shallow place of the silicon substrate (1), and the drain current can be easily controlled by the voltage applied to the gate. As a result, the gate length of 0.5 μm F
In ET, the transconductance, which was 1000ms / mm in the past, was improved to 1800ms / mm.

Wherein the second drawing PdSi layer (5 _5), (6 ₅₎ by reverse phase transition silicon layer (5 _6), Pd ₂ Si layer on (6 ₆₎ (5 _7),
Source and drain regions (6 ₇₎ was laminated structure (5),
When forming a (6), PdSi layer (5 _5), shows the relationship between the specific contact resistance of the thickness and these areas (6 _5).

Is the one in which As ions were implanted into the PiSi layer under the conditions of an acceleration voltage of 45 keV and a dose of 1 × 10 ¹⁶ cm ^-2 before the reverse phase transition.
The marks also show B ions implanted at 30 keV and 1 × 10 ¹⁶ cm ^{−2 respectively} .

As is clear from this figure, the specific contact resistance increases as the PdSi layer becomes thicker than 1100 [接触]. For this reason, the PdSi layer has a low 1100
[Å] It is preferable that:

In this embodiment, Pd is used as the metal capable of reverse phase transition, but other metals may be used. Further, here, the alloy layer is made to be silicon-rich by performing a phase transition, but in addition to this, silicon may be made into the alloy layer by performing ion implantation together with silicon-rich.

Next, a second embodiment of the present invention will be described with reference to FIG. This is different from the first embodiment in that the method of making the metal silicide layer silicon-rich and that Co is used instead of Pd.

First, through the same steps as in FIGS. 1 (a) to 1 (c), Pd
CoSi ₂ layers (5 ₃ ) and (6 ₃ ) are formed instead of the Si layer. The Co film was deposited at 3000Å using DC magnetron sputtering.
For silicidation, heat treatment was performed at 650 ° C. for 10 minutes. Unreacted Co film was selectively removed with a mixed solution of hydrogen peroxide, hydrochloric acid and water.

Next, Si ions are implanted into the CoSi ₂ layers (5 ₃ ) and (6 ₃ ) at an acceleration voltage of 20 keV and a dose of 1 × 10 ¹⁷ cm ⁻² , and silicon-rich cobalt silicide (5 ₄ ) and (6 ₄ ) Is formed (FIG. 3A).

Then silicide layer of cobalt (5 _4), the acceleration voltage 15ke (6 ₄₎
V, a dose of 1 at × 10 ¹⁶ cm ^-2 by implanting B ions, silicide cobalt layer of B-doped (5 ₅₎ to form a (6 _5). This step may be performed before the implantation of Si ions (FIG. 3B).

Furthermore, 850 ° C. in an Ar gas, B-doped silicon layer by heat treatment for 1 hour (5 _6), (6 ₆₎ with precipitating a silicon substrate (1) as a core, CoSi ₂ layer (5 _7),
To form a (6 _7). As a result, a P ⁺ type source region (5) and a drain region (6) are formed, and a shallow source / drain region similar to that of the previous embodiment is obtained (FIG. 3 (c)).

Thereafter, electrode wiring is provided in the same manner as in FIG.
Is completed. This FET is also an excellent one having characteristics similar to those of the first embodiment.

Next, a third embodiment of the present invention will be described with reference to FIG.

This embodiment differs from the above-described second embodiment in the method of making the metal silicide layer rich in silicon.

First, through the same steps as in FIGS. 1 (a) to 1 (c), CoSi
_Two layers (5 ₃₎ to form a (6 _3). In forming this film, the same conditions as in the second embodiment may be used.

Thereafter, the partial pressure of silane is 5 × 10 ^-4 Tor using the UPCVD method.
r, at a temperature of 500 ° C., 300 Å thick silicon layer (5 _9), (6 ₉₎ the CoSi ₂ layer _(3), (6 ₃₎ it is selectively formed on (FIG. 4 (a )).

Then, the silicon layer (5 _9), (6 _9), for example, B ions acceleration voltage 20 keV, injected at a dose of 1 × 10 ¹⁶ cm ^-2 (Fig. 4 (b)).

Further, by performing a heat treatment at a temperature of 850 ° C. for 1 hour in an Ar gas, the CoSo ₂ layers (5 ₃ ) and (6 ₃ ) once become silicon-rich, and excess silicon is deposited on the silicon substrate (1) by 1 ×.
It is deposited as a B-doped P-type silicon layer (5 ₆ ) and (6 ₆ ) of 10 ²⁰ cm ^-3 , and a CoSi ₂ layer (5 ₇ )
(6 ₇₎ is formed (FIG. 4 (c)).

Thereafter, through the same steps as in FIG. 1 (g), an interlayer insulating film and an electrode wiring are formed, and a P-channel FET is completed.

As with the FET also previous embodiment, P-type silicon layer (5 _7), to be formed at shallow (6 _7), having the same excellent characteristics.

Figure 5 (a) silicon layer from silicide cobalt layer (5 _6), (6 ₆₎ to precipitate the source and drain regions (5), when forming a (6), changing the composition ratio of the silicide layer of cobalt The results of measuring the specific contact resistance of these regions are shown below. − ○-mark indicates BF ₂ ions on cobalt silicide layer at accelerating voltage 4
0 keV, implanted at a dose of 1 × 10 ¹⁶ cm ^-2 , In the same manner, each shows the measurement results obtained when As ions were implanted at 50 keV and 1 × 10 ¹⁶ cm ⁻² . As is clear from this figure, the Si
The specific contact resistance increases as / Co exceeds 2.5. Therefore, to provide a shallow and low-resistance source / drain region from a silicon-rich cobalt silicide layer, Si / C
It turned out that o is 2 or more and 2.5 or less is preferable.

In the present invention, Ni can be used instead of Pd or Co. FIG. 5 (b) shows a measurement result similar to that shown in FIG. 5 (a) when an FET is provided using a nickel silicide layer instead of cobalt silicide. As is clear from this figure,
It has been found that also in the case of a silicon-rich nickel silicide layer, the Si / Ni ratio is preferably 2 or more and 2.5 or less.

In the above embodiments, the MOS type FET has been described. However, the present invention can be applied to other FETs, such as a Schottky gate type FET, and further, an element requiring a shallow diffusion layer other than the FET, such as a Pn junction diode or a bipolar transistor. Also available. Here, silicon is used for the substrate, but germanium or a compound semiconductor such as GaAs or InP may be used. As the metal, W or Ti may be used in addition to Pd or Co.

It is needless to say that the present invention is not limited to the above-described embodiment, and cannot be carried out with various modifications without departing from the gist of the present invention.

〔The invention's effect〕

According to the present invention, a semiconductor device having a shallow impurity layer and having a structure suitable for lowering resistance can be easily formed.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a first embodiment of the present invention in the order of steps,
FIG. 2 is a view for explaining a first embodiment of the present invention, FIG. 3 is a sectional view showing a second embodiment of the present invention in the order of steps, and FIG. 4 is a view showing a third embodiment of the present invention. FIG. 5 is a view for explaining the second and third embodiments of the present invention, and FIG. 6 is a cross-sectional view for showing a conventional example in the order of steps. DESCRIPTION OF SYMBOLS 1 ... Silicon substrate, 2 ... Field oxide film 3 ... Gate region 4, ... Metal layer 5 ... Source region, 6 ... Drain region 7 ... Interlayer insulating film, 8 ... Electrode wiring

Claims (5)

(57) [Claims] An alloy layer comprising a first semiconductor layer constituent element and a metal is provided on a first semiconductor layer, and a composition ratio of the first semiconductor layer constituent element in the alloy layer is set in the alloy layer. Forming the first semiconductor layer so as to have a composition ratio larger than the composition ratio of the first semiconductor layer constituent elements in a thermal equilibrium state; and causing the alloy layer to contain an impurity exhibiting a conductivity type in the first semiconductor layer. Depositing a second semiconductor layer containing the first semiconductor layer constituent element and the impurity in the alloy layer at an interface between the first semiconductor layer and the alloy layer. A method for manufacturing a semiconductor device. 2. A step of forming a first alloy layer comprising the first semiconductor layer constituent element and a metal on a first semiconductor layer; and forming the first semiconductor layer constituent element on the first alloy layer. A phase transition step of forming a second alloy layer having a large composition ratio of the first semiconductor layer constituent element, and adding an impurity exhibiting a conductivity type in the first semiconductor layer to the second alloy layer. And a second step including the first semiconductor layer constituent element component and the impurity component from the second alloy layer at an interface between the first semiconductor layer and the second alloy layer. A method for manufacturing a semiconductor device, comprising: a reverse phase transition step of depositing and forming a semiconductor layer. 3. The method according to claim 2, wherein the step of forming the second alloy layer is performed by ion-implanting a constituent element of the first semiconductor layer into the first alloy layer. The manufacturing method of the semiconductor device described in the above. 4. A step of selectively forming an insulating film on a silicon substrate, a step of forming a laminated film on a portion where a gate electrode is to be formed on the silicon substrate, and a step of forming a metal silicide film on the exposed silicon substrate. Forming a silicon nitride film, introducing silicon into the metal silicide film, introducing an impurity exhibiting a conductivity type in silicon into the metal silicide film, and then forming the silicon substrate and the metal silicide Depositing a silicon layer containing the impurity from the metal silicide film at an interface with the film. 5. The method according to claim 4, wherein the metal is Co or Ni, and the composition ratio of silicon to metal in the metal silicide film further doped with silicon is 2 to 2.5.
13. The method for manufacturing a semiconductor device according to item 5.