JPH047094B2 - - Google Patents
Info
- Publication number
- JPH047094B2 JPH047094B2 JP19857082A JP19857082A JPH047094B2 JP H047094 B2 JPH047094 B2 JP H047094B2 JP 19857082 A JP19857082 A JP 19857082A JP 19857082 A JP19857082 A JP 19857082A JP H047094 B2 JPH047094 B2 JP H047094B2
- Authority
- JP
- Japan
- Prior art keywords
- melting point
- point metal
- forming
- high melting
- insulating film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000010408 film Substances 0.000 claims description 36
- 229910052751 metal Inorganic materials 0.000 claims description 32
- 239000002184 metal Substances 0.000 claims description 32
- 229910052710 silicon Inorganic materials 0.000 claims description 32
- 239000010703 silicon Substances 0.000 claims description 32
- 238000002844 melting Methods 0.000 claims description 31
- 230000008018 melting Effects 0.000 claims description 30
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 29
- 229910021332 silicide Inorganic materials 0.000 claims description 28
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 27
- 238000000034 method Methods 0.000 claims description 17
- 239000000758 substrate Substances 0.000 claims description 15
- 238000010438 heat treatment Methods 0.000 claims description 14
- 239000002019 doping agent Substances 0.000 claims description 10
- 150000002500 ions Chemical class 0.000 claims description 7
- 239000004065 semiconductor Substances 0.000 claims description 5
- 239000012535 impurity Substances 0.000 claims description 4
- 239000003870 refractory metal Substances 0.000 claims description 3
- 239000010409 thin film Substances 0.000 claims description 3
- 239000013078 crystal Substances 0.000 claims 1
- 239000010410 layer Substances 0.000 description 24
- 238000009792 diffusion process Methods 0.000 description 17
- 238000004519 manufacturing process Methods 0.000 description 11
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 10
- 229910052698 phosphorus Inorganic materials 0.000 description 9
- 239000011574 phosphorus Substances 0.000 description 9
- 238000005468 ion implantation Methods 0.000 description 8
- 239000011521 glass Substances 0.000 description 7
- 229910052750 molybdenum Inorganic materials 0.000 description 7
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 6
- 239000011733 molybdenum Substances 0.000 description 6
- -1 arsenic Chemical class 0.000 description 5
- 229910016006 MoSi Inorganic materials 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 4
- 239000011229 interlayer Substances 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 238000006243 chemical reaction Methods 0.000 description 3
- 238000005243 fluidization Methods 0.000 description 3
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 238000010561 standard procedure Methods 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 description 1
- 108010075750 P-Type Calcium Channels Proteins 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
- H01L21/76889—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances by forming silicides of refractory metals
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Electrodes Of Semiconductors (AREA)
Description
【発明の詳細な説明】
本発明はシリコン半導体装置の製造方法に関す
るものである。シリコン集積回路におけるパター
ンの微細化とチツプ寸法の拡大により、シリコン
基板表面層に高濃度にドーパントを導入すること
により形成されたいわゆる拡散層の抵抗が無視し
得なくなつてきた。拡散層を低抵抗化する方法と
して、拡散層表面に金属シリサイドを形成する方
法が知られている。特に、モリブデン、タングス
テンやチタン等の高融点金属シリサイドは1000℃
程度の高温熱処理にも耐えることや熱酸化により
表面に酸化膜を形成できる等の理由により注目さ
れている。高融点金属シリサイドを所定の開口部
にのみ選択的かつ自己整合的に形成することが、
デバイス製造への応用上極めて望ましい。高融点
金属とシリコンとの反応によりシリサイドを形成
する方法は、原理的にはその目的に合致するが、
シリコン上に推積された高融点金属とシリコンと
の単に熱処理のみによる反応ではシリサイド化反
応の再現性が悪くかつ形成された高融点金属シリ
サイドの均一性も悪いという問題があり、実用に
は適さない。熱処理前に高融点金属とシリコンと
の界面をイオン注入により混合させておくと、そ
の後の熱処理によつて均一でかつピンホールの無
い高融点金属シリサイド膜をシリコン開口部に自
己整合的に再現性よく形成し得ることが知られて
いる。特に砒素等のドーパントイオン注入によつ
て界面混合を行う場合には、シリサイド形成に対
する上述の効果の他に、シリサイド層直下にシリ
サイドに自己整合的に拡散層を形成し得るという
利点がある。しかし、界面混合によつて均一なシ
リサイドを形成するためのイオン注入濃度は、ほ
ぼ単結晶シリコンを非結晶化するのに必要な注入
量以上が必要であり、そのために単結晶シリコン
基板中にイオン注入によつて形成された損傷の回
復には900〜1000℃程度の高温熱処理が必要であ
る。しかしその様な高温熱処理を行うと、イオン
注入によつてシリサイド層に接して形成された拡
散層のドーパントが拡散して接合深さの増大を引
起す結果微細デバイス製造には適さなくなるとい
う問題が生じる。更に、その後に層間絶縁膜の平
坦化のために行われる900〜1000℃のリンガラス
流動化の熱処理によつてもドーパントの拡散が生
じるので、リンガラス流動化を行えないという問
題も生じる。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a silicon semiconductor device. With the miniaturization of patterns and the expansion of chip dimensions in silicon integrated circuits, the resistance of so-called diffusion layers formed by introducing dopants at high concentrations into the surface layer of silicon substrates has become impossible to ignore. A known method for reducing the resistance of a diffusion layer is to form metal silicide on the surface of the diffusion layer. In particular, high melting point metal silicides such as molybdenum, tungsten and titanium are heated to 1000℃.
It is attracting attention because it can withstand high-temperature heat treatment and can form an oxide film on its surface through thermal oxidation. Forming high melting point metal silicide selectively and self-aligned only in predetermined openings
Extremely desirable for application to device manufacturing. Although the method of forming silicide through the reaction of a high-melting point metal and silicon meets the purpose in principle,
The reaction between a high melting point metal deposited on silicon and silicon by simply heat treatment has the problem of poor reproducibility of the silicidation reaction and poor uniformity of the formed high melting point metal silicide, making it unsuitable for practical use. do not have. If the interface between the high melting point metal and silicon is mixed by ion implantation before heat treatment, a uniform and pinhole-free high melting point metal silicide film can be reproducibly formed in the silicon opening in a self-aligned manner by subsequent heat treatment. It is known that it can be easily formed. In particular, when interfacial mixing is performed by implanting dopant ions such as arsenic, in addition to the above-mentioned effect on silicide formation, there is an advantage that a diffusion layer can be formed directly under the silicide layer in a self-aligned manner with the silicide. However, the ion implantation concentration required to form uniform silicide through interfacial mixing is approximately higher than the implantation amount required to amorphize single-crystal silicon. High-temperature heat treatment of approximately 900 to 1000°C is required to recover from damage caused by implantation. However, when such high-temperature heat treatment is performed, the dopant in the diffusion layer formed in contact with the silicide layer by ion implantation diffuses and increases the junction depth, making it unsuitable for manufacturing fine devices. arise. Furthermore, dopant diffusion also occurs during the subsequent heat treatment for phosphorus glass fluidization at 900 to 1000° C. for flattening the interlayer insulating film, resulting in the problem that phosphorus glass fluidization cannot be performed.
本発明の目的は、上記従来法の問題点を解決し
た新規なシリコン半導体装置の製造方法、特に高
融点金属シリサイドを表面に形成した浅い拡散層
の形成方法を提供することである。 An object of the present invention is to provide a novel method for manufacturing a silicon semiconductor device that solves the problems of the conventional methods described above, particularly a method for forming a shallow diffusion layer with a high melting point metal silicide formed on the surface.
本発明によればシリコン半導体基板上に絶縁膜
を形成する工程と、該絶縁膜に開口を設けシリコ
ン基板表面の所定の領域を露出させた後高融点金
属薄膜を形成する工程と、シリコン結晶中で電気
的に不活性なイオンを高融点金属とシリコン表面
との界面にイオン注入することにより該界を混合
した後熱処理により前記絶縁膜の開口部において
高融点金属とシリコン基板とを反応させることに
より高融点金属シリサイドを前記開口部に自己整
合的に形成する工程と、絶縁膜上の未反応な高融
点金属を除去する工程と、少くとも該高融点金属
シリサイド上に絶縁膜を形成した後該絶縁膜の一
部に開口を設けて該開口部の絶縁膜を薄くするか
又は除去する工程と、該開口より高融点金属シリ
サイドを通じてドーパント不純物を横方向にも拡
散させることにより高融点金属シリサイドとシリ
コン基板との界面に接した領域のシリコン中にド
ーピング層を形成する工程とを含むことを特徴と
する半導体装置の製造方法が得られる。 According to the present invention, there are a step of forming an insulating film on a silicon semiconductor substrate, a step of forming a high melting point metal thin film after forming an opening in the insulating film and exposing a predetermined region of the surface of the silicon substrate, and After mixing the field by implanting electrically inert ions into the interface between the high melting point metal and the silicon surface, the high melting point metal and the silicon substrate are reacted at the opening of the insulating film by heat treatment. a step of forming a high melting point metal silicide in the opening in a self-aligned manner, a step of removing unreacted high melting point metal on the insulating film, and at least after forming an insulating film on the high melting point metal silicide. A step of forming an opening in a part of the insulating film and thinning or removing the insulating film in the opening, and also diffusing the dopant impurity laterally through the opening through the high melting point metal silicide. and forming a doped layer in silicon in a region in contact with an interface with a silicon substrate.
本発明による方法は、本発明が見出したシリコ
ン基板表面に形成した高融点金属シリサイド膜を
通してのドーパントの著しい横方向拡散作用を利
用したものである。本発明の方法では、高融点金
属シリサイドに接する拡散層の形成は、イオン注
入による界面混合を用いた高融点金属シリサイド
の形成後、更には層間絶縁膜の形成後にも行える
という画期的な特長を有する。従つて、本発明に
よる方法においては、高融点金属とシリコンの界
面混合のために用いるイオン注入は単に界面混合
のためのみ用いるので、シリコン等の電気的に不
活性なイオンを用いて行え、かつイオン注入によ
つて生じる損傷を充分に回復させるための熱処理
や層間絶縁層としてのリンガラス層の流動化温度
を1000℃程度の高温にしても高融点金属シリサイ
ド層下には拡散層がまだ形成されていないので全
く問題を引起さない。従つて、本発明による方法
を用いれば、すべての高温熱処理（900〜1000℃）
を行つた後に高融点金属シリサイドに接する領域
に極めて浅い拡散層を形成することが可能とな
り、微細デバイスを用いた超高密度集積回路を製
造する上での効果は極めて大きい。 The method according to the present invention utilizes the remarkable lateral diffusion effect of a dopant through a high melting point metal silicide film formed on the surface of a silicon substrate, which has been discovered by the present invention. The method of the present invention has the revolutionary feature that the formation of the diffusion layer in contact with the high melting point metal silicide can be performed after the formation of the high melting point metal silicide using interfacial mixing by ion implantation, and even after the formation of the interlayer insulating film. has. Therefore, in the method according to the present invention, the ion implantation used for interfacial mixing of the high melting point metal and silicon is used only for interfacial mixing, so it can be performed using electrically inactive ions such as silicon, and Even if heat treatment is used to fully recover the damage caused by ion implantation, and the fluidization temperature of the phosphor glass layer as an interlayer insulating layer is raised to a high temperature of approximately 1000°C, a diffusion layer still forms under the high melting point metal silicide layer. Since it has not been done yet, it does not cause any problems. Therefore, using the method according to the invention, all high-temperature heat treatments (900-1000°C)
After performing this, it becomes possible to form an extremely shallow diffusion layer in the region in contact with the high melting point metal silicide, which is extremely effective in manufacturing ultra-high density integrated circuits using microscopic devices.
次に第１図を用いて本発明による方法を詳細に
説明する。ｎチヤネルMOS集積回路における
MOSFET製造に本発明による方法を適用した場
合の主要な製造工程におけるMOSFETの概略断
面を第１図ａ〜ｉに順次示す。先ず第１図ａに示
した様に、標準的な方法を用いてｐ型単結晶シリ
コン基板１の主平面上にフイールド酸化膜２とゲ
ート酸化膜３を形成した後、リンをドープした多
結晶シリコン膜４推積する。次にリンドープ多結
晶シリコン膜４を標準的なホトエツチング技術に
よりパターニングし、ゲート電極５を形成する
（ｂ図）。次に該ゲート電極５をマスクとしてソー
ス・ドレインや拡散層配線となるべき部分６，７
のゲート酸化膜を除去して開口を設けた（ｃ図）、
後、ｄ図に示した様に200Åのモリブデン膜８を
スパツタし、更に50kevのシリコンイオン９を５
×1015-2だけイオン注入することによりモリブデ
ン薄膜８とシリコン基板１との界面を混合させ
る。次に550℃で20分間熱処理することによりｅ
図に示した如く開口部及び多結晶シリコンパター
ン表面上にMoSi2層１０，１１を形成し、続いて
フイールド酸化膜上の未反応モリブデン８を選択
的に除去する（ｆ図）。モリブデンの選択エツチ
ングは、過酸化水素水等を用いることにより容易
に行える。次にイオン注入による損傷の回復と
MoSi2膜の電気抵抗を下げるために1000℃で熱処
理を行つた後、層間絶縁膜としてリンガラス膜１
２を化学蒸着法により堆積した後、950℃の熱処
理によりリンガラス流動化を行い段差平滑化を図
る（ｇ図）。次にｈ図に示した様にリンガラス層
１２にコンタクトホール１３を開口し、該コンタ
クトホール１３よりリンを900℃で拡散すること
によりコンタクトホール下のMoSi2層１０に接す
るシリコン領域に極めて浅いリン拡散層１４を形
成する。本実施例においてはMoSi2P層１０，１
１表面からリン拡散Ｐ層１４の底面までの深さは
約0.1μｍであつた。次にｉ図に示す様に標準的な
方法でアルミニウム系配線・コンタクト１５を形
成することにより主要なデバイス製造工程が終
る。本実施例ではモリブデン膜とシリコン基板の
界面を混合させるためシリコンのイオン注入を行
なつたが、アルゴン等の不活性元素をイオン注入
してもよい。 Next, the method according to the present invention will be explained in detail using FIG. In n-channel MOS integrated circuits
Schematic cross-sections of a MOSFET in main manufacturing steps when the method according to the present invention is applied to MOSFET manufacturing are sequentially shown in FIGS. 1a to 1i. First, as shown in FIG. 1a, a field oxide film 2 and a gate oxide film 3 are formed on the main plane of a p-type single crystal silicon substrate 1 using a standard method, and then a phosphorus-doped polycrystalline film is formed. A silicon film 4 is estimated. Next, the phosphorus-doped polycrystalline silicon film 4 is patterned by standard photoetching techniques to form a gate electrode 5 (FIG. b). Next, using the gate electrode 5 as a mask, the portions 6 and 7 that are to become source/drain and diffusion layer wiring are
The gate oxide film was removed to create an opening (Figure c).
After that, as shown in figure d, a 200 Å molybdenum film 8 is sputtered, and 50 kev silicon ions 9 are further sputtered.
The interface between the molybdenum thin film 8 and the silicon substrate 1 is mixed by implanting ions by ×10 15 -2 ions. Next, by heat treatment at 550℃ for 20 minutes,
As shown in the figure, MoSi 2 layers 10 and 11 are formed on the openings and the surface of the polycrystalline silicon pattern, and then unreacted molybdenum 8 on the field oxide film is selectively removed (Figure f). Selective etching of molybdenum can be easily performed using a hydrogen peroxide solution or the like. Next, repair the damage caused by ion implantation and
After heat treatment at 1000℃ to lower the electrical resistance of the MoSi 2 film, a phosphorus glass film 1 was added as an interlayer insulating film.
After depositing 2 by chemical vapor deposition, phosphorus glass is fluidized by heat treatment at 950°C to smooth out the steps (Figure g). Next, as shown in figure h, a contact hole 13 is opened in the phosphorus glass layer 12, and phosphorus is diffused through the contact hole 13 at 900°C to form an extremely shallow layer in the silicon region in contact with the MoSi 2 layer 10 below the contact hole. A phosphorus diffusion layer 14 is formed. In this example, MoSi 2 P layers 10, 1
The depth from the 1 surface to the bottom of the phosphorus-diffused P layer 14 was about 0.1 μm. Next, as shown in Figure i, the main device manufacturing process is completed by forming aluminum wiring/contacts 15 using a standard method. In this embodiment, silicon ions were implanted to mix the interface between the molybdenum film and the silicon substrate, but ions of an inert element such as argon may also be implanted.
また本実施例においては、高融点金属シリサイ
ドを通してのドーパントの横方向拡散法として通
常の熱拡散を用いたが、熱拡散源としてリンドー
プ多結晶シリコンを用いることもできるし、更に
は、イオン注入によつてドーパント不純物を開口
部の高融点金属シリサイド中に高濃度に導入して
から熱拡散させることもできる。イオン注入を用
いた場合は開口部においてシリサイドを露出させ
ず絶縁膜をうすく残してもよい。 Furthermore, in this example, normal thermal diffusion was used as the lateral diffusion method of the dopant through the refractory metal silicide, but phosphorus-doped polycrystalline silicon can also be used as the thermal diffusion source. Therefore, it is also possible to introduce the dopant impurity into the refractory metal silicide in the opening at a high concentration and then thermally diffuse it. When ion implantation is used, a thin insulating film may be left in the opening without exposing the silicide.
また、ドーパント不純物としてｐ型のボロンを
用いることにより、ｐ型チヤネルMOSFET製造
にも本発明による方法が効果的に適用できた。ま
た高融点金属としてはMo以外にＷ、Ta、Ti等
も使うことができた。 Furthermore, by using p-type boron as a dopant impurity, the method according to the present invention could be effectively applied to the manufacture of p-type channel MOSFETs. In addition to Mo, W, Ta, Ti, etc. could also be used as high melting point metals.
第１図は本発明による方法をMOS集積回路の
製造に適用した場合におけるMOSFET部での主
要製造工程に対する概略断面図である。図中の番
号は以下のものを示している。
１……単結晶シリコン基板、２……フイールド
酸化膜、３……ゲート酸化膜、５……多結晶シリ
コンゲート、８……高融点金属膜、９……シリコ
ンイオン、１０，１１……高融点金属シリサイ
ド、１２……リンガラス、１４……リン拡散層。
FIG. 1 is a schematic cross-sectional view of the main manufacturing steps in a MOSFET section when the method according to the present invention is applied to manufacturing a MOS integrated circuit. The numbers in the figure indicate the following. 1... Single crystal silicon substrate, 2... Field oxide film, 3... Gate oxide film, 5... Polycrystalline silicon gate, 8... High melting point metal film, 9... Silicon ion, 10, 11... High Melting point metal silicide, 12...phosphorus glass, 14... phosphorus diffusion layer.
Claims (1)
程と、該絶縁膜に開口を設けシリコン基板表面の
所定の領域を露出させた後、高融点金属薄膜を形
成する工程と、シリコン結晶中で電気的に不活性
なイオンを高融点金属とシリコン基板表面との界
面にイオン注入することにより該界面を混合した
後熱処理により前記絶縁膜の開口部において高融
点金属とシリコン基板とを反応させることにより
高融点金属シリサイドを前記開口部に自己整合的
に形成する工程と、絶縁膜上の未反応な高融点金
属を除去する工程と、少なくとも該高融点金属シ
リサイド上に絶縁膜を形成した後該絶縁膜の一部
に開口を設けて該開口部の絶縁膜を薄くするか又
は除去する工程と、該開口より高融点金属シリサ
イドを通じてドーパント不純物を横方向にも拡散
させることにより高融点金属シリサイドとシリコ
ン基板との界面に接した領域のシリコン中のドー
ピング層を形成する工程とを含むことを特徴とす
る半導体装置の製造方法。1. A process of forming an insulating film on a silicon semiconductor substrate, a process of forming a refractory metal thin film after forming an opening in the insulating film and exposing a predetermined region of the surface of the silicon substrate, and a process of forming an electrically conductive film in a silicon crystal. After mixing the interface by implanting inert ions into the interface between the high melting point metal and the silicon substrate surface, heat treatment is performed to cause the high melting point metal and the silicon substrate to react at the opening of the insulating film. a step of forming a melting point metal silicide in the opening in a self-aligned manner; a step of removing unreacted high melting point metal on the insulating film; and after forming an insulating film on at least the high melting point metal silicide, the insulating film A process of forming an opening in a part of the opening and thinning or removing the insulating film in the opening, and also diffusing the dopant impurity laterally through the opening through the high melting point metal silicide, thereby removing the high melting point metal silicide and the silicon substrate. forming a doped layer in silicon in a region in contact with an interface with a semiconductor device.
Priority Applications (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19857082A JPS5988868A (en) | 1982-11-12 | 1982-11-12 | Manufacture of semiconductor device |
| US06/550,913 US4558507A (en) | 1982-11-12 | 1983-11-10 | Method of manufacturing semiconductor device |
| EP83111366A EP0109082B1 (en) | 1982-11-12 | 1983-11-14 | Method of manufacturing a semiconductor device comprising a diffusion step |
| DE8383111366T DE3381880D1 (en) | 1982-11-12 | 1983-11-14 | METHOD FOR PRODUCING A SEMICONDUCTOR ARRANGEMENT WITH A DIFFUSION STEP. |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19857082A JPS5988868A (en) | 1982-11-12 | 1982-11-12 | Manufacture of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5988868A JPS5988868A (en) | 1984-05-22 |
| JPH047094B2 true JPH047094B2 (en) | 1992-02-07 |
Family
ID=16393375
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19857082A Granted JPS5988868A (en) | 1982-11-12 | 1982-11-12 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5988868A (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07120672B2 (en) * | 1986-01-28 | 1995-12-20 | 日本電気株式会社 | Semiconductor device |
| JPH0685320B2 (en) * | 1989-10-31 | 1994-10-26 | シャープ株式会社 | Battery storage mechanism for electronic devices |
| JP2606954B2 (en) * | 1990-08-30 | 1997-05-07 | シャープ株式会社 | Battery storage structure |
-
1982
- 1982-11-12 JP JP19857082A patent/JPS5988868A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5988868A (en) | 1984-05-22 |
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