JPH08204193A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE: To prevent short circuit between a gate electrode and a source.drain region, in a salicide method. CONSTITUTION: After a side wall 209 of a silicon nitride film is formed on the side surface of a protruding pattern composed of a gate oxide film 204, a polycrystalline silicon gate electrode 205 and a PSG film pattern 206, the PSG film pattern 206 is eliminated, and the side wall 209 which protrudes higher than the polycrystalline silicon gate electrode 205 is left. A titanium film 211 is deposited, heat treatment at 450-550 deg.C is performed for 5-10 minutes by using a heating furnace, and a silicide layer 212 is formed on the surface of the polycrystalline silicon gate electrode 205 and the surface of a source.drain region. In this case, the side wall 209 protruding higher than the polycrystalline silicon gate electrode 205 restrains the short circuit between the source.drain region and the gate electrode in a silicification process.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a MOS type semiconductor device, and more particularly to a method for manufacturing a semiconductor device having a silicided gate electrode and source / drain regions.

[0002]

2. Description of the Related Art As semiconductor devices are highly integrated and patterns are made finer, there is a demand for lower resistance of gate electrodes. SALI as a method to reduce the resistance of the gate electrode
A method of siliciding a gate electrode by a CIDE (Self-Aligned Silicide) technique is known.

FIG. 1 shows a step of siliciding the gate electrode and the source / drain regions by using the SALICIDE process. (A) A gate oxide film 102 on a silicon substrate 101 and a polycrystalline silicon film 10 whose resistance is lowered by introducing impurities.
3 is formed, a silicon oxide film is deposited on the substrate including the gate electrode, and the oxide film is etched back to form the sidewall 104 on the side surface of the gate electrode.

(B) Next, an electrode material metal film 105 is deposited on the entire surface. (C) Then, by performing heat treatment,
Drain region and polycrystalline silicon film 103 and metal film 10
The inter-diffusion between 5 is performed to form the silicide layer 106. (D) When the metal film 105 other than the silicide layer 106 is removed by etching, a silicided source / drain region and a silicided gate electrode are obtained.

When forming a silicide layer on the gate electrode by the method of FIG. 1, it is known that the reaction rate of silicidation becomes slow when the impurity concentration of the polycrystalline silicon film 103 is high. Therefore, if the heat treatment time is extended to form a silicide layer having a sufficient thickness on the gate electrode, diffusion of silicon from the source / drain regions occurs also in the metal film on the sidewall 104. Source·
It is said that a short circuit may occur between the drain region and the gate electrode, and it is difficult to further reduce the resistance of the gate electrode.

Therefore, in the step of FIG. 1B, the metal film 10 is formed.
After forming No. 5, a focused ion beam is used to selectively implant silicon ions only into the metal film of the gate electrode portion to form a silicide layer having a sufficient thickness on the gate electrode in a short heat treatment time. , A method of preventing a short circuit between the source / drain region and the gate electrode has been proposed (see Japanese Patent Publication No. 4-57095).

[0007]

In the method of the reference, a focused ion beam is used to implant silicon ions only on the metal film in the gate electrode portion. However, it is technically difficult to implant ions into the miniaturized gate electrode with high accuracy, and even if the focused ion beam can be controlled to perform accurate ion implantation, it is possible to increase the size of the wafer to be enlarged. It takes a very long time to process the entire surface, which is not practical. The invention is SALICI
A method of forming a silicide layer on the gate electrode and the source / drain region by the DE method, which aims to prevent short circuit between the source / drain region and the gate electrode and to enable processing in a practical time. It is a thing.

[0008]

The first aspect of the method of the present invention includes the following steps (A) to (D).
(A) A gate insulating film is formed in an element forming region of a semiconductor substrate, a polycrystalline silicon film is formed on the gate insulating film, and a silicon oxide film is further formed on the gate insulating film. Then, the polycrystalline silicon film and the silicon oxide film are removed. Patterning to form a gate electrode, (B) forming a silicon nitride film on the surface of the substrate including the gate electrode, anisotropically etching the silicon nitride film, and forming the silicon nitride film only on the side of the gate electrode. And (C) removing the silicon oxide film by etching to expose the surface of the polycrystalline silicon film of the gate electrode, and (D) forming a refractory metal film on the substrate surface including the gate electrode, and performing heat treatment. Is performed to silicidize the refractory metal film in contact with the silicon of the semiconductor substrate and the polycrystalline silicon film of the gate electrode, and then the portion other than the silicided part of the refractory metal film is etched. Removing the ring.

It is preferable that the silicon oxide film formed on the polycrystalline silicon film in the step (A) has impurities added thereto. In that case, in the subsequent heat treatment step, the impurity can be diffused into the polycrystalline silicon film of the gate electrode to reduce the resistance of the polycrystalline silicon film of the gate electrode.

Another aspect of the present invention includes the following steps (A) to (C). (A) A gate insulating film is formed in an element forming region of a semiconductor substrate, a polycrystalline silicon film is formed on the gate insulating film, a refractory metal film is further formed on the gate insulating film, and a polycrystalline film is further formed on the refractory metal film. After forming the silicon film,
Forming a gate electrode by patterning the uppermost polycrystalline silicon film, the refractory metal film thereunder, and the lowermost polycrystalline silicon film; and (B) forming an insulating film on the substrate surface including the gate electrode. , A step of anisotropically etching the insulating film to leave the insulating film only on the side of the gate electrode,
(C) After forming a refractory metal film on the surface of the substrate including the gate electrode and performing heat treatment to silicify the refractory metal film in contact with the semiconductor substrate silicon and the polycrystalline silicon film of the gate electrode, A step of removing portions other than the silicided portion of the metal film by etching.

Still another embodiment of the present invention includes the following steps (A) to (C). (A) A gate insulating film is formed in an element forming region of a semiconductor substrate, a polycrystalline silicon film is formed thereon, and then a refractory metal is ion-implanted into the polycrystalline silicon film. Patterning the silicon film to form a gate electrode,
(B) forming an insulating film on the surface of the substrate including the gate electrode,
A step of anisotropically etching the insulating film to leave the insulating film only on the side of the gate electrode, (C) forming a refractory metal film on the surface of the substrate including the gate electrode, and performing heat treatment on the semiconductor substrate. After silicidizing the refractory metal film in contact with silicon and the polycrystalline silicon film of the gate electrode,
A step of etching away the portion of the refractory metal film other than the silicided portion.

The refractory metal film is preferably molybdenum, tantalum, tungsten, or titanium. This is because these refractory metal films can be easily removed by wet etching. Molybdenum, tantalum, tungsten, or titanium can also be used as the ion-implanted refractory metal. Of these, titanium, which has the smallest mass number, is convenient because a simple device can be used as an ion implanter.

[0013]

Embodiment An embodiment corresponding to claim 1 will be described with reference to FIG. (A) The channel stopper region 20 is formed by selectively ion-implanting boron, which is a P-type impurity, into the P-type silicon substrate 201.
After forming 2, the field oxide film 203 is formed on the channel stopper region by the selective oxidation method. Subsequently, a thermal oxidation process is performed to form the silicon substrate 201 in the element formation region.
Approximately 10 nm of thermal oxide film 204 to be a gate oxide film on the surface
Grow to a thickness of. A polycrystalline silicon film 205 is deposited on the entire surface of the gate oxide film 204 to a thickness of about 500 nm, and a PSG film (phosphorus-doped glass film) 206 is deposited on the polycrystalline silicon film 205 to a thickness of about 500 nm.
To a thickness of.

Then, the laminated film is patterned by photolithography and reactive ion etching to form a convex pattern composed of the gate oxide film 204, the polycrystalline silicon gate electrode 205 thereon and the PSG film pattern 206 thereon. Form. Using the convex pattern and the field oxide film 203 as a mask, the silicon substrate 201 is ion-implanted with phosphorus, which is an N-type impurity. Ion implantation at this time is performed by LDD (Lightly Doped) in the source / drain regions.
This is for forming a low-concentration region of the Drain structure, and the conditions are as follows: implantation energy is 85 to 95 KeV, and dose is 2.0 × 10 ^{13 to} 2.5 × 10 ¹³ / cm ² .

(B) Heat treatment is performed to form a thermal oxide film (not shown) of about 10 nm on the exposed silicon substrate 201, and then heat treatment is performed in an inert gas atmosphere to implant the silicon substrate 201. Activated phosphorus to form an N ⁻ region 207 having a shallow junction depth. The PSG film 20 is formed on the polycrystalline silicon film 205 to be the gate electrode by these heat treatments.
Phosphorus diffuses from 6 and becomes an N-type polycrystalline silicon gate electrode. Then, a silicon nitride film 208 is deposited on the entire surface by CVD to a thickness of about 100 nm.

(C) The silicon nitride film 208 is etched by reactive ion etching to leave the sidewalls 209 of the silicon nitride film on the side surfaces of the polycrystalline silicon gate electrode 205 and the PSG film 206.

(D) Next, the PSG film 206 is removed by etching. By this processing, the silicon nitride film sidewall 209 has a shape protruding higher than the height of the polycrystalline silicon gate electrode 205, and this serves to suppress a short circuit between the source / drain region and the gate electrode in the subsequent silicidation process. . After that, the polycrystalline silicon gate electrode 205 and the silicon nitride film sidewall 2
09 and the field oxide film 203 as a mask, arsenic, which is an N-type impurity, is ion-implanted into the silicon substrate 201 to form a high concentration source / drain N ⁺ region 210 having a deeper junction than the N ⁻ region 207. Form. The ion implantation condition at this time is that the implantation energy is 45 to 55 Ke.
V, the dose amount is 5 × 10 ^{15 to} 6 × 10 ¹⁵ / cm ² .

(E) Next, a titanium film 211 as a refractory metal forming a silicide layer is deposited to a thickness of 50 to 100 nm by means such as a sputtering method.

(F) Subsequently, heat treatment is performed in a heating furnace at a temperature of 450 to 550 ° C. for 5 to 10 minutes to form silicon and titanium films 211 on the surface of the polycrystalline silicon gate electrode 205 and the source / drain region surface. Interdiffusion is performed between them to form a silicide layer 212. Next, the unreacted titanium film 211 is removed with a mixed solution of (ammonia water + hydrogen peroxide solution + pure water) which is an etching solution for titanium. As a result, the silicide layer 212 remains only on the surface of the source / drain region 210 and the surface of the polycrystalline silicon gate electrode 205.

In the embodiment of FIG. 2, even if a BPSG film (boron phosphorus added glass film) or a BSG film (boron added glass film) is used in place of the PSG film 206 in the step (A), the polycrystalline silicon film 205 is used. The purpose of lowering the resistance can be achieved. In the embodiment of FIG. 2, as shown in (F), the protruding portions of the sidewalls 209 remain, but this is not a problem because they are covered by the interlayer insulating film in the subsequent wiring process. If the protrusion of the sidewall 209 becomes a problem, the height of the protrusion of the sidewall 209 may be reduced by selectively etching the silicon nitride film after the step (F).

An embodiment corresponding to claim 2 will be described with reference to FIG. (A) The P-type silicon substrate 301 is selectively ion-implanted with boron, which is a P-type impurity, to form the channel stopper region 30.
After forming 2, the field oxide film 303 is formed on the channel stopper region by the selective oxidation method. Subsequently, a thermal oxidation process is performed to form the silicon substrate 301 in the element formation region.
Approximately 10n of thermal oxide film 304 to be the gate oxide film on the surface of
Grow to a thickness of m. A polycrystalline silicon film 305 containing impurities is deposited on the entire surface to a thickness of about 300 nm, and a titanium film 306 is further deposited on the entire surface to a thickness of about 50 nm.
To a thickness of. Further thereon, a polycrystalline silicon film 307 is deposited on the entire surface to a thickness of about 150 nm.

Then, those films are patterned by photolithography and etching to form a convex pattern composed of the gate oxide film 304, the polycrystalline silicon film 305 containing impurities, the titanium film 306 and the polycrystalline silicon film 307. Using the convex pattern and the field oxide film 303 as a mask, as in the step (A) of FIG. 2, phosphorus, which is an N-type impurity, is formed on the silicon substrate 301 to form a low concentration region of the LDD structure of the source / drain regions. Is ion-implanted. The ion implantation conditions at this time are the same as those in the step (A) of FIG. 2, and the implantation energy is 85 to 95 Ke.
V, dose amount is 2.0 × 10 ^{13 to} 2.5 × 10 ¹³ / cm ^2.
Is.

(B) Heat treatment is performed to form a thermal oxide film (not shown) of about 10 nm on the exposed silicon substrate 301, and then heat treatment is performed in an inert gas atmosphere to implant the silicon substrate 301. Activated phosphorus to form an N ⁻ region 308 having a shallow junction depth. By these heat treatments, interdiffusion between the titanium film 306 and the polycrystalline silicon films 305 and 307 progresses to cause silicidation, and the polycrystalline silicon films 305 and 307 are respectively formed into the silicide layers 305.
a, 307a. Then, a silicon oxide film 309 is deposited on the entire surface by a CVD method to a thickness of about 100 nm.

(C) The silicon oxide film 309 is etched by reactive ion etching, and the sidewalls 310 of the silicon oxide film are left on the side surfaces of the convex pattern to be the gate electrode.

(D) After that, the convex pattern to be the gate electrode and the side wall 3 of the silicon oxide film on the side surface thereof are formed.
10, using the field oxide film 303 as a mask,
Arsenic, which is an N-type impurity, is ion-implanted into the silicon substrate 301 to form a high concentration source / drain N ⁺ region 311 having a junction deeper than the N ⁻ region 308. The ion implantation conditions at this time are the same as those in the step (D) of FIG. 2, the implantation energy is 45 to 55 KeV, and the dose amount is 5 × 10 ^{15 to} 6 × 10 ¹⁵ / cm ² .

(E) Next, a titanium film 312 as a refractory metal for forming a silicide layer is deposited to a thickness of 50 to 100 nm by a method such as a sputtering method.

(F) Subsequently, heat treatment is performed by a lamp annealing method (RTA) at a temperature of 650 to 750 ° C. for 10 to 30 seconds, and a silicon and titanium film is formed on the surface of the gate electrode 307a and the surface of the source / drain region. Interdiffusion is performed with respect to the metal layer 312 to form a silicide layer 313. Next, the unreacted titanium film 312 is removed with a mixed solution of (ammonia water + hydrogen peroxide solution + pure water) which is an etching solution for titanium. As a result, the silicide layer 313 remains only on the surface of the source / drain region and the surface of the gate electrode.

An embodiment corresponding to claim 3 will be described with reference to FIG. (A) The channel stopper region 40 is formed by selectively ion-implanting boron, which is a p-type impurity, into a p-type silicon substrate 401.
After forming 2, the field oxide film 403 is formed on the channel stopper region by the selective oxidation method. Then, a thermal oxidation process is performed to form the silicon substrate 401 in the element formation region.
Approximately 10n of thermal oxide film 404 to be the gate oxide film on the surface of
Grow to a thickness of m. A polycrystalline silicon film 405 containing impurities is deposited on the entire surface to a thickness of about 500 nm.

Then, titanium, which is a refractory metal, is injected into the polycrystalline silicon film 405. The injection condition at this time is 1
Energy of 0 to 30 KeV and dose of 5 × 10 ¹⁵
˜5 × 10 ¹⁶ / cm ² . Polycrystalline silicon film 405
By using titanium as the refractory metal to be ion-implanted into titanium, titanium has an advantage that a special implanter is not required because the mass of titanium is relatively light. However, the polycrystalline silicon film 405
Instead of titanium, the refractory metal to be ion-implanted may be molybdenum, tantalum, or tungsten.

(B) The polycrystalline silicon film 405 and the gate oxide film 404 are patterned by photolithography and etching to form a convex pattern to be a gate electrode. Using the convex pattern and the field oxide film 403 as a mask, as in the step (A) of FIG. 2, phosphorus, which is an N-type impurity, is added to the silicon substrate 401 to form a low concentration region of the LDD structure of the source / drain regions. Is ion-implanted. The ion implantation conditions at this time are the same as those in the step (A) of FIG. 2, the implantation energy is 85 to 95 KeV, and the dose amount is 2.0 × 10 ^{13 to} 2.5 × 10 ¹³ / cm ² .

(C) Next, heat treatment is performed to form a thermal oxide film (not shown) of about 10 nm on the exposed silicon substrate 401.
After forming, heat treatment under an inert gas atmosphere,
Phosphorus implanted into the silicon substrate 401 is activated to form an N ⁻ region 406 having a shallow junction depth. Subsequently, a silicon oxide film 407 is formed on the entire surface by a CVD method to a thickness of about 100 nm.
Deposited to a thickness of

(D) The silicon oxide film 407 is etched by reactive ion etching, and the sidewalls 408 of the silicon oxide film are left on the side surfaces of the convex pattern to be the gate electrode. After that, arsenic, which is an N-type impurity, is ion-implanted into the silicon substrate 401 by using the convex pattern to be the gate electrode, the sidewall 408 of the silicon oxide film on the side surface thereof, and the field oxide film 403 as a mask, and N ⁻ A high concentration N ⁺ region 409 having a junction deeper than the region 406 is formed. The ion implantation conditions at this time are the same as those in the step (D) of FIG. 2, the implantation energy is 45 to 55 KeV, and the dose amount is 5 × 10 ^15.
It is about 6 × 10 ¹⁵ / cm ² .

(E) Next, a titanium film 410 is deposited as a refractory metal forming a silicide layer to a thickness of 50 to 100 nm by means such as sputtering.

(F) Subsequently, heat treatment is performed by a lamp annealing method at a temperature of 650 to 750 ° C. for 10 to 30 seconds, and the surface of the polycrystalline silicon gate electrode 405 and the source.
Interdiffusion between silicon and titanium film 410 is performed on the surface of the drain region to form a silicide layer 411.
Next, an unreacted titanium film 410 is mixed with a mixed solution of (ammonia water + hydrogen peroxide solution + pure water) which is an etching solution of titanium.
Is removed. As a result, the silicide layer 411 remains only on the surface of the source / drain region and the surface of the gate electrode.
The silicide layer can be similarly formed by using molybdenum, tantalum, or tungsten instead of titanium as the refractory metal film deposited in the embodiment. It is easy to remove the unreacted metal film of these refractory metals by wet etching.

[0035]

According to the first aspect of the present invention, since the protruding sidewall is formed between the gate electrode and the source / drain region in the heat treatment step for silicidation, silicon is diffused in the refractory metal film. It is possible to prevent the short circuit between the gate electrode and the source / drain regions with the silicide layer. In the present invention according to claims 2 and 3, since the refractory metal is contained in the gate electrode, the delay of the silicidation reaction in the polycrystalline silicon can be compensated for, and the silicidation can be achieved in a short time. It is possible to prevent a short circuit between the electrode and the source / drain region due to the silicide layer. When titanium, molybdenum, tantalum, or tungsten is used as the refractory metal film, the unreacted refractory metal film can be easily removed by wet etching after the silicidation step.

According to the present invention of claim 5, P is used as the silicon oxide film deposited on the polycrystalline silicon film of the gate electrode.
By using a silicon oxide film containing impurities such as an SG film, a BPSG film, and a BSG film, impurities are diffused into the polycrystalline silicon film of the gate electrode by heat treatment, and the resistance of the polycrystalline silicon film is lowered. You can In addition, the use of a silicon oxide film containing impurities facilitates removal by etching and improves the operating rate of the device. In the present invention in which titanium is ion-implanted into the polycrystalline silicon film of the gate electrode, titanium is used as the refractory metal to be ion-implanted as in claim 6, so that titanium has a relatively light mass, so that a special implanter is used. do not need. Since the present invention does not include a photoengraving step other than the step of patterning the gate electrode, the cost increase can be suppressed.

[Brief description of drawings]

FIG. 1 is a process sectional view showing a conventional salicide method.

FIG. 2 is a process sectional view showing a first embodiment.

FIG. 3 is a process sectional view showing a second embodiment.

FIG. 4 is a process sectional view showing a third embodiment.

[Explanation of symbols]

201, 301, 401 Silicon substrate 204, 304, 404 Gate oxide film 205, 305, 307, 405 Polycrystalline silicon film 206 PSG film 208 Silicon nitride film 209, 310, 408 Sidewall 309, 409 Silicon oxide film 211, 306, 312,410 titanium film 212,313,411 silicide layer

Claims (6)

[Claims] 1. A method of manufacturing a semiconductor device, comprising the following steps (A) to (D). (A) A gate insulating film is formed in an element formation region of a semiconductor substrate, a polycrystalline silicon film is formed on the gate insulating film, and a silicon oxide film is further formed on the gate insulating film. Then, the polycrystalline silicon film and the silicon oxide film are removed. A step of patterning to form a gate electrode, (B) forming a silicon nitride film on the surface of the substrate including the gate electrode, anisotropically etching the silicon nitride film, and forming the silicon nitride film only on the side of the gate electrode. And (C) removing the silicon oxide film by etching to expose the surface of the polycrystalline silicon film of the gate electrode, (D) forming a refractory metal film on the substrate surface including the gate electrode, and performing heat treatment. Is performed to silicidize the refractory metal film in contact with the semiconductor substrate silicon and the polycrystalline silicon film of the gate electrode, and then except the silicified portion of the refractory metal film. The step of removing by etching. 2. A method of manufacturing a semiconductor device, comprising the following steps (A) to (C). (A) A gate insulating film is formed in an element forming region of a semiconductor substrate, a polycrystalline silicon film is formed on the gate insulating film, a refractory metal film is further formed on the gate insulating film, and a polycrystalline film is further formed on the refractory metal film. Forming a gate electrode by patterning the uppermost polycrystalline silicon film, the refractory metal film thereunder, and the lowermost polycrystalline silicon film after forming the silicon film,
(B) forming an insulating film on the surface of the substrate including the gate electrode,
A step of anisotropically etching the insulating film to leave the insulating film only on the side of the gate electrode, (C) forming a refractory metal film on the surface of the substrate including the gate electrode, and performing heat treatment on the semiconductor substrate. After silicidizing the refractory metal film in contact with silicon and the polycrystalline silicon film of the gate electrode,
A step of etching away the portion of the refractory metal film other than the silicided portion. 3. A method of manufacturing a semiconductor device, comprising the following steps (A) to (C). (A) A gate insulating film is formed in an element forming region of a semiconductor substrate, a polycrystalline silicon film is formed thereon, and then a refractory metal is ion-implanted into the polycrystalline silicon film. Step of patterning a silicon film to form a gate electrode, (B) forming an insulating film on the surface of the substrate including the gate electrode, anisotropically etching the insulating film, and insulating the insulating film only on the side of the gate electrode. The process of leaving the film,
(C) After forming a refractory metal film on the surface of the substrate including the gate electrode and performing a heat treatment to silicide the refractory metal film in contact with the semiconductor substrate silicon and the polycrystalline silicon film of the gate electrode, A step of removing portions other than the silicided portion of the melting point metal film by etching. 4. The method for manufacturing a semiconductor device according to claim 1, wherein the refractory metal film and the ion-implanted refractory metal are molybdenum, tantalum, tungsten, or titanium. 5. The silicon oxide film formed on the polycrystalline silicon film in the step (A) of claim 1 is one to which impurities are added, and the polycrystalline silicon film of the gate electrode is formed in the subsequent heat treatment step. The method of manufacturing a semiconductor device according to claim 1, wherein the impurities diffuse to reduce the resistance of the polycrystalline silicon film of the gate electrode. 6. The method of manufacturing a semiconductor device according to claim 3, wherein the ion-implanted refractory metal is titanium.