JPH0581051B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention relates to a method for manufacturing a semiconductor device, and in particular, a method for manufacturing a semiconductor device suitable for increasing the density of the electrode extraction portion and miniaturizing the semiconductor element region. Regarding.

(Prior art) Nowadays, the pattern dimensions of semiconductor integrated circuits have progressed to the submicron order, and the high mask alignment precision of commonly used photolithography is making it possible to miniaturize the semiconductor element area and speed up the response. It is becoming an obstacle for higher education.

In particular, the size (area) of the source/drain region of a MOSFET is determined by the accuracy of mask alignment in forming the electrode extraction (contact) part, making it difficult to miniaturize the active region of the element and increase speed. I can't plan.

For example, FIGS. 4a and 4b show a cross-sectional view and a planar pattern of a conventional MOSFET. Each component includes a P-type semiconductor substrate 100, a field oxide film 101, a gate oxide film 102, and a gate electrode 10.
3. Low concentration drain region 104, gate electrode 10
A side wall 105 made of a silicon oxide film provided on the side wall of 3, a high concentration source/drain region 106, a passivation film (PSG film) 107,
It consists of a contact hole 108 and an electrode wiring layer 109.

(Problems to be Solved by the Invention) In the conventional MOSFET described above, the oxide film 102 on the source/drain region (n ⁺ layer) 106
Since the contact hole 108 is directly provided to form the electrode wiring layer 109, it is necessary to secure a large area for the source/drain region 106.

For example, as shown in FIG. 5, when forming a contact hole 108 in a passivation film 107, if the mask is misaligned and the contact hole overlaps the edge of the field oxide film 101, the electrode wiring layer 109 and P-type semiconductor substrate 1
00, the source or drain region 106 and the substrate 100 are short-circuited through the electrode wiring layer 109.

Therefore, as shown in FIG. 4B, the contact hole 108 needs to be formed at a distance D _a from the inner edge of the field oxide film 101 that is greater than the mask alignment accuracy of photolithography. Similarly, the contact hole 108 is also located at a distance greater than the mask alignment accuracy from the gate electrode 103.
It is necessary to form them with D _b separated.

For this reason, the area of the source/drain region (n ⁺ layer) 106 of the conventional MOSFET needs to be increased by the area associated with electrode formation, and miniaturization cannot be achieved. In addition, in terms of functionality, the parasitic capacitance of the source/drain region 106 increases, making it impossible to increase the speed of the device.

Note that, although the above-mentioned example concerns an N-channel MOSFET, the problem is exactly the same in a P-channel MOSFET, and a similar problem also occurs in the formation of an electrode in the base region of a bipolar transistor.

The purpose of the present invention is to achieve high integration and high performance (high speed, high reliability) by eliminating the need for semiconductor regions (source/drain regions for MOSFETs and base regions for bipolar transistors) required only for electrode formation. An object of the present invention is to provide a method for manufacturing a semiconductor device suitable for

(Means for solving the problem) The above object is to form a polycrystalline silicon film in contact with a source/drain region or a base region and separated in a self-aligned manner by a gate electrode or an emitter electrode. This is achieved by providing contact members for these areas.

According to the results of studies conducted by the present inventors, the etching rate or oxidation rate of a polycrystalline silicon film to which donor-type impurities such as As, P, or Sb are added at a high concentration is lower than that of a polycrystalline silicon film to which these are not added. A semiconductor device with the above structure can be realized by utilizing the phenomenon that the size is significantly larger than that in comparison.

That is, when applying the present invention to an N-channel MOSFET, there is a step of adding As, P, or Sb at a high concentration into the gate electrode, and an insulating film with a controlled thickness is provided on the side walls of the gate electrode. At the same time, a step of exposing the source/drain region and the surface of the gate electrode is carried out, and then a polycrystalline silicon film to which no impurities are added is deposited on the entire surface, and then heat treatment is performed to expose the surfaces of the gate electrode. The impurities are diffused into the polycrystalline silicon film in a region in contact with the upper surface of the gate electrode.

After that, the etching rate or oxidation rate of the polycrystalline silicon into which the impurities have been diffused at a high concentration is:
Taking advantage of the fact that the polycrystalline silicon film is significantly larger than the polycrystalline silicon film to which no impurity has been added, only the polycrystalline silicon film on the gate electrode in which the impurity has been diffused is etched away in a self-aligned manner.

As a result, a desired N-channel MOSFET can be obtained by forming and processing the remaining polycrystalline silicon film into a size that covers at least a portion of the source region, drain region, and field oxide film.

(Function) The polycrystalline silicon film of the N-channel MOSFET formed as described above is separated into a portion above the source region and a portion above the drain region in a self-aligned manner by the gate electrode. , and are connected to the source and drain regions in a self-aligned manner.

Therefore, by doping the polycrystalline silicon film with impurities to lower its resistance, it can be used as source and drain electrode wiring. Therefore, it is no longer necessary to enlarge the area of the source/drain region, which was conventionally necessary in conjunction with the formation of electrode wiring, and the conventional disadvantages can be eliminated.

The present invention is not only applicable to P-channel MOSFETs, but also to electrode wiring in the base region of bipolar transistors.

(Example) Hereinafter, an example of the present invention will be described using the drawings. FIG. 2 is a cross-sectional view showing a method for manufacturing an N-channel MOSFET according to an embodiment of the present invention in the order of manufacturing steps.

FIG. 2a First, a field oxide film 31 is formed on a P-type semiconductor substrate 30 by selective oxidation, and a thin gate oxide film 32 is formed in a region surrounded by the field oxide film 31.

Next, a first polycrystalline silicon film is applied to the entire surface for 2000 m
A film of 3000 Å thick is deposited on top of the MoSi ₂ film with a thickness of 3000 Å. Furthermore, after ion-implanting 2.5×10 ¹⁶ cm ⁻² of As, it is processed into a desired shape by photolithography to form the gate electrode 33.

Using the gate electrode 33 as a mask, lightly doped n-type source/drain regions 34 are formed by ion implantation.

Figure 2b After depositing a silicide oxide film on the entire surface by CVD method,
By etching the silicon oxide film using an anisotropic dry etching technique, side walls 35 made of silicon oxide are provided on the side walls of the gate electrode 33, and at the same time, side walls 35 made of silicon oxide are formed on the upper surfaces of the source region, drain region 34, and gate electrode 33. expose.

FIG. 2c After a second polycrystalline silicon film 36 is deposited on the entire surface with a thickness of 3000 Å,
By performing a heat treatment at .degree. C. for 10 minutes, a thin silicon oxide film of several tens of angstroms is formed on the surface of the second polycrystalline silicon film 36.

Next, heat treatment is performed at 900° C. for 30 minutes in a nitrogen atmosphere to diffuse the As doped in the gate electrode 33 into the polycrystalline silicon in the region in contact with the upper surface of the gate electrode 33, so that As is doped. A polycrystalline silicon film 36A is formed directly above the gate electrode 33.

Figure 2 d When heat treatment is performed at 70°C for 60 minutes in water vapor obtained by burning a mixed gas of H ₂ /O ₂ =1.6/1, about 2000
A silicon oxide film 37 with a thickness of about 250 Å is grown on the undoped polycrystalline silicon film 36, while a silicon oxide film 38 with a thickness of about 250 Å is grown on the undoped polycrystalline silicon film 36.

FIG. 2e After removing the silicon oxide film 38 with an HF-based aqueous solution, Mo is deposited to a thickness of 500 Å on the entire surface.

Next, a heat treatment is performed at 600° C. for 30 minutes in a nitrogen atmosphere to cause the upper layer of the polycrystalline silicon film 36 to react with Mo, and then the unreacted Mo on the silicon oxide film 37 is removed.
By removing it with aqua regia, MoSi ₂ 39 is formed in a self-aligned manner on the surface portion except on the silicon oxide film 37.

Furthermore, heat treatment was performed at 800°C for 10 minutes in a dry oxygen atmosphere to form a thin silicon oxide film on the MoSi ₂ 39, and As ions 40 were added to the entire surface at 1×10 ¹⁶
By implanting cm ⁻² and performing heat treatment at 950° C. for 10 minutes in a nitrogen atmosphere, a highly concentrated n-type source/drain region 41 is formed in the P-type semiconductor substrate 30.

FIG. 2f The polycrystalline silicon film 36 and the MoSi ₂ film 39 are selectively etched using a conventional photolithography method so that at least a portion thereof extends onto the field oxide film 31. Then, as shown in FIG.

Next, the silicon oxide film 37 is removed by photolithography.
After removing it by etching, it was heated to about 70℃.
The polycrystalline silicon film 36A on the gate electrode 33 is removed using an etchant of a KOH aqueous solution/isopropyl alcohol mixture to form a source/drain electrode 42.

At this time, the MoSi ₂ film 39 on the gate electrode 33 and the polycrystalline silicon film 36 is not dissolved at all by the etchant.

FIG. 2g After a PSG film 43 is deposited on the entire surface as a passivation film, a contact hole 44 is formed on the source/drain electrode 42 using a conventional photolithography method. Next, Al-2%Si was deposited on the entire surface, and the electrode wiring layer 4 was selectively etched in the same manner as described above.
5, the manufacturing process of the n-channel MOSFET is completed.

Note that FIG. 1 is a diagram showing the plane pattern of FIG. 2g.

By using the manufacturing method explained above,
The source region and drain region 41 are formed by a source/drain electrode 42 formed in a self-aligned manner.
The contact hole 44 extends above the field oxide film 31, and the contact hole 44 can be formed at least on the field oxide film 31 (instead of only on the source/drain region 41). The large area source and drain regions required in the prior art are no longer required.

Therefore, miniaturization of MOSFETs can be easily achieved. Moreover, as the area of the source/drain regions is reduced, the parasitic capacitance thereof can also be significantly reduced, so that higher speed devices can be achieved.

Further, since the connection between the electrode wiring layer 45 and the source/drain regions 34 and 41 is made via the polycrystalline silicon film (source/drain electrode) 36,
Deterioration of bonding characteristics due to penetration of Al atoms contained in the electrode wiring layer can be prevented.

Furthermore, a highly doped n-type source/drain region 41
is formed by the diffusion of As from the polycrystalline silicon 36, so it is possible to make the diffusion depth sufficiently shallow, which results in the short channel effect (the depletion layer in the drain region becomes the source region). It is less susceptible to the effects of large currents that limit the space charge (in other words, punch-through).
MOSFET can be realized.

In this embodiment, the case where As is used as the impurity doped into the gate electrode 33 has been described.
Even when impurities such as P and Sb were used, the desired effects of the present invention could be achieved.

Further, although MoSi ₂ is used on the gate electrode 33 and the source/drain electrodes, other silicides may be used. Furthermore, although the polycrystalline silicon film 36 on the gate electrode is etched using a KOH aqueous solution etchant, it is also possible to use an alkaline solution such as a hydrazine aqueous solution or ammonium hydroxide, or photoexcitation etching using a chlorine gas. The effects of the present invention can also be achieved using other etching methods such as etching.

The first embodiment of the present invention has a P channel.
It was confirmed that the same effect can be achieved even when applied to MOSFETs and bipolar transistors.

Next, a second embodiment of the present invention will be described. FIG. 3 is a cross-sectional view sequentially showing the manufacturing steps when the present invention is applied to manufacturing the emitter and base regions of a bipolar transistor.

FIG. 3a First, a high concentration n-type conductive layer (n ⁺ layer) 51 is formed on a P-type semiconductor substrate 50, and a low concentration conductive single crystal layer (n ^- layer) 5 is formed by epitaxial growth.
2 is formed, and then a field oxide film 53 is formed by selective oxidation.

Next, a thin silicon oxide film 54 is formed in the region surrounded by the field oxide film 53, and then B is ion-implanted to form a P-type conductive region 55 that will become a base layer.

FIG. 3b: selectively etching a desired region of the thin silicon oxide film 54;
Form an opening. Next, a first polycrystalline silicon film with a thickness of 2000 Å was deposited on the entire surface, and MoSi ₂
Deposit a 1000 Å film. After that, heat treatment was performed at 800℃ for 10 minutes in a dry oxygen atmosphere, and the
A thin silicon oxide film is formed on the surface of MoSi ₂ .

Next, by implanting As ions at 1.5×10 ¹⁶ cm ⁻² into the entire surface and heat-treating in a nitrogen atmosphere, a highly concentrated n-type conductive emitter layer 57 is formed in the P-type conductive region 55 .

Thereafter, the polycrystalline silicon film and the MoSi ₂ film thereon are selectively etched to form an emitter electrode 56, leaving the silicon oxide film 54 so as to cover the etched opening.

Figure 3c: After depositing a silicon oxide film on the entire surface using the CVD method, the silicon oxide film is etched using an anisotropic dry etching technique to form a sidewall 58 with a controlled thickness on the side wall of the emitter electrode. At the same time as providing the base region 55 and the emitter electrode 5
Expose the top surface of 6.

Figure 3d: After depositing a second polycrystalline silicon film 59 on the entire surface with a thickness of 2000 Å, it is placed in a dry oxygen atmosphere.
Heat treatment is performed at 800° C. for 10 minutes to form a thin oxide film of several tens of angstroms on the surface of the polycrystalline silicon film 59.

Next, heat treatment is performed at 900° C. for 30 minutes in a nitrogen atmosphere to transfer the As atoms doped into the emitter electrode 56 into the second polycrystalline silicon film 59 in the region in contact with the upper surface of the emitter electrode 56. A polycrystalline silicon film 59A doped with As is formed by diffusion.

FIG. 3e When heat treatment is performed at 800° C. for 60 minutes in an air stream made by burning a mixed gas of H ₂ /O ₂ =1.6/1, the second polycrystalline silicon film 59A doped with As is , a silicon oxide film 60 with a thickness of 2200 Å is grown, while a second polycrystalline silicon film 59 in other regions that are not doped is grown.
A silicon oxide film 61 with a thickness of about 5000 Å is grown on A.

Next, B ions are implanted at 3×10 ¹⁵ cm ⁻² into the entire surface through the silicon oxide film 61, and heat treatment is performed at 950° C. for 10 minutes to heat the second polycrystalline silicon film 5.
High concentration P-type conductive layer 6 in the base region in contact with 9
form 2. At this time, the thick silicon oxide film 60 as described above functions as a mask to prevent B ions from being implanted into the emitter electrode 56.

FIG. 3f First, the silicon oxide film 61 is removed by etching. At this time, a portion of the thick silicon oxide film 60 remains. Thereafter, a silicon nitride film 63 is selectively formed on the second polycrystalline silicon film 59 by plasma thermal nitridation.

FIG. 3g Silicon oxide film 6 on second polycrystalline silicon film 59A
After removing 0 with an HF solution, the silicon nitride film 6
3 as a mask, the second polycrystalline silicon film 59A on the emitter electrode 56 is removed using a hydrazine aqueous solution to expose the upper surface of the emitter electrode 56.

Next, the silicon nitride film 6 is removed using a hot phosphoric acid solution.
3 is removed, the second polycrystalline silicon film 59 is selectively etched using a normal photolithography method, leaving the second polycrystalline silicon film 59 to cover at least the inner edge of the field oxide film 53. A base electrode 64 made of silicon film 59 is formed.

FIG. 3h Next, after depositing a PSG film 65 as a passivation film, the PSG film 65 is selectively etched to open a contact hole 66 for the base electrode 64 and a contact hole 66A for the emitter electrode 56, respectively.

Next, after depositing Al-2%Si on the entire surface, selective etching is performed in the same manner as described above to form an electrode wiring layer 67, thereby completing the manufacturing process of the bipolar transistor.

Note that FIG. 3i is a plan pattern diagram of FIG. 3h.

If the manufacturing method described above is used, the base layer 55 has a base electrode 64 that is ohmic-connected in a self-aligned manner, and the base electrode 64 extends to the top of the field oxide film 53. A contact hole 66 in the base region can be provided above the base electrode 64 on this field oxide film 53.

Therefore, it is possible to completely eliminate the enlarged base region, which was required only for forming contact holes in the base region in the conventional method.

As a result, it is not only possible to easily miniaturize the bipolar transistor by reducing the base region to the necessary minimum size, but also to significantly reduce the parasitic capacitance of the base region, thereby increasing the speed of the device.

In addition, in the conventional method, the formation position of the high concentration P-type conductive layer, which serves as an external base, is set at a sufficient distance from the emitter electrode that exceeds the mask alignment accuracy (Db in Figure 4), taking into account the mask itself and mask alignment errors.
However, in the present invention, since the thick oxide film 60 on the emitter electrode prevents B ions from being implanted into the emitter electrode, it is necessary to consider alignment accuracy. do not have.

That is, since the heavily doped P-type conductive layer 62 can be brought close to the emitter electrode 56 in a self-aligned manner, the base series resistance is reduced and the speed can be further increased.

Further, the connection between the electrode wiring layer 65 and the base layers 55 and 62 is formed using a second polycrystalline silicon film (base electrode).
64, it is possible to prevent deterioration of bonding characteristics due to penetration of Al atoms constituting the electrode wiring layer 67. Therefore, the reliability of the device can be greatly improved.

(Effects of the Invention) According to the present invention, a polycrystalline silicon electrode can be provided in a self-aligned manner on the source/drain region of a MOSFET or on the base region of a bipolar transistor. The area of the region can be sufficiently miniaturized. As a result, the device can be easily integrated to a high degree, parasitic capacitance and parasitic resistance can be significantly reduced, and the speed of the device can be increased.

[Brief explanation of the drawing]

FIG. 1 shows n manufactured by the manufacturing method of the present invention.
A planar pattern diagram of a channel MOSFET, FIG. 2 is a cross-sectional view showing a method for manufacturing an n-channel MOSFET, which is an embodiment of the present invention, in order of manufacturing steps, and FIG. 3 is a method for manufacturing a bipolar transistor, which is another embodiment of the present invention. Figure 4 is a cross-sectional view and a plane pattern diagram showing the manufacturing process in order.
A cross-sectional view of the MOSFET and its plane pattern diagram, Figure 5 is a MOSFET to explain the drawbacks of the conventional method.
FIG. 31...Field oxide film, 33...Gate electrode, 42... _MoSi2 /polycrystalline silicon film (source/drain electrode), 44...Contact hole,
45... Electrode wiring layer, 53... Field oxide film, 56... Emitter electrode, 64... Polycrystalline silicon film, 66... Contact hole, 67... Electrode wiring layer.

Claims (1)

[Scope of Claims] 1. At least one of As, P, and Sb is formed on the semiconductor region of one conductivity type of a semiconductor substrate having semiconductor regions of one conductivity type and opposite conductivity type adjacent to each other and exposed on the same main surface. a step of forming a first electrode made of a conductive film doped with impurities of a step of forming an insulating layer so as to penetrate into the substrate from the main surface; a step of forming an insulating layer to cover a side wall of the first electrode; and the first electrode, the insulating layer provided on the side wall, and the opposite conductivity type. a step of providing a polycrystalline silicon film so as to cover the semiconductor region and the field insulating layer; a step of then performing heat treatment to diffuse the impurity into the polycrystalline silicon film in a region in contact with the first electrode; and then oxidizing. By heat treatment in a neutral atmosphere, a thick silicon oxide film is formed on the polycrystalline silicon film in the region where the impurity is diffused, and a thin silicon oxide film is formed on the polycrystalline silicon film in the region where the impurity is not diffused. After removing the thin oxide film using the thick oxide film as a mask, forming at least one of a refractory metal silicide film and a silicon nitride film on the exposed polycrystalline silicon; After removing the thick oxide film, using at least one of the high melting point metal silicide film and the silicon nitride film as a mask, the polycrystalline silicon in the region where the impurities have been diffused is etched and removed, and the semiconductor of the opposite conductivity type is removed. 1. A method of manufacturing a semiconductor device, comprising: forming a second electrode ohmicly connected to the region. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the first electrode is ohmicly connected to the semiconductor region of one conductivity type. 3. The method of manufacturing a semiconductor device according to claim 1, wherein the first electrode is formed insulated from the 1-conductivity type semiconductor region.