JPH065696B2 - Method for manufacturing semiconductor device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for making direct contact between a gate electrode and a diffusion layer wiring.

[Technical Background of the Invention and Problems Thereof] In the conventional LS1, wiring between elements is performed by a diffusion layer, polysilicon, Al wiring, and the like. The interconnections between these wirings are made, for example, via diffusion layers and, in the case of polysilicon, via direct contacts. However, the conventional direct contact method is
There are various problems, and new technical improvements have been desired. The problems of the prior art will be described below with reference to the drawings.

FIG. 4A is a plan view showing a part of an LSI having a direct contact, in which a gate electrode (401) made of polysilicon, a wiring (402) and the like are arranged. (403) (404)
Is a diffusion layer wiring, and at the same time is a source and a drain of a MOS transistor having (401) as a gate electrode. For example, this corresponds to the circuit diagram as shown in FIG. 4 (b). Electrical contact between the polysilicon wiring (402) and the diffusion layer wiring (404) is made by direct contact (405). 5 (a) to 5 (d) are cross-sectional views of the circuit element p-p 'shown in FIG. 4, which schematically shows the manufacturing process.

For example, a gate oxide film (502) is formed on the P-type Si substrate (501) by thermal oxidation of about 200 Å, for example. Then, mask alignment is performed, and the oxide film of the direct contact portion (503) is removed by etching with, for example, NH ₄ F to expose the surface of the Si substrate (FIG. 5 (a)). Next, polysilicon (504) is deposited on the entire surface by a CVD method or the like, and, for example, POC is used.
l ₈ Diffusion is performed to diffuse phosphorus over the entire surface. At this time, in the direct contact portion, phosphorus is diffused into the silicon substrate to form a diffusion layer (505) (FIG. 5 (b)). Next, a photoresist (506) is left by matching a mask to the gate electrode and the wiring portion, and using this as a mask, polysilicon (50
4) is removed by etching. This etching can be
It is performed by reactive ion etching using l ₄ etc. At this time, the etching of Si stops at the surface of the oxide film (502) in the transistor part, but since there is no oxide film in the direct contact part, FIG. 5 (c) A groove (507) is formed in the silicon substrate as shown in FIG. Then, the gate oxide film (502) is removed, and As is ion-implanted at 3 to 5 × 10 ¹⁵ cm ^{-2 at} 50 KV, and then annealed at, for example, 1000 ° C. for about 30 minutes to form the source / drain and diffusion layer wiring ( 508) is formed. At this time, an N ⁺ diffusion layer is also formed in the groove portion by ion implantation, and the polysilicon wiring (509) and the diffusion layer wiring (508) are
It is electrically connected. However, since the depth and shape of the groove portion are not constant and vary greatly depending on etching conditions, overetching time, etc., the variation in the resistance value in the groove portion becomes large. If the groove is large and circular,
As shown in Figure (e), the diffusion layer does not connect to the groove
(508) and the polysilicon wiring (509) are electrically isolated. The above problem becomes an important problem as the junction depth becomes shallower with the miniaturization of the device, which has been a cause of remarkably lowering the yield of the LSI. There is also a problem that the crystal defects generated in the groove due to the reactive ion etching increase the junction leak in the diffusion layer and deteriorate the device performance.

The case of an N-channel transistor formed on a p-type substrate has been described above, but a so-called CMOS circuit in which a p-type portion and an n-type portion are simultaneously present on the same substrate has the following important problem. That is, if N ⁺ polysilicon is used, direct contact cannot be made in the region where the P channel transistor is formed. For example, Figure 6 (a)
As shown in Fig. 5, the source / drain / diffusion layer wiring is made of P ⁺ diffusion layer with ion implantation of polon, but Fig. 5 (a)-
If the same process as in (d) is performed, a pn junction cannot be formed between the N ⁺ polysilicon and the n-type substrate in the direct contact portion, so that the substrate is short-circuited. Also, for example, in FIG.
After forming the P ⁺ diffusion layer initially form a gate (610) of the transistor as shown in (b), N ⁺ polysilicon When forming the wiring (609) by a second N ⁺ polysilicon
A pn junction is formed in the direct contact portion between (609) and the P ⁺ diffusion layer (608), and ohmic contact cannot be established.

For the above reason, for example, in a CMOS circuit using N ⁺ polysilicon wiring, direct contact could not be established in the P channel transistor region. These problems have placed great constraints on circuit design.

[Object of the Invention] The present invention has been made in view of the above points, and an object of the present invention is to provide a direct contact manufacturing method capable of achieving high integration, excellent yield, and increased design freedom of LSI. And

[Summary of the Invention] In the present invention, an electrode is formed in a direct contact portion via an insulating film, and a semiconductor material is selectively left on the side portion thereof. Then, a metal or a metal-semiconductor compound is formed on the surface of the substrate, the upper surface of the electrode, and the surface of the semiconductor material in a self-aligned manner to connect the electrode and the wiring region of the substrate.

As a method of selectively forming, for example, a method of depositing a metal film and alloying it by heating, a method of growing under a metal halide gas, or the like can be used.

[Advantages of the Invention] According to the present invention, the diffusion layer wiring and the polysilicon wiring have a good yield and can be electrically contacted. Also, in CMOS,
Direct contact can be freely made to any combination of n ⁺ and p ⁺ polysilicon wirings and n-channel and p-channel transistors.
The degree of freedom in LSI design has greatly increased. Moreover, since the metal or the metal semiconductor compound is provided by the selective growth in this manner, as compared with the case where the insulating film is further deposited, the contact holes are formed in the wiring film and the substrate wiring layer respectively, and the metal member is formed to connect them. The degree of integration is significantly increased.

[Embodiment of the Invention] An embodiment of the present invention will be described below with reference to the drawings.

As shown in FIG. 1 (a), for example, a p-type silicon substrate (101)
A gate electrode 103 and a wiring 103 'made of polysilicon are formed on the gate oxide film (102) of, for example, 200 liters, and using these as a mask, for example, phosphorus at 40 kv and 10
¹³ to 10 ¹⁴ cm ^-2 ions are implanted to form an N type region 104.
The polysilicon used is one doped with impurities such as phosphorus or As.

Next, as shown in Fig. 1 (b), an oxide film is formed on the surface of the poly-Si film.
After growing about 0Å, poly-Si again, for example 3000
Å Grow to thickness. Next, for example, the entire surface is subjected to reactive ion etching to remove poly-Si by, for example, 3000 Å
By etching, as shown in FIG. 1 (c), the poly-Si 107, 107 'can be left only on the side walls of the electrode 103 and the wiring 104.

Next, a photoresist 109 is selectively provided on the surface, and MO
The polycrystalline silicon (107) on the side wall of the gate electrode (103) of the S-transistor is removed by etching using, for example, isotropic plasma etching (FIG. 1d).

Next, the photoresist is removed, and further the oxide film 110 on the N-type wiring layer 108, the gate electrode 103, and the oxide film (110 ', 110 ") on the wiring (103') are removed, and the Si substrate and the surface of the poly-Si are removed. To expose.

Then, a metal film such as titanium (Ti) is formed on the entire surface, for example, 50
When formed by 0Å vapor deposition and annealed at a temperature of 600-1000 ° C, for example, silicon and Ti react and a TiSi ₂ (titanium silicide) film of about 1000Å is formed in the contact area between Ti and Si or poly-Si. To be done.

The metal deposited on the oxide film 111 does not react, so no silicide is formed. Then, for example, when Umu is treated with fresh water, only unreacted Ti is dissolved, and Fig. 1 (e)
As shown in, a structure is obtained in which the silicide is self-aligned only on the Si surface.

Since the side wall of the gate electrode 103 is covered with the oxide film 111, the silicide 112, 114 formed on the source / drain is formed.
Are insulated from the silicide 113 formed on the gate electrode. However, the silicide 116 formed on the wiring, the silicide 115 formed on the poly-Si 107 'left on the sidewall and the silicide 114 formed on the diffusion layer 108 are connected to each other. The reason is that these silicon surfaces are separated from each other only by the region of the oxide film having a width of about 200 to 300 Å, and each surface has 200 to 300 Å.
When the above silicide is formed, bridges are easily formed and connected.

In this way, the wiring part 10
It is possible to electrically connect 3'and the substrate diffusion layer 108.

In this way, since the connection is made by the silicide, all the problems in the conventional Japanese radish are solved.

Moreover, since silicide is formed on the wiring surface, the wiring resistance can be reduced from the conventional 40 to 50 Ω / □ to 2 to 3 Ω / □, and the circuit speed can be increased.

Further, the drain of the transistor 120 has realized a so-called LDD (Lightly Doped Drain) structure composed of a region 104 with a small amount of N-type impurity and a region 108 with a large amount of N-type impurity, and is a highly reliable transistor having a high drain breakdown voltage. It has a structure.

In this embodiment, the method of performing the ion implantation of the n-type impurity twice is described, but it is needless to say that either one may be used if the LDD structure is not particularly required. Particularly, when the ion implantation is performed only once immediately after the gate electrode 103 and the wiring 103 'are formed, phosphorus is not implanted as in the case of 10 ¹³ to 10 ¹⁴ cm ^{-2 as} in this embodiment, but As is, for example, 3 to 5 ×. A diffusion layer may be formed by ion implantation of about 10 ¹⁵ cm ^-2 .

Further, it is clear that the resist shown in FIG. 1 (d) may be formed only once after being stripped.

FIG. 2 shows a second embodiment of the present invention in which a P-type diffusion layer 202, an N-type poly-Si gate electrode 203 and a wiring 204 are formed on an N-type substrate. The silicide 205 is formed by the same process as in the first embodiment, and the wiring 204 and the diffusion layer 20 are formed.
The two are connected to each other by a silicide 205.

Since both N-type and P-type silicide can make ohmic contact, there is no problem that a PN junction is formed between the wiring and the diffusion layer and ohmic contact cannot be made.

FIG. 3 shows a third embodiment of the present invention. The manufacturing process is exactly the same as in Fig. 1 (a) to (d), but instead of depositing Ti on the entire surface, for example, by reducing WF ₆ gas, metal W is selectively deposited on the silicon or polysilicon surface. It is a structure realized by depositing only.

With the structure shown in FIG. 1 in which the silicide is replaced by the metal W, the same effect as in the first embodiment can be obtained.

In the first and third embodiments described above, only the case where N-type impurities are introduced as poly-Si has been described, but P-type may of course be used. Further, in all of the above-mentioned embodiments, the n-type and the p-type may be replaced by any one without departing from the gist of the present invention.

In addition, silicide is not limited to TiSi ₂ , platinum silicide, palladium silicide, other tantalum, molybdenum,
Any metal silicide such as tungsten may be used.

It goes without saying that the metal layer selectively deposited may be made of a material other than W.

[Brief description of drawings]

1 (a) to (e) are process cross-sectional views for explaining the first embodiment of the present invention, and FIGS. 2 and 3 are process cross-sections for explaining the second and third embodiments of the present invention. Fig. 4 (a) is a top view for explaining a direct contact, Fig. 4 (b) is a circuit diagram thereof, Figs. 5 (a) to (e) and Fig. 6 (a) (b) are conventional. It is sectional drawing explaining an example. In the figure, 103,203,303,401,502 ... Gate electrode 103 ', 204,303', 402,509 ... Poly-Si wiring 108,202,308,404,508 ... Diffusion layer 112-116,205 ... Silicide (TiSi ₂ ) 312-316 ... Tungsten

Claims (3)

[Claims] 1. A step of forming an electrode on the surface of a semiconductor substrate via an insulating film, a step of covering the electrode surface with an insulating film, a semiconductor material is deposited, and the entire surface is anisotropically etched to form the electrode. A step of leaving this only on the side wall portion, a step of removing at least a part of the left semiconductor material, a step of exposing at least a part of the substrate surface not covered with the electrodes and the semiconductor material, By self-aligning a metal or a metal-semiconductor compound on the exposed surface of the substrate, the surface of the semiconductor material, and the upper surface of the electrode, the electrode in which the semiconductor material is left on the side wall and the substrate adjacent to the electrode are electrically connected. And a step of electrically connecting the semiconductor devices. 2. A first ion implantation step of introducing an impurity of a conductivity type opposite to that of the substrate using the electrode as a mask at least once before depositing the semiconductor material on the entire surface. The method for manufacturing a semiconductor device according to claim 1, wherein 3. A second ion implantation in which the semiconductor material is deposited on the entire surface and left only on the side wall portion, and then, at least once, an impurity of opposite conductivity type to the substrate is used as a mask with the semiconductor material and the electrode. The method of manufacturing a semiconductor device according to claim 2, further comprising a step, wherein the dose amount of the second ion implantation step is larger than the dose amount of the first ion implantation step.