JP3876401B2 - Manufacturing method of semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for manufacturing a semiconductor device, and in particular, Si and Ge in forming a low-resistance metal silicide electrode by heat-treating a semiconductor layer containing Si and Ge and a metal layer deposited thereon. The present invention relates to a method for manufacturing a semiconductor device characterized by the structure of a semiconductor layer containing Ge.
[0002]
[Prior art]
With the recent increase in the speed of semiconductor integrated circuit devices, salicide processes using metal silicide for source / drain electrodes and gate electrodes are widely used. In MOS type semiconductor integrated circuit devices using such salicide processes, When the gate dimension is reduced with the increase in integration, the depth of the impurity diffusion region constituting the source / drain region becomes shallower.
[0003]
In order to form a low-resistance silicide electrode while suppressing an increase in the pn junction leakage current with respect to such a shallow source / drain region, a silicon layer is deposited on the source / drain region, and the silicon layer is formed on the silicon layer. Attempts have been made to form silicide electrodes.
Such a method for forming a silicide electrode can be used for forming a fully depleted MOSFET on an SOI (Silicon On Insulator) substrate as well as for forming a silicide electrode in a source / drain region.
[0004]
Recently, instead of such a silicon layer, it has been proposed to use a layer containing Si and Ge having a smaller forbidden band width than the silicon layer, that is, a Si _1-x Ge _x layer. by using the Si _1-x Ge _x layer having a small band gap, the height of the silicide layer / Si _1-x Ge _x layer interface of the Schottky barrier is lowered, the silicide layer / Si _1-x Ge _x layer Since attempts have been made to reduce the contact resistance at the interface, the process of forming such a silicide electrode will be described with reference to FIGS.
[0005]
First, a conventional process for forming a Co silicide electrode will be described with reference to FIG. 6. In order to simplify the description, a part of the source / drain region is enlarged and illustrated.
6A. First, after depositing a Si _1-x Ge _x layer 42 (for example, Si _0.5 Ge _0.5 layer) on the source / drain region 41 by using the CVD method, the Co layer 43 is formed by the sputtering method. Deposit.
[0006]
FIG 6 (b) refer then used RTA (Rapid Thermal Annealing) method, for example, 30 to 120 seconds at 450 to 800 ° C., by heating treatment, a Co layer 43 and the Si _1-x Ge _x layer 42 To form a Co silicide layer 44 to be a source / drain electrode.
[0007]
Next, a conventional Ti silicide electrode forming process will be described with reference to FIG. 7. In this case as well, in order to simplify the description, a part of the source / drain region is shown enlarged.
7A. First, a Si _1-x Ge _x layer 42 (for example, Si _0.5 Ge _0.5 layer) is deposited on the source / drain region 41 by CVD, and then a Ti layer 45 is formed by sputtering. Deposit.
[0008]
Next, referring to FIG. 7B, the Ti layer 45 and the Si _1-x Ge _x layer 42 are reacted with each other by performing heat treatment at, for example, 550 to 800 ° C. for 30 to 120 seconds using the RTA method. The silicide layer 46 is formed, and then the unreacted Ti layer 45 is removed to form source / drain electrodes made of TiSi ₂ .
[0009]
[Problems to be solved by the invention]
However, in the conventional method of forming a silicide electrode for a Si _1-x Ge _x layer, a sufficient Si-metal reaction is not performed under the above heating conditions, and a high-resistance silicide layer with a small Si / metal ratio is formed. Alternatively, there is a problem that the metal remains unreacted.
[0010]
For example, in the case of Co silicide, when the Co layer reacts with the Si _1-x Ge _x layer, Co reacts preferentially with Si, whereas Ge acts to suppress the reaction. Therefore, when the composition ratio of Ge is large, a sufficient Si—Co reaction is not performed under the above heating conditions, a CoSi layer having a high resistance is formed, and a low resistance CoSi ₂ layer is not formed. The resistance is increased, thereby increasing the resistance of the entire source / drain electrode.
[0011]
FIG. 8 is a diagram showing the dependence of the sheet resistance on the wiring layer width when the Co silicide layer is formed on the Si _1-x Ge _x layer, although the wiring layer width dependence is hardly seen. Compared with the case where the Co silicide layer is formed on the Si layer, the sheet resistance value is increased by about 20 times.
[0012]
On the other hand, even in the case of the Ti silicide layer, since Ti and Si form silicide only at a ratio of 1: 2, that is, only TiSi ₂ is formed, a sufficient Si—Ti reaction can be achieved under the above heating conditions. There is a problem that an unreacted Ti layer remains, and a Ti silicide layer having a required thickness cannot be formed.
[0013]
In addition, when heat treatment is performed at a temperature and time sufficient for sufficient reaction, the metal layer deposited on the sidewall is also silicided, and the source / drain region and the gate electrode are short-circuited through the silicide layer. Problem arises.
[0014]
Further, Ge constituting the Si _1-x Ge _x layer does not effectively react with the metal under the above-described heating conditions, and therefore, the Ge in the region where the silicide is formed diffuses into the region where the silicide is not formed and remains. There is a problem that the mixed crystal ratio x of the Si _1-x Ge _x layer is changed.
[0015]
Accordingly, an object of the present invention is to form a low-resistance silicide layer with a desired thickness by reacting a semiconductor layer containing Si and Ge with a metal layer.
[0016]
[Means for Solving the Problems]
FIG. 1 is an explanatory diagram of the principle configuration of the present invention. Means for solving the problems in the present invention will be described with reference to FIG.
1A to 1C. (1) In the present invention, an Si _x (Ge _y C _1-y ) _1-x layer 2 and Si _v (Ge _w C _1-w ) ₁₋ are formed on a semiconductor _1. After sequentially depositing the _v layer 3 (where 0 <x <v <1, 0 <y ≦ 1, 0 <w ≦ 1), the Si _v (Ge _w C _1-w ) _1-v layer 3 is deposited. metal layer 4 is deposited, a method of manufacturing a semiconductor device by forming a metal compound and a metal silicide electrode by heat _{treatment, Si v (Ge w C 1} -w) 1-v Si composition ratio in the layer 3 v Is set to v ≧ 0.6 , the C composition ratios (1-x) (1-y) and (1-w) (1-v) are set to 0.05 or less, and the Si _v (Ge _w C _{1 -w} ) The thickness of the _1-v layer 3 is set to a thickness that allows complete silicidation by reaction with the metal layer 4.
[0017]
In this way, when forming the low resistance metal compound layers 5 and 6 using the Si (GeC) layer, that is, the silicide electrode, the metal layer 4 side has a two-layer structure having a different Si composition ratio with a high Si ratio. Thus, the Si _x (Ge _y C _1-y ) _1-x layer 2 having an arbitrary forbidden band width can be provided on the semiconductor 1 side, whereby the metal compound layer 6 and the Si _x (Ge _y C _{1). -y} ) The Schottky barrier at the interface with the _1-x layer 2 can be lowered, and the Si _v (Ge _w C _1-w ) _1-v layer 3 on the side on which the metal compound layers 5 and 6 are formed Since the silicidation reaction is not inhibited by increasing the Si ratio, a low-resistance silicide electrode can be formed.
Normally, the silicidation reaction is performed in a two-stage reaction as shown in FIGS. 1B to 1C in order to prevent silicidation of the metal layer 4 on the sidewall.
[0019]
Further, since the Si _v (Ge _w C _1-w ) _1-v layer 3 needs to be completely silicided, the thickness of the Si _v (Ge _w C _1-w ) _1-v layer 3 is determined by deposition. This is determined by the thickness of the metal layer 4 to be formed.
[0020]
( 2 ) Further, in the above (1) , the present invention provides that the composition ratio of Ge in the Si _x (Ge _y C _1-y ) _1-x layer 2 after the heat treatment becomes a predetermined value before the heat treatment. The composition ratio of the Si _x (Ge _y C _1-y ) _1-x layer 2 is set to be smaller than a predetermined value in advance in consideration of the diffusion of Ge from the Si _v (Ge _w C _1-w ) _1-v layer 3. It is characterized by doing.
[0021]
In the silicidation reaction of the Si _v (Ge _w C _1-w ) _1-v layer 3, Ge that does not form a compound diffuses to the Si _x (Ge _y C _1-y ) _1-x layer 2 side, and Si _Since the composition ratio of the _x (Ge _y C _{1 -y} ) _{1 -x} layer 2 is changed, the composition ratio of the Si _x (Ge _y C _{1 -y} ) _{1 -x} layer 2 provided on the semiconductor 1 side is the same as that of Ge. In consideration of diffusion, it is necessary to make the Ge composition ratio smaller than the composition ratio to be finally obtained. In this case, the composition ratio depends on the thickness of the metal layer 4 to be deposited and Si _v (Ge _w C _1-w ) Determined by the composition ratio and film thickness of the _1-v layer 3.
[0022]
DETAILED DESCRIPTION OF THE INVENTION
Here, a first embodiment of the present invention will be described with reference to FIGS.
2A. First, an n-type silicon substrate 11 is selectively oxidized to form an element isolation oxide film 12, and then B is introduced into the element formation region to form a p-type well region 13. FIG. Next, after forming an insulating film on the surface of the p-type well region 13, an n ⁺ -type polycrystalline Si film is deposited and patterned to form the gate insulating film 14 and the gate electrode 15.
Next, an n-type LDD (Lightly Doped Drain) region 16 is formed by ion implantation of As using the gate electrode 15 as a mask, and then an SiO ₂ film is deposited on the entire surface, and anisotropic etching is performed to form a sidewall. 17 is formed.
Next, the n ⁺ -type source region 18 and the n ⁺ -type drain region 19 are formed by ion implantation of As with higher energy using the gate electrode 15 and the sidewall 17 as a mask, thereby forming a basic configuration of the n-channel MOSFET. The part is completed.
[0023]
Next, the whole is cleaned by cleaning, and then exposed on the exposed gate electrode 15, n ⁺ -type source region 18, and n ⁺ -type drain region 19 by selective CVD using SiH ₄ and GeH _4. A Si _0.53 Ge _0.47 layer 20 having a thickness of 10 to 60 nm, for example, 30 nm and an As concentration of, for example, 5 × 10 ²⁰ cm ⁻³ , is subsequently deposited; For example, a Si _0.9 Ge _0.1 layer 21 having a concentration of 3 × 10 ¹⁹ cm ⁻³ is deposited.
In this case, since Ge is contained in the growth gas atmosphere, good selective growth is possible, and it is not deposited on the insulating film such as the element isolation oxide film 12.
In order to make the final composition ratio of the SiGe layer in contact with the n ⁺ -type source region 18 and the n ⁺ -type drain region 19 into an Si _0.5 Ge _0.5 layer, an Si _0.53 Ge _0.47 layer 20 is formed in consideration of Ge diffusion. Yes.
[0024]
Next, referring to FIG. 2B, a Co layer 22 having a thickness of, for example, 10 nm is deposited on the entire surface by sputtering.
In this case, the thickness of the Co layer 22 is determined by the required thickness of the silicide layer, and the thickness of the Si _0.9 Ge _0.1 layer 21 is determined by the thickness of the Co layer 22. It will be.
[0025]
Next, by performing rapid thermal annealing (RTA) in a N ₂ atmosphere at a temperature of 400 to 600 ° C., for example, 500 ° C., for 10 to 900 seconds, for example, 30 seconds. Then, the Co layer 22 and the Si _0.9 Ge _0.1 layer 21 are reacted to form a CoSi layer 23.
In this case, the Co layer 22 deposited on the insulating films such as the element isolation oxide film 12 and the sidewalls 17 remains unreacted as unreacted Co layers 24 and 25.
If a heat treatment is performed at a higher temperature for a longer time, a CoSi ₂ layer having a low resistance phase can be formed. However, the Co layer 22 deposited on the exposed surface of the sidewall 17 is also silicided to form the gate electrode 15 and the n ⁺ -type source. Since the region 18 and the n ⁺ -type drain region 19 are short-circuited, it is not desirable.
[0026]
Next, referring to FIG. 3D, unreacted Co layers 24 and 25 are removed by etching for 20 minutes with a mixed solution of H ₂ SO ₄ : H ₂ O ₂ = 3: 1.
[0027]
Next, refer to FIG. 3 (e). Then, in the N ₂ atmosphere, the RTA treatment is performed at a temperature of 700 to 900 ° C., for example, 800 ° C., for 10 to 900 seconds, for example, 30 seconds, thereby performing the CoSi layer 23 and the remaining Si. _{The 0.9} Ge _0.1 layer 21 is reacted to form a low resistance phase CoSi ₂ layer 26.
[0028]
In this RTA process, Si _0.9 Ge Ge in _0.1-layer 21 is diffused into the Si _0.53 Ge _0.47 layer 20 side without reacting with Co, Si _0.53 Ge _0.47 layer 20 Si _0.5 Ge _0.5 layer by changing the composition ratio of 27 It becomes.
Therefore, the composition ratio of the Si _1-x Ge _x layer deposited on the side in contact with the n ⁺ -type source region 18 and the n ⁺ -type drain region 19 needs to be reduced in advance in view of Ge diffusion. There is, the extent to reduce are those determined by the composition ratio and the thickness of the Si _1-x Ge _x layer on the side to react silicidation, also, _the Si _1-x Ge _x layer on the side to react silicidation Therefore, the composition ratio of the Si _1-x Ge _x layer in contact with the n ⁺ -type source region 18 and the n ⁺ -type drain region 19 depends on the thickness of the Co layer 22. Will depend.
[0029]
Thus, in the first embodiment of the present invention, the final composition ratio of the Si _1-x Ge _x layer in contact with the n ⁺ type source region 18 and the n ⁺ type drain region 19 is Si _0.5 Ge _0.5 layer. since Ensure a 27, it is possible to reduce the height of the silicide layer / Si _1-x Ge _x layer interface of the Schottky barrier, reducing the contact resistance of the silicide layer / Si _1-x Ge _x layer interface Can be made.
[0030]
In addition, since the Si _1-x Ge _x layer that reacts with the Co layer 22 to form a silicide layer is a Si _0.9 Ge _0.1 layer 21 having a Ge ratio as small as 0.1, the silicidation reaction is inhibited by Ge. Since the low-resistance phase CoSi ₂ layer 26 can be formed, the resistance of the entire source / drain electrode can be reduced.
[0031]
Further, since the heat treatment for silicidation in two stages, without Co layer deposited on the side walls 17 is silicided, since it is removed in the etching step of the Co layer, n ⁺ -type source region 18 In addition, the n ⁺ -type drain region 19 and the gate electrode 15 are not short-circuited via the silicide layer.
[0032]
Next, a second embodiment of the present invention will be described with reference to FIGS.
Referring to FIG. 4A, first, the basic components of the n-channel MOSFET are formed in the same manner as in the first embodiment, and then the whole is cleaned by cleaning, and then SiH ₄ and GeH ₄ are used. On the exposed gate electrode 15, n ⁺ -type source region 18, and n ⁺ -type drain region 19, the thickness is 10 to 60 nm, for example, 30 nm, and the As concentration is, for example, A Si _0.53 Ge _0.47 layer 20 having a thickness of 5 × 10 ²⁰ cm ⁻³ is deposited, and subsequently a Si _0.9 Ge _0.1 layer 21 having a thickness of, for example, 51 nm and an As concentration of, for example, 3 × 10 ¹⁹ cm ^−3. To deposit.
[0033]
Next, referring to FIG. 4B, a Ti layer 28 having a thickness of, for example, 30 nm is deposited on the entire surface by sputtering.
In this case, the thickness of the Ti layer 28 is also determined by the required thickness of the silicide layer, and the thickness of the Si _0.9 Ge _0.1 layer 21 is determined by the thickness of the Ti layer 28. It will be.
[0034]
Next, by performing rapid thermal annealing (RTA) in a N ₂ atmosphere at a temperature of 650 to 750 ° C., for example, 700 ° C., for 10 to 900 seconds, for example, 30 seconds. The TiN layer 30 is formed on the surface of the Ti layer 28, and the Ti layer 28 and the Si _0.9 Ge _0.1 layer 21 are reacted to form a TiSi ₂ layer 29 made of C-49, which is a metastable low-temperature phase crystal. .
In this case, the silicidation reaction of the Ti layer 28 deposited on the exposed surface of the sidewall 17 is suppressed by performing the heat treatment in the N ₂ atmosphere to form the TiN layer 30, so that the gate electrode 15 and the n ⁺ type are formed. A short circuit between the source region 18 and the n ⁺ -type drain region 19 can be prevented.
In this case as well, the Ti layer 28 on the insulating film remains the unreacted Ti layers 31 and 33, and the unreacted Ti layer 32 may remain on the TiSi ₂ layer 29 in some cases.
[0035]
Next, referring to FIG. 5D, the TiN film 30 and the unreacted Ti layers 31 and 33 are removed using a mixed solution of H ₂ SO ₄ : H ₂ O ₂ = 3: 1 as an etching solution.
If some of the unreacted Ti layer 32 remains on the TiSi ₂ layer 29, it is removed at the same time as the unreacted Ti layers 31 and 33 are removed.
[0036]
Next, referring to FIG. 5 (e), rapid thermal annealing (RTA) is performed in an Ar atmosphere at a temperature of 750 to 900 ° C., for example, 800 ° C., for 10 to 600 seconds, for example, 30 seconds. The silicide electrode is completed by converting the TiSi ₂ layer 29 made of C-49 in the low temperature phase into the TiSi ₂ layer 34 made of C-54 in the stable and low resistance high temperature phase.
[0037]
Again, in the RTA process, Si _0.9 Ge Ge in _0.1-layer 21 is diffused into the Si _0.53 Ge _0.47 layer 20 side without reacting with Ti, Si _0.53 Ge Si _0.5 by changing the composition ratio of _0.47 layer 20 Ge _0.5 layer 27 is formed.
Therefore, the composition ratio of the Si _1-x Ge _x layer deposited so as to be in contact with the n ⁺ -type source region 18 and the n ⁺ -type drain region 19 is the composition ratio of the Si _1-x Ge _x layer on the silicidation reaction side. It depends on the thickness and the thickness of the Ti layer 28.
[0038]
Thus, in the second embodiment of the present invention, the final composition ratio of the Si _1-x Ge _x layer in contact with the n ⁺ type source region 18 and the n ⁺ type drain region 19 is Si _0.5 Ge _0.5 layer. since Ensure a 27, the silicide layer / Si _1-x Ge _x layer height of the interface of the Schottky barrier is lowered, reducing the contact resistance of the silicide layer / Si _1-x Ge _x layer interface Can do.
[0039]
In addition, since the Si _1-x Ge _x layer that reacts with the Ti layer 28 to form a silicide layer is a Si _0.9 Ge _0.1 layer 21 having a Ge ratio as small as 0.1, the silicidation reaction is inhibited by Ge. Therefore, the TiSi ₂ layer 29 having a sufficient thickness, and thus the TiSi ₂ layer 34 having a sufficient thickness can be formed, and the resistance of the entire source / drain electrode can be reduced.
[0040]
Although the embodiments of the present invention have been described above, the present invention is not limited to the configurations and conditions described in the embodiments, and various modifications can be made.
For example, in the description of each of the above embodiments, the final composition of the Si _1-x Ge _x layer in contact with the source / drain regions is Si _0.5 Ge in consideration of lattice matching and reduction in the height of the Schottky barrier. _Although it is set to be _0.5 , it is not necessarily Si _0.5 Ge _0.5 , the composition ratio is arbitrary, and the lattice mismatch becomes larger as x becomes larger, so that epitaxial growth becomes difficult and it may become polycrystalline. On the other hand, when x becomes small, lattice matching can be obtained, but the height of the Schottky barrier becomes high.
[0041]
In each of the above embodiments, the composition of the Si _1-x Ge _x layer to be silicided is Si _0.9 Ge _0.1 , but it is not necessarily Si _0.9 Ge _0.1 , and it is not necessarily Si _0.9 Ge _0.1. Any Si-rich layer than the _1-x Ge _x layer may be used, and Si (x = 0) may be used. However, in the case of Si, selective growth becomes difficult.
However, considering the required thickness of the silicide layer, it is desirable that x ≦ 0.4, that is, Si / Ge ≧ 1.5.
[0042]
Further, in each of the above embodiments, the layer containing Si and Ge is configured as Si _1-x Ge _x , but C is added to form a Si _x (Ge _y C _1-y ) _1-x layer. Is also good.
That is, by adding C having a small atomic radius, the size of the atomic radius of Ge can be offset, and thereby lattice matching with Si constituting the source / drain region can be achieved. The degree of freedom can be increased.
Note that the composition ratio (1-y) (1-x) of C is about 0.05 (5.0%) or less, and the forbidden band width is rather reduced by the inclusion of C. Will not be high.
[0043]
Further, in each of the above embodiments, the Si _1-x Ge _x layer is selected so that lattice matching is possible, and a single crystal is grown, but it is not necessarily a single crystal, It may be polycrystalline, amorphous, or a film in which polycrystalline and amorphous are mixed.
However, in terms of lowering resistance, a single crystal is preferable.
[0044]
In each of the above embodiments, the Si _1-x Ge _x layer is selectively grown using the CVD method. However, the CVD method is not necessarily used, and a sputtering method or a vapor deposition method may be used. Is.
Furthermore, after depositing the Si layer, Ge may be ion-implanted to form the Si _1-x Ge _x layer. Conversely, after depositing the Ge layer, Si is ion-implanted to form Si _{1- An x} Ge _x layer may be formed.
[0045]
In the description of each of the above embodiments, a Co layer or a Ti layer from which a low-resistance silicide layer is obtained is used as a metal layer to be silicided, but is not limited to Co or Ti. Pt, W, etc. may be used.
However, since Ni silicide is a low-resistance silicide that is formed at a medium temperature but is unstable, if it is accompanied by a high-temperature process after the formation of a low-resistance phase silicide, it changes to a high-resistance silicide. Attention is required.
W silicide is thermally stable, but has a relatively high resistance, and Pt exhibits intermediate characteristics.
[0046]
In the description of each of the above embodiments, the metal layer to be silicided is formed by the sputtering method. However, the sputtering is not necessarily performed, and the resistance is changed depending on the melting point, vapor pressure, etc. of the metal used. A vapor deposition method by heating, an electron beam vapor deposition method, a CVD method, or the like may be used.
[0047]
In the first embodiment, the two RTA processes are performed in the N ₂ atmosphere. However, the N ₂ atmosphere is not necessarily used, and other inert gas such as Ar is used. Is also good.
[0048]
In each of the above-described embodiments, the n-channel MOSFET is described. However, the present invention is naturally applied to a p-channel MOSFET. In this case, each Si _1-x Ge _{x is applied.} The layer may be doped with a p-type impurity such as B as an impurity.
[0049]
In each of the above embodiments, the contact electrode for the source / drain electrode and the gate electrode is described. However, the contact electrode is not necessarily limited to the contact electrode of the MOS type semiconductor device, but the emitter of the bipolar type semiconductor element. It can also be used as a contact electrode for various semiconductor elements including an electrode, a base electrode, and a collector electrode.
[0050]
Furthermore, it is not necessarily limited to the contact electrode, but may be the gate electrode itself.
In that case, after depositing a Si _1-x Ge _x layer on the side in contact with the gate insulating film and patterning it as a gate electrode, a Si _1-y Ge _y layer (x> y) to be silicided can be selectively grown. It ’s fine.
However, the composition ratio of the gate electrode changes due to the solid phase diffusion of Ge accompanying silicidation, and the threshold voltage V _th also changes accordingly. Therefore, in consideration of such a solid phase diffusion amount of Ge, gate insulation It is necessary to control the composition ratio of the Si _1-x Ge _x layer in contact with the film.
[0051]
【The invention's effect】
According to the present invention, when a silicide contact electrode is formed in a semiconductor region such as a source / drain region, a low resistance phase silicide layer is formed by using a Si _1-x Ge _x layer having a different composition ratio. Therefore, it is possible to form a low-resistance contact electrode without increasing the manufacturing time and causing a short circuit between the electrodes. As a result, it greatly contributes to improving the performance and manufacturing yield of highly integrated semiconductor devices.
[Brief description of the drawings]
FIG. 1 is an explanatory diagram of a basic configuration of the present invention.
FIG. 2 is an explanatory diagram of the manufacturing process up to the middle of the first embodiment of the present invention.
FIG. 3 is an explanatory diagram of the manufacturing process from FIG. 2 onward according to the first embodiment of the present invention.
FIG. 4 is an explanatory diagram of the manufacturing process up to the middle of the second embodiment of the present invention.
FIG. 5 is an explanatory diagram of the manufacturing process after FIG. 4 according to the second embodiment of the present invention.
FIG. 6 is an explanatory diagram of a conventional process for forming a Co silicide electrode.
FIG. 7 is an explanatory diagram of a conventional Ti silicide electrode forming process.
FIG. 8 is an explanatory diagram of a problem in a conventional silicide electrode formation process.
[Explanation of symbols]
1 semiconductor _{2 Si x (Ge y C 1} -y) 1-x layer _{3 Si v (Ge w C 1} -w) 1-v layer 4 metal layer 5 metal compound layer 6 metal compound layer 11 n-type silicon substrate 12 element Isolation oxide film 13 p-type well region 14 gate insulating film 15 gate electrode 16 n-type LDD region 17 sidewall 18 n ⁺ type source region 19 n ⁺ type drain region 20 Si _0.53 Ge _0.47 layer 21 Si _0.9 Ge _0.1 layer 22 Co layer 23 CoSi layer 24 Unreacted Co layer 25 Unreacted Co layer 26 CoSi ₂ layer 27 Si _0.5 Ge _0.5 layer 28 Ti layer 29 TiSi ₂ layer 30 TiN layer 31 Unreacted Ti layer 32 Unreacted Ti layer 33 Unreacted Ti layer 34 TiSi ₂ layers

Claims (2)

On the semiconductor, a Si _x (Ge _y C _1-y ) _1-x layer and a Si _v (Ge _w C _1-w ) _1-v layer (where 0 <x <v <1, 0 <y ≦ 1, After sequentially depositing 0 <w ≦ 1), a metal layer is deposited on the Si _v (Ge _w C _1-w ) _1-v layer, and a metal compound is formed by heat treatment to form a metal silicide electrode. A method for manufacturing a semiconductor device, wherein the Si composition ratio v in the Si _v (Ge _w C _1-w ) _1-v layer is v ≧ 0.6, and the C composition ratio (1-x) (1-y) And (1-w) (1-v) is set to 0.05 or less, and the thickness of the Si _v (Ge _w C _1-w ) _1-v layer is completely silicided by reaction with the metal layer. A method for manufacturing a semiconductor device, characterized in that the thickness is set to a thickness to be realized. As described above _{Si x (Ge y C 1-} y) Ge composition ratio in the _1-x layer after heat treatment becomes a predetermined value, the Si _x before the heat treatment _{(Ge y C 1-y)} 1-x 2. The semiconductor device according to claim 1, wherein the composition ratio of the layer is set to be smaller than the predetermined value in advance in consideration of diffusion of Ge from the Si _v (Ge _w C _1-w ) _1-v layer. Production method.

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