JPH10229052A - Semiconductor integrated circuit device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide the manufacture of a semiconductor integrated circuit device which has a low-resistant diffusion layer resistor and a low-resistant contact. SOLUTION: A MOSFET Qn, which has a gate electrode 6 and source and drain regions consisting of an n<-> semiconductor region 7 and an n<+> - semiconductor region 8, is made on a semiconductor substrate 1 which has a field insulating film 2, a p-well 3, and a channel stopper 4, and a stacked film where a cobalt film is stacked, after stacking of a titanium film has been made, and first heat treatment is applied to make a thin epitaxial cobalt silicide film on the surfaces of the gate electrode 6 and the n<+> -semiconductor region 8. Next, the titanium film and the cobalt film are removed, and then a cobalt film is stacked, and second heat treatment is applied to make an epitaxial silicide layer 10 which has a film thickness of 30-50nm.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a technology for manufacturing a semiconductor integrated circuit device, and more particularly to a technology effective when applied to a highly integrated silicon semiconductor integrated circuit device requiring high-speed operation.

[0002]

2. Description of the Related Art In a silicon semiconductor integrated circuit device with a high degree of integration, especially in a logic semiconductor integrated circuit device such as an MPU which requires a high-speed operation, an increase in contact resistance and diffusion layer resistance is a problem. .

[0003] As one of the methods for solving such a problem, for example, November 20, 1995, a press journal published, "Monthly Semiconductor World", January 1995
As described in the February issue, pages 150 to 165, a so-called salicide process is known.

In the salicide process, after forming an element isolation structure between elements using a field oxide film or the like, a metal film such as Ti is deposited on an exposed diffusion layer on the main surface of the semiconductor substrate, and a heat treatment is performed. This is a technique for silicidizing the silicon surface by silicidizing the diffusion layer portion on the surface and the surface portion of the gate electrode, and removing the unreacted metal film by wet etching. According to the salicide process, the resistance of the diffusion layer can be reduced due to the influence of silicide, and the contact resistance can be further reduced.

However, in the titanium silicide conventionally used, when the wiring becomes finer and the line width becomes about 0.3 μm, there arises a problem that the process window for forming the C54 phase, which is a low resistance phase, becomes narrower. . That is,
When the line width is about 0.3 μm, the temperature at which the phase transition from the C49 phase which is a high resistance phase to the C54 phase which is a low resistance phase increases, while the temperature at which aggregation occurs decreases. That is, it is difficult to control the temperature for forming the C54 phase, which is a low resistance phase.

In addition, increasing the thickness of the salicide layer to compensate for the increase in the resistance of the salicide layer has the disadvantage that pn junction leakage is likely to occur at the interface with the field insulating film.

Therefore, as described in the above-mentioned document, other metal salicides are being studied.

[0008] Nickel salicide cannot be used if thermal processes after the salicide step are taken into consideration due to poor thermal stability. Platinum salicide has a high resistivity and has a technical direction of thinning the impurity semiconductor region. Again, this cannot be taken into account.

On the other hand, cobalt salicide is excellent in terms of both thermal stability and resistivity, and is a material which is likely to satisfy the required performance resulting from future demand for miniaturization.

[0010]

As a result of the present inventors' investigation on such a cobalt salicide process, it has been found that the following two processes are effective.

[0011] That is, (1) a method of obtaining an epitaxial cobalt silicide by forming a thin titanium film under the cobalt film and heat-treating the film with a laminated film structure of cobalt / titanium; (2) After forming the cobalt film, After forming the cobalt monosilicide in the first heat treatment and selectively removing the unreacted cobalt film, the second heat treatment is performed at a higher temperature than the first heat treatment, and the cobalt monosilicide obtained in the first heat treatment is obtained. Is a method of obtaining cobalt disilicide of low resistance.

In the method (1), an epitaxial cobalt silicide can be obtained.
In the method (2), since cobalt disilicide is obtained, a silicide film having low resistance and excellent heat resistance can be obtained.

However, the present inventors have also recognized that there are some problems in the salicide process.

That is, in the method (1), the reaction rate of silicidation is low because an epitaxial reaction is used, and a high-temperature and long-time heat treatment is required. However, high-temperature, long-time heat treatment has a problem that bridging and encroachment in the element isolation structure are likely to occur, resulting in a narrow process window. In addition, since the reaction is carried out through the titanium film, the reaction system becomes complicated, and controllability is poor. Further, there is a problem that titanium is mixed into the cobalt silicide, thereby increasing the resistance of the cobalt silicide.

In the method (2), since the second heat treatment is performed in a state where the silicide is exposed, the surface is nitrided or oxidized at the time of the heat treatment. I do. These effects cause a problem that the resistance of lithilicide increases.

An object of the present invention is to provide a low-temperature and good controllability,
It is an object of the present invention to provide a technique capable of forming a low-resistance epitaxial silicide layer.

Another object of the present invention is to provide a technique capable of preventing nitridation and oxidation of the silicide surface and suppressing the aggregation phenomenon of the silicide layer.

Still another object of the present invention is to provide a diffusion layer resistance,
An object of the present invention is to provide a semiconductor integrated circuit device having a MISFET having a sufficiently low contact resistance.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0020]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

(1) In the method of manufacturing a semiconductor integrated circuit device according to the present invention, a semiconductor substrate having an element isolation region on its main surface and an active region surrounded by the element isolation region are formed on the main surface of the semiconductor substrate. And a MISFET including an impurity semiconductor region formed on the main surface of the semiconductor substrate on both sides of the gate electrode formed with the gate insulating film interposed therebetween. After forming an element isolation region on the main surface of the semiconductor substrate, a gate electrode is formed on the main surface of the active region of the semiconductor substrate via a gate insulating film, and an impurity semiconductor is formed on the main surface of the semiconductor substrate on both sides of the gate electrode Forming a region, (b) depositing a first metal film over the entire surface of the semiconductor substrate on which the gate electrode and the impurity semiconductor region are formed, and bonding energy between the first metal and silicon constituting the first metal film. Bound at lower binding energies than formate, depositing a second metal film formed of a second metal to form a silicon and silicide, (c) first and second
Performing a first heat treatment on the semiconductor substrate on which the metal film is deposited;
Forming a first epitaxial silicide layer of a second metal and silicon at an interface where the first metal film and silicon are in contact with each other; (d) removing the first and second metal films that have not reacted in the above step; e) depositing a third metal film made of the same material as the second metal on the entire surface of the semiconductor substrate from which the unreacted first and second metal films have been removed, and (f) depositing the third metal film Subjecting the semiconductor substrate to a second heat treatment to form a second epitaxial silicide layer made of the same material as the first epitaxial silicide layer at the interface between the first epitaxial silicide layer and the third metal film; (g) the step And removing the unreacted third metal film.

According to such a method of manufacturing a semiconductor integrated circuit device, in the steps (a) to (d), the second metal silicide layer is formed on the surface of the gate electrode or the impurity semiconductor region by using the salicide technique. In forming the first metal layer, a first metal layer is formed between the second metal and the silicide formation surface, and a metal having a binding energy larger than that of the second metal and silicon is selected as the first metal. An epitaxial silicide layer can be formed using the first metal film as a transport layer, and the first epitaxial silicide layer can be formed. In the steps (e) to (g), the first epitaxial silicide layer
Since the third metal film made of the same material as the second metal is formed and the second heat treatment is performed, the second epitaxial silicide layer having a larger thickness can be formed with a low impurity concentration.

That is, at the time of the first heat treatment, it is sufficient that a thin epitaxial film as a nucleation film required for epitaxial growth at the time of the second heat treatment is formed.
At the time of the second heat treatment, since the nucleation film has already been generated, the first metal as the transport layer is not required.
Even if the third metal film is formed directly on the first epitaxial silicide layer, the second epitaxial silicide layer can be formed. At this time, since the first metal film does not exist, the reaction speed of the second epitaxial silicide layer is high, and the second epitaxial silicide layer can be formed at a low temperature in a short time. Further, since the first metal film does not exist, the first metal does not enter the second epitaxial silicide layer as an impurity.

As a result, the reaction time for the first heat treatment can be shortened, and the cause of defects such as bridging or encroachment can be suppressed. Further, at the time of the second heat treatment, an epitaxial silicide layer having a sufficient film thickness and containing no impurities can be formed. Furthermore, a MISFET with sufficiently low diffusion layer resistance and contact resistance with good controllability can be formed.

Incidentally, titanium can be exemplified as the first metal, and cobalt can be exemplified as the second and third metals.

Further, the first and second heat treatments can be performed at a processing temperature of 700 ° C. or less and a processing time of 2 minutes or less. That is, both the processing temperature and the processing time can be lowered and shortened as compared with the conventional heat treatment of the epitaxially grown film which requires annealing at 650 to 700 ° C. for 5 to 10 minutes.

(2) In the method of manufacturing a semiconductor integrated circuit device according to the present invention, a semiconductor substrate having an element isolation region on its main surface and an active region surrounded by the element isolation region are formed on the main surface of the semiconductor substrate. And a MISFET including an impurity semiconductor region formed on a main surface of a semiconductor substrate on both sides of the gate electrode, and a MISFET including an impurity semiconductor region formed on both sides of the gate electrode. After forming an element isolation region on the main surface of the semiconductor substrate, a gate electrode is formed on the main surface of the active region of the semiconductor substrate via a gate insulating film, and an impurity semiconductor is formed on the main surface of the semiconductor substrate on both sides of the gate electrode. Forming a region, (b) over the entire surface of the semiconductor substrate on which the gate electrode and the impurity semiconductor region are formed,
Depositing a fourth metal film made of a fourth metal forming silicide with silicon, and a fifth metal film made of a fifth metal that does not react with the silicide of the fourth metal film;
(C) performing a third heat treatment on the semiconductor substrate on which the fourth and fifth metal films are deposited to form a first silicide layer with silicon at an interface where the fourth metal film and silicon are in contact;
(D) a step of removing the unreacted fourth metal film and the fifth metal film in the above step, and (e) an unreacted fourth metal film and the fifth metal film.
Depositing a sixth metal film made of a sixth metal that does not react with the first silicide layer on the entire surface of the semiconductor substrate from which the metal film has been removed; (f) forming a fourth metal film on the semiconductor substrate on which the sixth metal film has been deposited; Performing a heat treatment to form a second silicide layer made of the same element as the first silicide layer and having a lower resistance than the first silicide layer; (g) selectively removing the sixth metal film Performing the steps of:

According to such a method of manufacturing a semiconductor integrated circuit device, when the first silicide layer is formed in the steps (a) to (d), the first silicide layer which does not react with the silicide on the fourth metal film is formed. Since the fifth metal film is deposited and the third heat treatment is performed, the fourth metal is cut off from the atmosphere, and the heat treatment can be performed without reacting with the atmosphere. In addition, since the fifth metal film is deposited, the surface of the silicide layer of the fourth metal is not in a free-stand state, but is fixed by the fifth metal. As a result, aggregation of the fourth metal silicide layer hardly occurs, and the silicide layer of the fourth metal can be formed as a continuous film without aggregation. Such a situation similarly applies to the case where the second silicide layer is formed in the steps (e) to (g), and the sixth metal film which does not react with the first silicide layer is deposited on the first silicide layer. Since the fourth heat treatment is performed, the first silicide layer is shielded from the atmosphere, the heat treatment can be performed without reacting with the atmosphere, and no aggregation occurs in the second silicide layer formed by the heat treatment.

As a result, a silicide layer having no oxide or nitride formed by the reaction with the atmosphere can be formed stably without causing aggregation, and a MISFET having sufficiently low diffusion layer resistance and contact resistance can be obtained. Can be manufactured.

Further, in the present invention, after the third heat treatment,
Since the fourth heat treatment is performed by removing the unreacted fourth and fifth metal films, the fourth heat treatment is performed by removing even a small amount of oxide or nitride generated by the third heat treatment. In addition, oxidation or nitridation of the silicide layer can be more effectively prevented.

Incidentally, cobalt can be exemplified as the fourth metal, and titanium nitride, tungsten or molybdenum can be exemplified as the fifth and sixth metals. In the case of forming cobalt silicide, it is recognized that production by the production method of the present invention is more effective, considering that cobalt is a substance which is particularly easily oxidized.

(3) The semiconductor integrated circuit device of the present invention is formed in a semiconductor substrate having an element isolation region on its main surface and in an active region surrounded by the element isolation region, and has a gate insulating film on the main surface of the semiconductor substrate. A MISFET including an impurity semiconductor region formed on the main surface of the semiconductor substrate on both sides of the gate electrode formed on the film, and a metal silicide on the surface of the impurity semiconductor region or the surface of the gate electrode. A semiconductor integrated circuit device having a low resistance layer formed thereon, wherein the low resistance layer is an epitaxial growth layer made of cobalt silicide having a thickness of 30 nm or more.

According to such a semiconductor integrated circuit device, since the low resistance layer is an epitaxially grown layer made of cobalt silicide having a thickness of 30 nm or more, the semiconductor integrated circuit having the MISFET having sufficiently low diffusion layer resistance and contact resistance is provided. It can be a circuit device.

Such a semiconductor integrated circuit device is manufactured by the manufacturing method (1). However, in the conventional epitaxial growth method, when an epitaxial growth layer made of cobalt silicide having a large thickness is to be formed, A long-time, high-temperature heat treatment was required, bridging or encroachment was inevitable, and an epitaxial cobalt silicide layer of 30 nm or more could not be formed. The present invention has made this possible.

(4) The semiconductor integrated circuit device of the present invention is formed in a semiconductor substrate having an element isolation region on its main surface and in an active region surrounded by the element isolation region, and has a gate insulating layer on the main surface of the semiconductor substrate. A MISFET including an impurity semiconductor region formed on the main surface of the semiconductor substrate on both sides of the gate electrode formed on the film, and a metal silicide on the surface of the impurity semiconductor region or the surface of the gate electrode. Semiconductor device having a low-resistance layer formed thereon, wherein the low-resistance layer is a flat film made of cobalt disilicide that does not have an oxide layer or a nitride layer on its surface and is not in an aggregated state. It is.

According to such a semiconductor integrated circuit device,
The low-resistance layer has no oxide or nitride layer on its surface,
In addition, since it is a flat film made of cobalt disilicide that is not in an aggregated state, a semiconductor integrated circuit device having a MISFET having sufficiently low diffusion layer resistance and contact resistance can be obtained.

Such a semiconductor integrated circuit device is manufactured by the manufacturing method (2). However, in order to form cobalt disilicide having a low resistivity by a conventional forming method, the temperature is set to 700 ° C. or more. Requires heat treatment, cannot be prevented from nitriding or oxidizing, and tends to cause an aggregation phenomenon. Therefore, it was not possible to form a flat film made of cobalt disilicide which did not have an oxide layer or a nitride layer on its surface and was not in an aggregated state, but the present invention has made this possible. .

[0038]

Embodiments of the present invention will be described below in detail with reference to the drawings. In all the drawings for describing the embodiments, members having the same functions are denoted by the same reference numerals, and the repeated description thereof will be omitted.

Embodiment 1 FIG. 1 shows an example of a semiconductor integrated circuit device according to an embodiment of the present invention.
(A) is a plan view, and (b) of FIG.
It is b sectional drawing.

The semiconductor integrated circuit device according to the first embodiment is
For example, a semiconductor integrated circuit device made of CMOS may be used, but a pMOS or nMOS may be used.
Here, the nMOS unit will be described for convenience of description. The pMOS section is the same as the nMOS section.

The semiconductor integrated circuit device according to the first embodiment is
The semiconductor device has a MOSFET Qn in an active region surrounded by a field insulating film 2 formed on a main surface of a semiconductor substrate 1.

The semiconductor substrate 1 is an n ⁻ -type substrate doped with an n-type impurity such as phosphorus at a low concentration, and has a resistance of several Ω · cm.
Having the following resistivity.

A p-well 3 is formed near the main surface of semiconductor substrate 1. The p well 3 is lightly doped with a p-type impurity such as boron.

Field insulating film 2 has an element isolation structure for electrically isolating elements, for example, LOCOS.
It is formed by a method. The film thickness is, for example, 400 nm.
It can be. Note that a channel stopper 4 doped with an n-type impurity at a high concentration is formed below the field insulating film 2.

The MOSFET Qn has a gate electrode 6 formed on the main surface of the active region with a gate insulating film 5 interposed therebetween.
And source / drain regions formed on the main surface of the active region on both sides of the gate electrode 6. The source / drain regions include an n ⁻ semiconductor region 7 doped with an n-type impurity at a low concentration and an n ⁺ semiconductor region 8 doped at a high concentration with an n-type impurity. That is, the source / drain regions have a so-called LDD (Lightly Doped Drain) structure.

Gate insulating film 5 is made of, for example, a silicon oxide film formed by a thermal CVD method, and has a thickness of 5 to 1
It can be 0 nm. Further, gate electrode 6 can be a polycrystalline silicon film formed by, for example, a CVD method. On the side surface of the gate electrode 6, a side wall 9 made of, for example, a silicon oxide film is formed.

An epitaxial silicide layer 10 made of cobalt silicide is formed on the surfaces of gate electrode 6 and n ⁺ semiconductor region 8, and has a thickness of 30 to 5 nm.
0 nm. Conventionally, if the thickness of an epitaxially grown layer of cobalt silicide is increased to 30 to 50 nm, a cause of device failure such as bridging or encroachment occurs, and a thick epitaxial silicide layer cannot be obtained. 6 or n
^{+ Although} the resistance value of the semiconductor region 8 could not be sufficiently reduced, the semiconductor integrated circuit device of the first embodiment uses a manufacturing method described later to increase the resistance by 30 to 50.
nm thick epitaxial silicide layer 10, the gate electrode 6 and the n ⁺ semiconductor region 8 can be formed.
Can be sufficiently reduced. Therefore, the performance of the semiconductor integrated circuit device can be improved without causing any element failure cause such as bridging or encroachment.

[0048] MOSFETQn and an upper layer of the field insulating film 2 is formed an interlayer insulating film 11, n ⁺ epitaxial silicide through contact holes 12 opened in the interlayer insulating film 11 on the semiconductor regions 8 on n ⁺ semiconductor region 8 Layer 10
Is formed.

The interlayer insulating film 11 is made of, for example, a silicon oxide film and can be formed by a CVD method using TEOS (tetraethoxysilane). The wiring 13 is
For example, it is made of an aluminum alloy containing aluminum as a main component, and can be formed by a sputtering method.

A protective insulating film 14 is formed on the wiring 13. The protective insulating film 14 may have a laminated structure of a silicon oxide film and a silicon nitride film, for example.
It can be formed by a plasma CVD method.

In the first embodiment, a silicon oxide film is exemplified as the sidewall 9 and the interlayer insulating film 11, but it is needless to say that a silicon nitride film may be used. Further, although an aluminum alloy is illustrated as the wiring 13, a laminated film of aluminum, titanium nitride, tungsten, or the like may be used.

Next, a method of manufacturing the semiconductor integrated circuit device according to the first embodiment will be described with reference to FIGS. FIG.
10 show an example of a method of manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention in the order of steps, FIGS. 2 to 6 are cross-sectional views of main parts, and FIGS. A plan view,
(B) shows a bb sectional view in (a).

Firstly, n ^- providing a semiconductor substrate 1 in the form, after forming a thin silicon oxide film 15 on the surface thereof, depositing a silicon nitride film 16 is patterned by using a known photolithography and etching . The patterning of the silicon nitride film 16 is performed so as to remove the region where the field insulating film 2 is formed. Using the silicon nitride film 16 as a mask, an n-type impurity such as phosphorus or arsenic is ion-implanted at a high concentration to form the channel stopper 4. Further, a p-type impurity such as boron is ion-implanted into a region where the p-well 3 is to be formed, thereby forming the p-well 3 (FIG. 2).

Next, a heat treatment is performed on the semiconductor substrate 1 to selectively oxidize a region not covered with the silicon nitride film 16, thereby forming a field insulating film 2 (FIG. 3). The channel stopper 4 and the p-well 3 are activated at this stage.

Next, after removing the silicon nitride film 16 and the silicon oxide film 15, a silicon oxide film to be the gate insulating film 5 and a polycrystalline silicon film to be the gate electrode 6 are formed on the entire surface of the semiconductor substrate 1. The gate electrode 6 is formed by patterning the polycrystalline silicon film using known photolithography and etching techniques (FIG. 4).
The silicon oxide film can be formed by, for example, a thermal oxidation method, and the polycrystalline silicon film can be formed by, for example, a CVD method.

Next, the photoresist and the gate electrode 6
Is used as a mask, an n-type impurity such as arsenic or phosphorus is ion-implanted at a low concentration to form n ⁻ semiconductor region 7 (FIG. 5).

Next, a silicon oxide film is deposited on the entire surface of the semiconductor substrate 1 and is subjected to a known anisotropic etching to etch the silicon oxide film, thereby forming side walls 9 on the side surfaces of the gate electrode 6. Further, using the photoresist, the gate electrode 6 and the side wall 9 as a mask, an n-type impurity such as arsenic or phosphorus is ion-implanted at a high concentration to form an n ⁺ semiconductor region 8 (FIG. 6).

At this stage, the semiconductor substrate 1 is heat-treated,
^The semiconductor region 7 and the n ⁺ semiconductor region 8 can be activated, but heat treatment may be performed in a later step.

Next, a titanium film 17 serving as a cobalt transport film for forming cobalt silicide epitaxially is used.
(First metal film), and further, a cobalt film 18 (second
A metal film is deposited (FIG. 7). The deposition of the titanium film 17 and the cobalt film 18 can be performed by a known sputtering method, and the thickness of each can be 5 to 10 nm.

Next, the semiconductor substrate 1 is subjected to a heat treatment (first heat treatment), so that the unreacted cobalt film 18 and the titanium film 1 are not reacted.
7 is removed, and an epitaxial silicide layer 10a (the first silicide layer 10a) is formed on the surface of the gate electrode 6 and the surface of the n ⁺ semiconductor region 8.
An epitaxial silicide layer is formed (FIG. 8). Here, the titanium film 17 is exemplified as a metal film acting as a cobalt transport film. However, as long as the titanium film 17 has a larger binding energy with silicon than cobalt (second metal) forming silicide with silicon. It is not limited to titanium (first metal), but may be another metal film.

The conditions of the heat treatment are, for example, 600 ° C.
Can be 1 minute. This heat treatment condition is 650 to 7 which is a heat treatment condition for conventional epitaxial growth.
At a low temperature and for a short time compared to 00 ° C. for 5 to 10 minutes,
No bridging or encroachment, which was a conventional problem, occurs. In addition, since the heat treatment is performed at a low temperature for a short time, the incorporation of titanium into the epitaxial silicide layer 10a can be suppressed.

The cobalt film 18 and the titanium film 17
A known wet etching method can be used for the removal, but examples of the etchant include a mixed solution of ammonia and a hydrogen peroxide solution or a hydrochloric acid-based mixed acid solution. The thickness of the epitaxial silicide layer 10a is about 7 to 8 when the thickness of the cobalt film 18 is 5 nm.
In the case of 10 nm, the thickness can be 14 to 16 nm.

Next, a cobalt film 19 (third metal film) is deposited on the entire surface of the semiconductor substrate 1 without depositing a titanium film (FIG. 9). For deposition of the cobalt film 19, a known sputtering method can be used as described above. Cobalt film 1
The thickness of 9 can be, for example, 10 to 20 nm.

Next, the semiconductor substrate 1 is subjected to a heat treatment (second heat treatment), the unreacted cobalt film 19 is removed, and an epitaxial silicide layer 10b (second epitaxial silicide layer) is formed on the epitaxial silicide layer 10a. I do. The epitaxial silicide layer 10 is composed of an epitaxial silicide layer 10a and an epitaxial silicide layer 10b, and can have a thickness of 30 to 50 nm (FIG. 10). As described above, by setting the film thickness to a sufficient thickness which cannot be obtained by the conventional technique, the sheet resistance of the gate electrode 6 and the n ⁺ semiconductor region 8 is reduced, and the contact resistance with the wiring 13 is reduced. The performance of the device can be improved.

The heat treatment conditions of the second heat treatment are, for example,
600 ° C. for 1 minute. This is the conventional heat treatment condition for epitaxial growth of 650-7.
At a low temperature and for a short time compared to 00 ° C. for 5 to 10 minutes,
No bridging or encroachment, which was a conventional problem, occurs. As described above, the condition of the second heat treatment can be reduced to a low temperature for a short time because the epitaxial silicide layer 10a is formed by the first heat treatment, and the epitaxial silicide layer 10a is formed by the epitaxial silicide in the second heat treatment. This is because it is a growth nucleus of the layer 10b, and the contamination of titanium is minute in the first heat treatment, and the titanium film 17 is removed in the second heat treatment, so that the film purity is improved. It is thought that it is.

Finally, an interlayer insulating film 11 is formed on the entire surface of the semiconductor substrate 1, and a connection hole 12 is opened by using a known photolithography technique and etching technique. afterwards,
For example, an aluminum alloy film is deposited on the entire surface of the semiconductor substrate 1 by a sputtering method, and the aluminum alloy film is patterned using a known photolithography technique and an etching technique to form the wiring 13. Further, the protective insulating film 1
The semiconductor integrated circuit device shown in FIG. The interlayer insulating film 11 contains TEOS and oxygen for about 7
The protection insulating film 14 can be formed by a plasma CVD method by a CVD method in which a reaction is performed at a processing temperature of about 40 ° C.

According to such a method of manufacturing a semiconductor integrated circuit device, the above-described semiconductor integrated circuit device can be manufactured, and the gate electrode 6 and n ^{+ of the} semiconductor integrated circuit device can be manufactured.
The sheet resistance and the contact resistance of the semiconductor region 8 can be reduced, and the performance can be improved. That is, the first
Forming a high-purity thin epitaxial silicide layer 10a by a heat treatment, and further forming an epitaxial silicide layer 10b by a second heat treatment so that the thickness of the epitaxial silicide layer 10 is a sufficient thickness that cannot be formed by the conventional technique. Can be formed. Moreover,
According to the above-mentioned method, the epitaxial silicide layer 10 having a sufficient thickness can be formed without causing bridging and encroachment, which cannot be avoided if an equivalent thickness is to be obtained by the conventional technique. Can be.

Further, since the mixing of titanium, which is an impurity, into the epitaxial silicide layer 10 is minimized, the resistance value of the epitaxial silicide layer 10 can be reduced.

As a result, the sheet resistance of the gate electrode 6 and the n ⁺ semiconductor region 8 can be reduced from 100 Ω / □ without the epitaxial silicide layer 10 to 5 Ω / □.

In the first and second heat treatments, a known RTA (Rapid Thermal Anneal) method can be used.

In the first embodiment, the nMOSFE
Although T has been described as an example, a pMOSFET can be similarly manufactured by setting the conductivity type to the opposite polarity.

Further, in the first embodiment, the gate electrode 6
Although the case where epitaxial silicide layer 10 is formed on both surfaces of n ⁺ semiconductor region 8 and n ⁺ semiconductor region 8 has been exemplified, it goes without saying that it may be formed only on either gate electrode 6 or n ⁺ semiconductor region 8. .

(Embodiment 2) FIGS. 11A and 11B show an example of a semiconductor integrated circuit device according to another embodiment of the present invention. FIG. 11A is a plan view, and FIG. It is bb sectional drawing in a).

The semiconductor integrated circuit device according to the second embodiment is
As in the first embodiment, a semiconductor integrated circuit device made of CMOS may be used, but a pMOS or nMOS may be used. For convenience of explanation, an nMOS unit will be described. The pMOS section is the same as the nMOS section.

The semiconductor integrated circuit device according to the second embodiment is
As in the first embodiment, the semiconductor device has a semiconductor substrate 1, a field insulating film 2, and a MOSFET Qn. A p-well 3, a gate insulating film 5, a gate electrode 6, and n ⁻
The semiconductor region 7, the n ⁺ semiconductor region 8, and the side wall 9 are the same as in the first embodiment. Therefore,
Only the low resistance layer 20 that is different from the first embodiment will be described, and description of the other same members will be omitted.

The low-resistance layer 20 formed on the surfaces of the gate electrode 6 and the n ⁺ semiconductor region 8 has no oxide layer or nitride layer on its surface, and is a flat film made of cobalt disilicide which is not in an agglomerated state. It is. The film thickness is 3
0 to 50 nm.

Conventionally, when heat treatment is performed at a high temperature to form cobalt disilicide, it is inevitable that the surface of the cobalt disilicide is oxidized or nitrided due to the ease of reaction of cobalt. However, in the semiconductor integrated circuit device according to the second embodiment, by using a manufacturing method described later, a cobalt die having no oxide layer or nitride layer on its surface and not in an agglomerated state can be obtained. It is to be silicide. Thereby, the resistance value of the gate electrode 6 or the n ⁺ semiconductor region 8 can be sufficiently reduced, and the performance of the semiconductor integrated circuit device can be improved.

The interlayer insulating film 11, the wiring 13, and the protective insulating film 14, which are formed on the MOSFET Qn and the field insulating film 2, are the same as those in the first embodiment, and the description is omitted.

Next, a method of manufacturing the semiconductor integrated circuit device according to the second embodiment will be described with reference to FIGS. 12 to 15 show an example of a method of manufacturing a semiconductor integrated circuit device according to another embodiment of the present invention in the order of steps, wherein (a) is a plan view and (b) is (a). B in
-B shows a sectional view.

The method of manufacturing the semiconductor integrated circuit device of the second embodiment is the same as that of the first embodiment up to the step of FIG. 6 in the first embodiment. Therefore, the description is omitted,
The following steps will be described.

A cobalt film 21 (fourth metal film) is deposited on the entire surface of the semiconductor substrate 1 on which the MOSFET Qn is formed, and a titanium nitride film 22 (fifth metal film) is further deposited (FIG. 1).
2). Here, the cobalt film 21 reacts with the gate electrode 6 and the n ⁺ semiconductor region 8 to form a silicide, and the titanium nitride film 22 has a function of preventing oxidation or nitridation of cobalt in a heat treatment described later. Have.

Cobalt film 21 and titanium nitride film 22
Can be deposited using a known sputtering method. The thickness of the cobalt film 21 is 10 to 20 nm, and the thickness of the titanium nitride film 2 is
2 can have a thickness of 10 nm.

Next, a heat treatment (third heat treatment) is performed on the semiconductor substrate 1 to react the silicon in the gate electrode 6 and the n ⁺ semiconductor region 8 with the cobalt film 21 to generate a cobalt silicide 23 (first silicide layer). Then, the unreacted cobalt film 21 is removed (FIG. 13). The heat treatment condition of the third heat treatment can be 500 ° C. for 1 minute. The cobalt silicide 23 at this stage is in a state of cobalt monosilicide having a high resistance value because the heat treatment temperature is low and the heat treatment time is short. The resistivity is 70-8
0 μΩ · cm can be exemplified. The thickness of the formed cobalt silicide 23 is, for example, 25 to 40 nm.

For removing the unreacted cobalt film 21, a known wet etching method using ammonia water or the like can be used. At this time, the nitrided or oxidized layer on the surface of the cobalt silicide 23 is also removed. Can be removed. Although the formation of a nitride layer or an oxide layer on the surface of the cobalt silicide 23 is suppressed by the presence of the titanium nitride film 22, slight nitridation or oxidation is unavoidable, and such a nitride layer or an oxide layer is removed. It has been found by the present inventors that the fact that nitrogen or oxygen is mixed as an impurity in the subsequent steps and causes a reduction in the resistance value of the silicide layer. Therefore, it can be said that removing the nitride layer or the oxide layer by wet etching in this step is effective for improving the performance of the semiconductor integrated circuit device.

Next, a titanium nitride film 24 is deposited on the entire surface of the semiconductor substrate 1 (FIG. 14). The titanium nitride film 24 can be deposited by a known sputtering method.
m.

Next, the semiconductor substrate 1 is subjected to a heat treatment (fourth heat treatment) at a higher temperature than the heat treatment in the previous step, and the cobalt silicide 23 composed of cobalt monosilicide is changed to cobalt disilicide, thereby forming the low resistance layer 20. I do. Further, the titanium nitride film 24 is removed (FIG. 15).

The fourth heat treatment is performed, for example, at 700 ° C.
The heat treatment can be performed for one minute, and the resistivity of the low-resistance layer 20 generated by the heat treatment can be, for example, 15 to 17 μΩ · cm. The thickness of the formed low resistance layer 20 can be 30 to 50 nm.

At the time of the fourth heat treatment in this step, since the titanium nitride film 24 is deposited on the cobalt silicide 23, the titanium nitride film 24 has an action of preventing oxidation or nitridation of the cobalt silicide 23, and The formation of an oxide layer or a nitride layer on the surface of the low resistance layer 20 made of silicide is suppressed. In addition, in the heat treatment at a high temperature of 700 ° C., agglomeration occurs in a process in which the cobalt silicide 23 made of cobalt monosilicide changes to the low resistance layer 20 made of cobalt disilicide, and a grain boundary is formed in the low resistance layer 20. Although the resistance value is likely to be increased, the titanium nitride film 24 is deposited on the upper surface of the cobalt silicide 23, so that the physical movement of the particles is inhibited in the above-described process, so that the aggregation is less likely to occur. . As a result, the resistance value of the low resistance layer 20 can be reduced.

Finally, as in the first embodiment, an interlayer insulating film 11, a connection hole 12, a wiring 13, and a protective insulating film 14 are formed to substantially complete the semiconductor integrated circuit device shown in FIG. Since the forming method is the same as that of the first embodiment, the description is omitted.

According to such a method of manufacturing a semiconductor integrated circuit device, the above-described semiconductor integrated circuit device can be manufactured, and the gate electrode 6 and n ^{+ of the} semiconductor integrated circuit device can be manufactured.
The sheet resistance and the contact resistance of the semiconductor region 8 can be reduced, and the performance can be improved. That is, by depositing the titanium nitride film 22 and the titanium nitride film 24, a cobalt silicide 23 made of cobalt monosilicide having no oxygen or nitrogen is formed in the third heat treatment, and the surface thereof is oxidized in the fourth heat treatment. It is possible to form the low resistance layer 20 made of cobalt disilicide having no layer or nitride layer and having no aggregation. As a result, the sheet resistance of the gate electrode 6 and the n ⁺ semiconductor region 8 is reduced to 100 Ω / □ without the low resistance layer 20.
To 5Ω / □.

In the manufacturing method according to the second embodiment, since the aggregation phenomenon does not occur in the low-resistance layer 20, a silicide having a flat surface and low roughness can be formed. As a result, the process margin can be expanded.

In the first and second heat treatments, the known RTA (Rapid Thermal Anneal) method can be used, and the pMOSFET can be manufactured in the same manner as in the first embodiment. The same is true.

Further, as in the first embodiment, low-resistance layer 20 may be formed only on either gate electrode 6 or n ⁺ semiconductor region 8.

Further, in the second embodiment, an example of the cobalt silicide film formed by the reaction between cobalt and silicon has been described. However, instead of cobalt, each silicide may be formed by using titanium, nickel, platinum or the like. . Further, the case where the titanium nitride films 22 and 24 are used as the silicide oxidation or nitridation prevention film is exemplified.
Does not react with silicide during heat treatment such as molybdenum, and
Any film that can be selectively etched with silicide can be used instead of the titanium nitride films 22 and 24.

As described above, the invention made by the inventor has been specifically described based on the embodiments of the invention. However, the invention is not limited to the above embodiments, and various modifications may be made without departing from the gist of the invention. Needless to say, it can be changed.

[0096]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

(1) A low-resistance epitaxial silicide layer can be formed at a low temperature with good controllability.

(2) The nitridation and oxidation of the silicide surface can be prevented, and the aggregation phenomenon of the silicide layer can be suppressed.

(3) It is possible to provide a semiconductor integrated circuit device having a MISFET whose diffusion layer resistance and contact resistance are sufficiently low, so that the speed of the semiconductor integrated circuit device can be increased.

[Brief description of the drawings]

FIGS. 1A and 1B show an example of a semiconductor integrated circuit device according to an embodiment of the present invention, wherein FIG. 1A is a plan view, and FIG. 1B is a bb cross-sectional view in FIG.

FIG. 2 is a fragmentary cross-sectional view showing an example of a method of manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention in the order of steps;

FIG. 3 is a fragmentary cross-sectional view showing one example of a method of manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention in the order of steps;

FIG. 4 is a fragmentary cross-sectional view showing one example of a method of manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention in the order of steps;

FIG. 5 is a fragmentary cross-sectional view showing an example of a method of manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention in the order of steps;

FIG. 6 is a fragmentary cross-sectional view showing one example of a method of manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention in the order of steps;

7A and 7B show an example of a method of manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention in the order of steps, wherein FIG. 7A is a plan view and FIG. 7B is a bb cross-sectional view in FIG. .

FIGS. 8A and 8B show an example of a method of manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention in the order of steps, in which FIG. 8A is a plan view and FIG. 8B is a bb cross-sectional view in FIG. .

FIGS. 9A and 9B show an example of a method of manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention in the order of steps, in which FIG. 9A is a plan view and FIG. 9B is a bb cross-sectional view in FIG. .

FIGS. 10A and 10B show an example of a method of manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention in the order of steps, in which FIG. 10A is a plan view, and FIG. 10B is a bb cross-sectional view in FIG. .

FIGS. 11A and 11B show an example of a semiconductor integrated circuit device according to another embodiment of the present invention, wherein FIG. 11A is a plan view and FIG.
It is bb sectional drawing in.

FIGS. 12A and 12B show an example of a method of manufacturing a semiconductor integrated circuit device according to another embodiment of the present invention in the order of steps, in which FIG. 12A is a plan view, and FIG. b shows a sectional view.

13A and 13B show an example of a method of manufacturing a semiconductor integrated circuit device according to another embodiment of the present invention in the order of steps, wherein FIG. 13A is a plan view, and FIG. b shows a sectional view.

14A and 14B show an example of a method of manufacturing a semiconductor integrated circuit device according to another embodiment of the present invention in the order of steps, wherein FIG. 14A is a plan view, and FIG. b shows a sectional view.

FIGS. 15A and 15B show an example of a method of manufacturing a semiconductor integrated circuit device according to another embodiment of the present invention in the order of steps, wherein FIG. 15A is a plan view, and FIG. b shows a sectional view.

[Explanation of symbols]

Reference Signs List 1 semiconductor substrate 2 field insulating film 3 p-well 4 channel stopper 5 gate insulating film 6 gate electrode 7 n ^- semiconductor region 8 n ⁺ semiconductor region 9 sidewall 10 epitaxial silicide layer 10a epitaxial silicide layer 10b epitaxial silicide layer 11 interlayer insulating film 12 Connection hole 13 Wiring 14 Protective insulating film 15 Silicon oxide film 16 Silicon nitride film 17 Titanium film 18 Cobalt film 19 Cobalt film 20 Low resistance layer 21 Cobalt film 22 Titanium nitride film 23 Cobalt silicide 24 Titanium nitride film Qn MOSFET

Claims (7)

[Claims] A semiconductor substrate having an element isolation region on a main surface thereof; and a gate formed on an active region surrounded by the element isolation region and formed on a main surface of the semiconductor substrate via a gate insulating film. A method of manufacturing a semiconductor integrated circuit device comprising: an electrode; and a MISFET including an impurity semiconductor region formed on a main surface of the semiconductor substrate on both sides of the gate electrode, wherein (a) an element is provided on the main surface of the semiconductor substrate. After forming the isolation region, the gate electrode is formed on the main surface of the active region of the semiconductor substrate via the gate insulating film, and the impurity semiconductor region is formed on the main surface of the semiconductor substrate on both sides of the gate electrode. (B) depositing a first metal film on the entire surface of the semiconductor substrate on which the gate electrode and the impurity semiconductor region are formed, and forming a first metal forming the first metal film Depositing a second metal film composed of a second metal that forms silicide with silicon by binding with a binding energy lower than the binding energy with silicon; and (c) depositing the first and second metal films. Subjecting said semiconductor substrate to a first heat treatment to form a first epitaxial silicide layer of said second metal and silicon at an interface where said first metal film and silicon are in contact with each other; (d) said step (c) Removing the unreacted first and second metal films in (e), the same material as the second metal on the entire surface of the semiconductor substrate from which the unreacted first and second metal films have been removed. (F) subjecting the semiconductor substrate on which the third metal film has been deposited to a second heat treatment to form a third heat treatment at an interface between the first epitaxial silicide layer and the third metal film. First episode A step of forming a second epitaxial silicide layer made of the same material as the axial silicide layer; and (g) a step of removing the unreacted third metal film in the step (f). A method for manufacturing a circuit device. 2. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein said first metal is titanium, and said second and third metals are cobalt. Manufacturing method. 3. The method for manufacturing a semiconductor integrated circuit device according to claim 1, wherein the first and second heat treatments have a processing temperature of 700 ° C. or less and a processing time of 2 minutes or less. A method for manufacturing a semiconductor integrated circuit device. 4. A semiconductor substrate having an element isolation region on its main surface, and a gate formed on an active region surrounded by the element isolation region and formed on a main surface of the semiconductor substrate via a gate insulating film. A method of manufacturing a semiconductor integrated circuit device comprising: an electrode; and a MISFET including an impurity semiconductor region formed on a main surface of the semiconductor substrate on both sides of the gate electrode, wherein (a) an element is provided on the main surface of the semiconductor substrate. After forming the isolation region, the gate electrode is formed on the main surface of the active region of the semiconductor substrate via the gate insulating film, and the impurity semiconductor region is formed on the main surface of the semiconductor substrate on both sides of the gate electrode. And (b) forming a fourth metal formed of silicon and silicide on the entire surface of the semiconductor substrate on which the gate electrode and the impurity semiconductor region are formed. Depositing a metal film and a fifth metal film made of a fifth metal that does not react with the silicide of the fourth metal film; and (c) depositing a third metal film on the semiconductor substrate on which the fourth and fifth metal films are deposited. Performing a heat treatment to form a first silicide layer with silicon at an interface where the fourth metal film and silicon are in contact with each other; (d) the fourth metal film and the fifth metal film that have not reacted in the step (c) (E) forming a sixth metal film made of a sixth metal that does not react with the first silicide layer on the entire surface of the semiconductor substrate from which the unreacted fourth metal film and the fifth metal film have been removed. (F) performing a fourth heat treatment on the semiconductor substrate on which the sixth metal film has been deposited, the semiconductor substrate being made of the same element as the first silicide layer; Low-resistance second silicide layer Forming, a method of manufacturing a semiconductor integrated circuit device, which comprises a step of selectively removing (g) the sixth metal film. 5. The method of manufacturing a semiconductor integrated circuit device according to claim 4, wherein said fourth metal is cobalt, and said fifth and sixth metals are titanium nitride, tungsten or molybdenum. Of manufacturing a semiconductor integrated circuit device. 6. A semiconductor substrate having an element isolation region on a main surface thereof, and a gate formed in an active region surrounded by the element isolation region and formed on a main surface of the semiconductor substrate via a gate insulating film. An MISFET including an impurity semiconductor region formed on a main surface of the semiconductor substrate on both sides of the gate electrode, and a low-resistance layer made of metal silicide on a surface of the impurity semiconductor region or a surface of the gate electrode. Wherein the low resistance layer is an epitaxial growth layer made of cobalt silicide having a thickness of 30 nm or more. 7. A semiconductor substrate having an element isolation region on its main surface, and a gate formed on an active region surrounded by the element isolation region and formed on a main surface of the semiconductor substrate via a gate insulating film. An MISFET including an impurity semiconductor region formed on a main surface of the semiconductor substrate on both sides of the gate electrode, and a low-resistance layer made of metal silicide on a surface of the impurity semiconductor region or a surface of the gate electrode. Wherein the low-resistance layer is a flat film made of cobalt disilicide that does not have an oxide layer or a nitride layer on its surface and is not in an aggregated state. Semiconductor integrated circuit device.