JP3640079B2 - Manufacturing method of CMOS transistor - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for manufacturing a CMOS transistor , in which a semiconductor substrate and a metal film are reacted to form a compound film on a diffusion layer of an NMOS transistor and a PMOS transistor on the semiconductor substrate.
[0002]
[Prior art]
In order to suppress the short channel effect associated with the miniaturization of a semiconductor device, it is necessary to shallow the diffusion layer serving as the source / drain of the field effect transistor. As the resistance increases, it becomes difficult to manufacture a semiconductor device with high speed and low power consumption. Therefore, a structure in which a TiSi ₂ film or a CoSi ₂ film, which is a low resistance compound film of a semiconductor and a metal, is formed on a diffusion layer is considered.
[0003]
FIG. 3 shows a conventional example of a method for manufacturing a CMOS transistor having such a structure. In this conventional example, as shown in FIG. 3A, a SiO ₂ film 12 as an element isolation oxide film and a SiO ₂ film 13 as a gate oxide film are formed on the surface of a Si substrate 11, and a W polycide layer is formed. A gate electrode is formed at 14.
[0004]
Then, using the W polycide layer 14 and the SiO ₂ film 12 as a mask, As is ion-implanted at a low concentration in the formation region of the NMOS transistor, and BF ₂ is ion-implanted at a low concentration in the formation region of the PMOS transistor. A sidewall spacer of the gate electrode is formed by the _two films 15.
[0005]
Then, using the W polycide layer 14 and the SiO ₂ films 12 and 15 as a mask, As is ion-implanted at a high concentration in the formation region of the NMOS transistor, and BF ₂ is ion-implanted at a high concentration in the formation region of the PMOS transistor. Thus, an N-type diffusion layer 16 and a P-type diffusion layer 17 having an LDD structure are formed.
[0006]
Next, as shown in FIG. 3B, a natural oxide film (not shown) on the diffusion layers 16 and 17 is completely removed with hydrofluoric acid, and then a Ti film 18 is formed on the entire surface. Then, as shown in FIG. 3C, the Si substrate 11 and the Ti film 18 are reacted with each other by heat treatment to selectively form a TiSi ₂ film 19, soaked in ammonia water or the like, and the SiO ₂ film 12. The Ti film 18 remaining unreacted on 15 and the W polycide layer 14 is removed.
[0007]
Next, as shown in FIG. 3D, the interlayer insulating film 21 is formed, the connection hole 22 is formed in the interlayer insulating film 21, and the connection hole 22 is filled with the TiN / Ti film 23 and the W film 24. Then, a wiring is formed by the Ti film 25 and the Al—Si film 26, and a conventionally known process is executed to complete a CMOS transistor 29 having an NMOS transistor 27 and a PMOS transistor 28.
[0008]
[Problems to be solved by the invention]
However, with the miniaturization of the CMOS transistor 29, the line widths of the diffusion layers 16 and 17 are also reduced. On the diffusion layer 16 formed of As and having a narrow line width, FIGS. As shown in FIG. ₂ , the TiSi ₂ film 19 aggregates. Moreover, when the line width is about 0.2 μm or less, the TiSi ₂ film 19 on the diffusion layer 17 formed of B becomes a low-resistance C49 crystal, whereas the TiSi on the diffusion layer 17 formed of As. _{The two} films 19 are likely to be a high resistance C54 crystal.
[0009]
Further, the crystal grain size of the TiSi ₂ film 19 on the diffusion layer 16 formed of As is about 1/10 or less than the crystal grain size of the TiSi ₂ film 19 on the diffusion layer 17 formed of B. This is considered to be because a Ti—O—As reaction occurs simultaneously with a Ti—As reaction, and the crystal growth of the TiSi ₂ film 19 becomes insufficient on the diffusion layer 16. The TiSi ₂ film 19 having a small crystal grain size has not only high resistance but also low heat resistance, and if the heat resistance is low, the margin for subsequent heat treatment is small.
[0010]
Therefore, in the conventional example shown in FIG. 3, the thin line effect that the sheet resistance of the diffusion layer 16 is not reduced even if the TiSi ₂ film 19 is formed is likely to occur, and the heat treatment after the TiSi ₂ film 19 is formed. Since the margin is small, it is difficult to manufacture the high-speed, low power consumption and fine CMOS transistor 29 with a high yield.
[0011]
Moreover, since the diffusion layer 16 needs to be shallow in order to miniaturize the CMOS transistor 29 as described above, the TiSi ₂ film 19 is also thin in order to prevent a short circuit between the TiSi ₂ film 19 and the Si substrate 11. There is a need to. For this reason, the TiSi ₂ film 19 is more easily aggregated, and it is further difficult to manufacture a high-speed, low power consumption and fine CMOS transistor 29.
[0012]
On the other hand, if a CoSi ₂ film is formed on the diffusion layer 16 instead of the TiSi ₂ film 19, the fine line effect is less likely to occur. However, the heat resistance of the CoSi ₂ film is not so high at about 750 to 800 ° C., which is the same as that of the TiSi ₂ film 19, and the subsequent heat treatment margin is small, so that high speed, low power consumption, and a fine semiconductor device with high yield can be obtained. It was difficult to manufacture.
[0013]
As another method for suppressing the thin line effect, the Ti film 18 is formed in a state where the surface portion of the Si substrate 11 is amorphized by As ion implantation, and then the TiSi ₂ film 19 is formed by high-speed heat treatment. There was a way to form. However, even with this method, it is considered that a Ti—O—As reaction occurs even with As ion-implanted for amorphization, and the TiSi ₂ film 19 having high heat resistance could not be formed. .
[0014]
On the other hand, as a method of forming the TiSi ₂ film 19 having high heat resistance, Si is ion-implanted in a state where the Ti film 18 is formed on the Si substrate 11 and mixed at the interface between the Si substrate 11 and the Ti film 18. Then, there was a method of forming the TiSi ₂ film 19 by subsequent rapid heat treatment. In this method, the heat resistance of the TiSi ₂ film 19 was improved up to about 850 ° C.
[0015]
However, in order to form the TiSi ₂ film 19 having high heat resistance by this method, it is necessary to ion-implant Si at a dose of 10 ¹⁵ cm ⁻² or more. As a result, the Si substrate 11 and the Ti film 18 A large number of crystal defects were formed at the interface, and these crystal defects could not be eliminated by the subsequent heat treatment. For this reason, the junction leakage current in the diffusion layer 16 is large, and it is difficult to manufacture the CMOS transistor 29 having excellent characteristics.
[0016]
[Means for Solving the Problems]
According to a method of manufacturing a CMOS transistor according to the present invention, a metal film is formed on a semiconductor substrate, and the semiconductor substrate and the metal film are reacted to form a compound film on the diffusion layers of the NMOS transistor and the PMOS transistor in the semiconductor substrate . the method of manufacturing a CMOS transistor to be formed, and forming the diffusion layer of the NMOS transistor and selectively introducing Sb into the semiconductor substrate, and after formation of the diffusion layer of the NMOS transistor and the PMOS transistor A step of ion-implanting Sb into the entire surface of the semiconductor substrate to form an amorphous surface portion of the semiconductor substrate before forming the metal film.
[0017]
In the CMOS transistor manufacturing method according to the present invention, a Si substrate is used as the semiconductor substrate, and a Ti film, a Co film, a Ni film, a Pt film, an Au film, a Cu film, a Zr film, a Hf film, and a Pd are used as the metal film. Any one of a film, a W film, a Mo film, and a Ta film is used, and the compound film is a TiSi ₂ film, a CoSi ₂ film, a NiSi film, a NiSi ₂ film, a Ni ₂ Si film, a PtSi film, a PtSi ₂ film, or AuSi _2. film, CuSi ₂ film, HfSi ₂ film, PdSi ₂ film, WSi ₂ film, MoSi ₂ layer can be formed either of TaSi ₂ film.
[0018]
In the CMOS transistor manufacturing method according to the present invention, the diffusion layer of the NMOS transistor is formed of Sb. Therefore, even if a compound film is formed on the diffusion layer having a narrow line width, this compound film is formed into a C54 crystal. Thus, a low-resistance compound film can be formed. In addition, the Sb forming the diffusion layer of the NMOS transistor does not cause insufficient crystal growth of the compound film, and the crystal grain size of the compound film can be increased, and the resistance is low. Thus, it is possible to form a highly heat-resistant compound film having a large heat treatment margin.
[0019]
In addition, Sb ions are implanted into the entire surface of the semiconductor substrate after the formation of the diffusion layers of the NMOS transistor and the PMOS transistor and before the formation of the metal film, so that the surface portion of the semiconductor substrate is made amorphous. The reaction with the metal film progresses uniformly, and the crystal grain size of the compound film can be further increased, and the crystal growth of the compound film is insufficient due to Sb ion-implanted for amorphization. In addition, the crystal grain size of the compound film can be increased, and a high heat-resistant compound film having a low resistance and a large margin for subsequent heat treatment can be formed.
[0020]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, the first and second embodiments of the present patent application the invention will be described with reference to FIGS. FIG. 1 shows a first embodiment in which a TiSi ₂ film is formed as a compound film. Also in the first embodiment, as shown in FIG. 1A, substantially the same steps as those in the conventional example shown in FIG. 3 are executed until the sidewall spacer of the gate electrode is formed with the SiO ₂ film 15. To do.
[0021]
However, in this first embodiment, after that, O ₂ gas is supplied at a rate of 4 slm, and thermal oxidation is performed at 800 ° C. for 10 minutes, so that the exposed portion of the Si substrate 11 and the upper surface of the W polycide layer 14 have a thickness of 10 nm. The SiO ₂ film 31 is formed.
[0022]
Then, using a resist (not shown) covering the formation region of the NMOS transistor, the W polycide layer 14 and the SiO ₂ films 12 and 15 as a mask, BF with an acceleration energy of 40 keV and a dose of 3 × 10 ¹⁵ cm ^−2. ₂ is ion-implanted to form a P-type diffusion layer 17 in the formation region of the PMOS transistor.
[0023]
Next, as shown in FIG. 1B, after removing the SiO ₂ film 31 with hydrofluoric acid, a resist (not shown) covering the formation region of the PMOS transistor, the W polycide layer 14, and the SiO ₂ films 12, 15 As a mask, Sb is ion-implanted with an acceleration energy of 60 keV and a dose of 3 × 10 ¹⁵ cm ⁻² to form an N-type diffusion layer 16 in the formation region of the NMOS transistor. Then, heat treatment is performed at 1000 ° C. for 10 seconds in an N ₂ atmosphere to activate the impurities in the diffusion layers 16 and 17.
[0024]
Next, as shown in FIG. 1C, a natural oxide film (not shown) or the like is removed with buffered hydrofluoric acid, and then the Si substrate is accelerated with an acceleration energy of 40 keV and a dose of 1 × 10 ¹⁴ cm ^−2. Sb ions are implanted into the entire surface of the silicon substrate 11 to form an amorphous layer 32 on the surface of the Si substrate 11.
[0025]
Since Sb has an atomic radius larger than that of As, the amorphous layer 32 can be formed with a smaller dose than that of As. Then, after removing a natural oxide film (not shown) and the like again with buffered hydrofluoric acid, a 30 nm-thick Ti film 18 is formed by sputtering with a power of 0.5 kW, a temperature of 150 ° C., Ar of 100 sccm, and a pressure of 0.47 Pa. It is formed on the entire surface of the Si substrate 11.
[0026]
Next, as shown in FIG. 1D, N ₂ gas is supplied at a rate of 5 slm and heat treatment is performed at 650 ° C. for 30 seconds to cause the Si substrate 11 and the Ti film 18 to react to form a TiSi ₂ film 19. Are selectively formed. Then, after immersing in ammonia excess water to remove the unreacted Ti film 18 on the SiO ₂ films 12 and 15 and the W polycide layer 14, N ₂ gas is again supplied at a rate of 5 slm. A TiSi ₂ film 19 is stabilized by heat treatment at 800 ° C. for 30 seconds.
[0027]
Next, a SiO ₂ film having a thickness of 100 nm is formed by a low pressure CVD method with SiH ₄ / O ₂ gas = 0.03 / 0.54 slm, temperature 400 ° C., pressure 10.2 Pa, or SiH ₂ Cl ₂ / A SiN film having a thickness of 50 nm is formed by a low pressure CVD method with NH ₃ / N ₂ gas = 0.05 / 0.2 / 0.2 slm, temperature 760 ° C., and pressure 70 Pa.
[0028]
Then, a BPSG film having a thickness of 500 nm is formed by a low pressure CVD method with O ₃ + TEOS gas = 50 sccm, temperature 720 ° C., and pressure 40 Pa. As shown in FIG. 1E, the interlayer insulating film 21 is formed by the above SiO ₂ film or SiN film and the BPSG film.
[0029]
Thereafter, a resist (not shown) is patterned on the interlayer insulating film 21, and this resist is used as a mask to perform dry etching with C ₄ F ₈ gas = 50 sccm, high-frequency power 1.2 kW, and pressure 2 Pa. A connection hole 22 is formed in the film 21.
[0030]
Thereafter, in order to cope with the mask displacement of the connection hole 22, the resist (not shown) and the interlayer insulating film 21 are used as a mask to apply 50 keV to the Si substrate 11 exposed from the connection hole 22 in the NMOS transistor formation region. As is ion-implanted with an acceleration energy and a dose of 3 × 10 ¹⁵ cm ⁻² .
[0031]
Further, BF ₂ is ion-implanted into the Si substrate 11 exposed from the connection hole 22 in the PMOS transistor formation region with an acceleration energy of 50 keV and a dose amount of 3 × 10 ¹⁵ cm ⁻² . Then, heat treatment is performed at 850 ° C. for 30 seconds in an N ₂ atmosphere to activate impurities implanted into the Si substrate 11 from the connection hole 22.
[0032]
Thereafter, a Ti film having a thickness of 10 nm is formed by sputtering with a power of 8 kW, a temperature of 150 ° C., an Ar of 100 sccm, and a pressure of 0.47 Pa. Further, a reactivity of 5 kW, Ar / N ₂ = 40/20 sccm, and a pressure of 0.47 Pa. A TiN film having a thickness of 70 nm is formed by sputtering, and a TiN / Ti film 23 is formed on the entire surface of the Si substrate 11 including the inside of the connection hole 22.
[0033]
Thereafter, a W film 24 having a thickness of 400 nm is formed by CVD using Ar / N ₂ / H ₂ / WF ₆ gas = 2200/300/500/75 sccm, temperature 450 ° C., and pressure 10640 Pa. Then, etch back of SF ₆ gas = 50 sccm, high frequency power 150 W, pressure 1.33 Pa is performed, and the connection hole 22 is filled with the TiN / Ti film 23 and the W film 24.
[0034]
Thereafter, a Ti film 25 having a thickness of 30 nm is formed by sputtering with a power of 4 kW, a temperature of 150 ° C., Ar of 100 sccm, and a pressure of 0.47 Pa. Further, a sputtering method of power of 22.5 kW, temperature of 150 ° C., Ar of 50 sccm, and pressure of 0.47 Pa is formed. Then, an Al—Si film 26 having a thickness of 0.5 μm is formed.
[0035]
Thereafter, a resist (not shown) is patterned on the Al—Si film 26, and using this resist as a mask, BCl ₃ / Cl ₂ gas = 60/90 sccm, microwave power 1 kW, high-frequency power 50 W, pressure 0.016 Pa. The dry etching is performed to form a wiring with the Ti film 25 and the Al—Si film 26. Further, a conventionally known process is executed to complete a CMOS transistor 29 having an NMOS transistor 27 and a PMOS transistor 28.
[0036]
FIG. 2 shows steps in the middle of the second embodiment for forming a CoSi ₂ film as a compound film, corresponding to FIGS. 1C and 1D in the first embodiment. Also in the second embodiment, after the amorphous layer 32 is formed on the surface portion of the Si substrate 11 by Sb ion implantation, the first process shown in FIG. Steps substantially similar to those of the embodiment are performed.
[0037]
However, in this second embodiment, thereafter, as shown in FIG. 2A, a Co film 33 having a thickness of 10 nm is formed on the entire surface of the Si substrate 11 by sputtering with a power of 1 kW, Ar 100 sccm, and pressure 0.47 Pa. Form. Subsequently, a 20 nm thick TiN film 34 is formed on the entire surface of the Co film 33 by a reactive sputtering method with a power of 5 kW, Ar / N ₂ = 40/20 sccm, and a pressure of 0.47 Pa.
[0038]
Note that a Ti film having a thickness of 10 nm may be formed in place of the TiN film 34 by sputtering with a power of 0.5 kW, Ar / N ₂ = 40/20 sccm, and a pressure of 0.47 Pa.
[0039]
Next, as shown in FIG. 2B, N ₂ gas is supplied at a rate of 5 slm and heat treatment is performed at 550 ° C. for 30 seconds to cause the Si substrate 11 and the Co film 33 to react with each other, thereby causing the CoSi ₂ film 35 to react. Are selectively formed. Then, after immersing in sulfuric acid / hydrogen peroxide to remove the Co film 33 remaining unreacted on the SiO ₂ films 12 and 15 and the W polycide layer 14, N ₂ gas is supplied again at a rate of 5 slm. A CoSi ₂ film 35 is stabilized by heat treatment at 700 ° C. for 30 seconds.
[0040]
Subsequent to the formation of the interlayer insulating film 21, a process substantially similar to that of the first embodiment described above is performed again to complete the CMOS transistor 29 having the NMOS transistor 27 and the PMOS transistor 28.
[0041]
In the second embodiment, the TiN film 34 or the Ti film is formed on the Co film 33. However, the TiN film 34 or the Ti film is not necessarily formed. However, these TiN film 34 or Ti film can prevent the surface of the Co film 33 from being oxidized and prevent the substantial thickness of the Co film 33 from decreasing.
[0042]
Further, the native oxide film, adsorbed oxygen, etc. on the surface of the Si substrate 11 can be adsorbed by the TiN film 34 or the Ti film through the Co film 33 so that the Si substrate 11 and the Co film 33 can react uniformly. Thus, crystal defects formed in the Si substrate 11 can be reduced.
[0043]
While in the first and second embodiments of the following to form a Ti film 18 and Co films 33 by the sputtering method, it may be formed of these films by the CVD method.
[0044]
In the first and second embodiments described above, the TiSi ₂ film 19 or the CoSi ₂ film 35 is formed using the Ti film 18 or the Co film 33. However, the Ni film, the Pt film, the Au film, and the Cu film are used. NiSi film, NiSi ₂ film, Ni ₂ Si film, PtSi film, PtSi ₂ film, AuSi ₂ film, CuSi using any one of Zr film, Zr film, Hf film, Pd film, W film, Mo film, Ta film, etc. ₂ film, HfSi ₂ film, PdSi ₂ film, WSi ₂ film, MoSi ₂ film may be formed either of such TaSi ₂ film.
[0045]
【The invention's effect】
In the method of manufacturing a CMOS transistor according to the invention of the present application, even if a compound film is formed on a diffusion layer having a narrow line width, it is possible to form a highly heat-resistant compound film having a low resistance and a large margin for subsequent heat treatment. Therefore, high speed, low power consumption, and a fine CMOS transistor can be manufactured with a high yield.
[Brief description of the drawings]
FIG. 1 is a side sectional view sequentially showing a first embodiment of the present invention.
FIGS. 2A and 2B are side sectional views sequentially showing steps in the middle of the second embodiment of the invention of the present application and corresponding to FIGS. 1C and 1D. FIGS.
FIG. 3 is a side cross-sectional view sequentially showing one conventional example of the present invention.
[Explanation of symbols]
11 Si substrate (semiconductor substrate) 16 Diffusion layer 18 Ti film (metal film) 19 TiSi ₂ film (compound film)
32 Amorphous layer 33 Co film (metal film)
35 CoSi ₂ film (compound film)

Claims (2)

In a method of manufacturing a CMOS transistor, a metal film is formed on a semiconductor substrate, and the semiconductor substrate and the metal film are reacted to form a compound film on a diffusion layer of an NMOS transistor and a PMOS transistor in the semiconductor substrate.
And forming the diffusion layer of the LDD structure of the NMOS transistor selectively introducing relatively low concentration As and relatively high concentration of Sb in the semiconductor substrate,
Forming a relatively high concentration diffusion layer among the diffusion layers of the LDD structure of the PMOS transistor by ion implantation through a SiO ₂ film;
After the formation of the diffusion layers of the NMOS transistor and the PMOS transistor and before the formation of the metal film, Sb is ion-implanted over the entire surface of the semiconductor substrate to amorphize the surface portion of the semiconductor substrate. A method of manufacturing a CMOS transistor, comprising: Using a Si substrate as the semiconductor substrate,
As the metal film, any one of Ti film, Co film, Ni film, Pt film, Au film, Cu film, Zr film, Hf film, Pd film, W film, Mo film, Ta film is used.
As the compound film, TiSi ₂ film, CoSi ₂ film, NiSi film, NiSi ₂ film, Ni ₂ Si film, PtSi film, PtSi ₂ film, AuSi ₂ film, CuSi ₂ film, HfSi ₂ film, PdSi ₂ film, WSi ₂ film, MoSi ₂ film, a manufacturing method of a CMOS transistor according to claim 1, wherein the forming one of TaSi ₂ film.

Images