JPH08274185A - Manufacture of mos transistor - Google Patents

Abstract

PURPOSE: To prevent the diffusion of boron from the p-type gate electrode of a MOS transistor while using means of high reproducibility, by forming an amorphous silicon film on the gate insulation film of the MOS transistor to change it into a polysilicon film through annealing it under specific conditions, and thereafter, by forming the gate electrode of the MOS transistor through patterning the polysilicon film, etc. CONSTITUTION: A MOS transistor with a gate electrode G1 at least one portion of which comprises a p-type semiconductor film is manufactured. In that case, an amorphous silicon film is formed on a gate insulation film 5, and the amorphous silicon film is annealed for an hour or more at 550-700 deg.C to change it into a polysilicon film 6p. Thereafter, patterning at least the polysilicon film 6p, the gate electrode G1 is formed, and using the gate electrode G1 as a mask, the injection of p-type impurity ions is performed. Thereby, concurrently with the formations of the source/drain regions of the MOS transistor, the conduction type of the gate electrode G1 is made to be p-type.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a MOS transistor, and more particularly to a p-type MOS transistor (PMOS) p-type in a CMOS (complementary MOS transistor) circuit.
The present invention relates to a method of suppressing boron (B) diffusion from a gate electrode of a mold, or suppressing penetration of B into a gate oxide film.

[0002]

2. Description of the Related Art A complementary MOS transistor (CMOS) circuit in which an n-type MOS transistor (NMOS) and a p-type MOS transistor (PMOS) coexist on the same substrate is consumed because a current flows only when both transistors are turned on. It has the advantages of low power consumption and high-speed operation due to easy miniaturization and high integration, and is widely used as many LSI constituent devices including memory elements and logic elements. Since room temperature operation of MOS transistors having a gate length of 0.1 μm or less has been confirmed in recent years, it is certain that CMOS circuits will continue to be highly integrated and miniaturized.

By the way, conventionally, as the constituent material of the gate electrode of the PMOS, n is the same as that of the gate electrode of the NMOS.
Materials such as a ⁺ type polysilicon film, or a polycide film or a polymetal film in which a refractory metal silicide film or a refractory metal film is stacked on the ⁺ type polysilicon film have been used. This is n ⁺
This is because the type polysilicon film can withstand a high temperature process well, and since the channel profile is a buried type, the high bulk mobility can be utilized to accelerate the operation. However, in the buried channel type MOS transistor, there is a problem that punch-through easily occurs because the tips of the depletion layers protruding from the source / drain regions approach each other in the deep portion of the substrate due to the influence of the gate electric field.
Therefore, in the generation in which the design rule is reduced to deep submicron or less, it is difficult to suppress the short channel effect in the buried channel type, and therefore the adoption of the surface channel type is desired. If the gate electrode of the PMOS is formed by using the p ⁺ type polysilicon film, a surface channel type profile can be realized.

There are other reasons why the p ⁺ type polysilicon film is desired as the gate electrode material of the PMOS. NMOS, P
In a conventional CMOS circuit using an n ⁺ -type polysilicon film for any of the MOS gate electrodes, an NMOS and a PMOS are used.
And a work function difference exists, and the threshold voltage V _th is asymmetric due to this difference. Therefore, the threshold voltage V _th of both transistors is set to be almost equal (usually 1 V or less) by shallowly ion-implanting boron into the channel region of the PMOS. However, if the impurity concentration on the substrate surface is increased by ion implantation for adjusting the threshold value, the carrier mobility near the substrate surface decreases, which is disadvantageous for speeding up the operation. Therefore, it is necessary to reduce the channel impurity concentration in the future. Is mandatory. Therefore, if the p ⁺ -type polysilicon film having a large work function is used as the gate electrode of the PMOS, the threshold voltage V _th can be made symmetrical between the NMOS and the PMOS without increasing the channel impurity concentration. This means that CMOS
When the basic gate is configured as an inverter, the input / output characteristics of the transistor are made symmetrical, which leads to improvement in the symmetry of the signal transfer characteristics.

[0005]

By the way, in the manufacturing process of a CMOS circuit, the gate electrode of the NMOS is generally PM.
Since the gate electrode of the OS is also formed by patterning a common polysilicon film, in order to give different conductivity types to each other, it is necessary to implant ions into regions to be the respective gate electrodes through a mask. Many. That is, As ⁺ and P ⁺ are formed in the region that becomes the n ⁺ type gate electrode.
Is ion-implanted, while B ⁺ and BF ₂ ⁺ are ion-implanted in the region to be the p ⁺ -type gate electrode, or co-ion implantation of B ⁺ and F ⁺ is performed.

Here, BF ₂ ⁺ is advantageous in controlling the range smaller than B ⁺ and preventing channeling because of its dissociation property and relatively large mass. Also, B ⁺
The same effect can be obtained by co-ion implantation of F ⁺ and F ⁺ . further,
F has an excellent effect of reducing the interface trap density of the gate oxide film (SiO ₂ ). However, on the other hand,
F has a problem that it promotes the diffusion of B, and in some cases B penetrates the gate oxide film and reaches the substrate (Si). This diffusion is the source /
It may occur during various heat treatments such as drain activation anneal, SALICIDE (self-aligned silicidation) process, interlayer dielectric reflow, and the like.

In the ion implantation of B ⁺ , since F is not taken into the polysilicon film, diffusion of B is not promoted as long as this polysilicon film is used alone as a gate electrode material. Even if some diffusion occurs, B does not penetrate through the gate oxide film and is stabilized in the gate oxide film. However, when a refractory metal silicide film or a refractory metal film is laminated on the polysilicon film for the purpose of reducing the gate resistance, F remaining in these films is taken into the polysilicon film. . In such a case, even if the ion implantation is performed using B ⁺ , F still promotes the diffusion and penetration of B. For example, low pressure CVD for reducing WF ₆ with SiH _4.
The WSi _x film formed by the method contains a relatively large amount of residual F, and has a high possibility of causing the above-mentioned problems. Such diffusion or penetration of B causes increase of the threshold voltage V _th of the PMOS, increase of subthreshold swing, or deterioration of reliability of the gate insulating film, and therefore must be prevented as much as possible.

A method considered effective in suppressing the diffusion of B is to lower the heat treatment temperature or shorten the heat treatment time. However, in the former case, recovery of crystal defects caused by ion implantation or dry etching may be insufficient, which may lead to increase in leak current. In the latter case, insufficient activation of impurities may result in insufficient diffusion layer or wiring layer. There is a possibility that this may lead to an increase in resistance.

Further, in order to suppress the penetration of B,
A method of performing rapid thermal nitridation (RTN) of a gate oxide film in a nitriding atmosphere such as NH ₃ or N ₂ O has been proposed. However, these methods lead to problems such as deterioration in transistor characteristics due to increase in film thickness of the gate insulating film and decrease in carrier mobility, and decrease in reliability of the gate insulating film due to increase in fixed charges and interface states, and are not necessarily a good measure. Absent.

Therefore, as an alternative method, there is a method of increasing the crystal grain size of the polysilicon film to reduce the grain boundaries which are diffusion paths, thereby suppressing the diffusion of B, at the 1990 IEEE Symposium on. VLS
I Technology (1990 Symposium on VLSI Technology,
(IEEE) Abstracts, p.111-112. According to this method, first, an amorphous silicon film is deposited on the gate oxide film, and the n ⁺ type gate electrode of the NMOS and the source / source are formed.
The drain region, the p ⁺ type gate electrode of the PMOS, and the source / drain region are simultaneously formed.
After that, the activation annealing of impurities in the source / drain regions and the gate electrode and the reflow of the interlayer insulating film (SiO ₂ film by plasma CVD + BPSG) are both performed 900 times.
It is performed under the condition of 15 ° C. for 15 minutes, and the grain size of the amorphous silicon film at the time of these heat treatments is more than doubled as compared with the polysilicon film formed as a polycrystalline film from the beginning. As a result, the diffusion of B and F into the gate oxide film is reduced, the penetration of B into the Si substrate is suppressed, and the electron trap density in the gate oxide film is successfully reduced. Although the annealing temperature is not specified in the above method, it is described that the TiSi _x film is formed by the SALICIDE method after the patterning of the gate electrode, and the growth of crystal grains also occurs at this stage.

However, since the progress of crystallization from amorphous silicon to polysilicon varies greatly depending on the heat treatment conditions after the amorphous silicon film is formed, the above method does not necessarily lead to a sufficiently large grain size. It cannot be said that this is happening, and that the particle size is not reproducible.

As described above, all the conventional measures for preventing the diffusion of B from the p-type gate electrode lack the decisive factor. Therefore, it is an object of the present invention to provide a method for manufacturing a MOS transistor capable of preventing the diffusion of B by a highly reproducible method without impairing the reliability of the gate insulating film.

[0013]

A method for manufacturing a MOS transistor according to the present invention is proposed in order to achieve the above-mentioned object, and a MOS having a gate electrode at least a part of which is formed of a p-type semiconductor film. When manufacturing a transistor, a first step of forming an amorphous silicon film on a gate insulating film and a second step of annealing the amorphous silicon film at 550 to 700 ° C. for 1 hour or more to change it into a polysilicon film A third step of patterning at least the polysilicon film to form a gate electrode, and ion-implanting p-type impurities using the gate electrode as a mask to form source / drain regions and to form the gate electrode. The fourth step is to make the conductivity type p-type.

A typical example of the gate insulating film is a silicon compound film. As a silicon compound film used as a gate insulating film of a MOS transistor, a silicon nitride film, a silicon oxide film, an ONO film in which a silicon nitride film is sandwiched by silicon oxide films, or the like is known. It is effective to use a film (SiO _x ).

The above-mentioned annealing conditions are conditions at a considerably low temperature and for a long time as compared with the usual impurity activation annealing. That is, according to the present invention, the grain size of the amorphous silicon film is not increased simultaneously with the subsequent heat treatment as in the prior art, but is gradually performed immediately after the film formation, whereby sufficient grain size increase and high controllability are achieved. It is realized with reproducibility. It is difficult to generate crystal nuclei in the temperature range where the annealing temperature is lower than 550 ° C, and 700 ° C.
In the higher temperature region, the rate of nucleation is too fast to cause sufficient grain size increase. A more preferable temperature range is 6
It is 00-650 degreeC. Further, even if the annealing time is less than 1 hour, the grain size cannot be sufficiently increased. A more preferable annealing time is 5 to 10 hours.

Here, after the amorphous silicon film is formed in the first step, at least one of silicon and argon is ion-implanted into a region of the amorphous silicon film other than the gate formation portion to further amorphize it. You may make it thorough.

The gate electrode may be composed of a polysilicon film alone, but after the polysilicon film is formed in the second step, a refractory metal silicide film or a refractory metal film is laminated thereon to form a composite. The resistance may be reduced by forming a film and patterning the composite film in the third step to form a gate electrode. A composite film of a polysilicon film and a refractory metal silicide film is known as a polycide film, and a composite film of a refractory metal film is known as a polymetal film.

As the refractory metal silicide film, W
Si _x film, TiSi _x film, MoSi _x film, TaSi
Conventionally known films such as an _x film, a PtSi _x film, and a NiSi _x film can be used, but a typical film among them is the WSi _x film. The WSi _x film is generally a low pressure CV for reducing WF ₆ with SiH ₄ or SiCl ₂ H ₂ (dichlorosilane).
It is known that a SiCl ₂ H ₂ reduction method for forming a film by D can reduce the residual F in the film. The refractory metal silicide film can also be formed by the SALICIDE method. In this case, after patterning the polysilicon film, the entire surface of the substrate is covered with a refractory metal film and annealed to make the upper surface of the gate electrode and the surface of the active region (source / drain region, etc.) of the substrate self-aligned. Then, the unreacted refractory metal film is removed. On the other hand, as the refractory metal film, W film, T film
Conventionally known films such as i film, Mo film, Ta film, Pt film, and Ni film can be used. These films are low pressure CVD
Method, plasma CVD method, or sputtering method.

In the present invention, since the diffusion of the p-type impurity is suppressed by increasing the grain size of the polysilicon film, the gate which contains B as the p-type impurity and inevitably contains fluorine in the manufacturing process. A highly reliable MOS transistor can be manufactured even by using the electrode. This fluorine is taken in during the ion implantation of BF ₂ ⁺ or the co-ion implantation of B ⁺ and F ⁺ to make the amorphous silicon film p-type, or is laminated on the polysilicon film. It is taken in by diffusion of residual F from the refractory metal silicide film or refractory metal film.

[0020]

When the amorphous silicon is changed to polysilicon, the generation of crystal nuclei can be delayed to increase the crystal grain size. In the present invention, this delay of nucleation is achieved by low temperature and long time annealing. Moreover, in the present invention, since this annealing is performed subsequent to the formation of the amorphous silicon film, the grain size can be increased sufficiently and with high reproducibility without being affected by the heat treatment conditions of the subsequent steps.

The delay in the generation of nuclei becomes more remarkable by using the complete amorphization by ion implantation together. That is, in the present invention, the nucleation rate in the region other than the gate electrode formation portion in the amorphous silicon film is extremely reduced, so that the nucleation rate is relatively increased in the gate electrode formation portion, and the growth of crystal grains is Proceed outward from the area. As a result, the grain boundaries in the gate electrode, that is, the diffusion paths are reduced, and even if the polysilicon film contains the impurity B as well as F, the diffusion and penetration of B are effectively suppressed. Therefore, for introducing the p-type impurity, BF
₂ ⁺ ion implantation, or B ⁺ and F ⁺ or adopting a co-ion implantation, also laminating the refractory metal silicide film or a refractory metal film containing residual F on the polysilicon film,
There will be no hindrance.

[0022]

EXAMPLES Specific examples of the present invention will be described below.

Example 1 This example illustrates the present invention with a C having a polycide gate electrode.
This is an example applied to the manufacture of MOS. The process of this embodiment will be described with reference to FIGS.

First, a ν type (low concentration n type) Si substrate (ν−
A field oxide film 2 is formed on the Sub 1 by a well-known LOCOS method to perform element isolation, and then B ⁺ is ion-implanted into the NMOS portion and P ⁺ is ion-implanted into the PMOS portion through a resist mask (not shown). The p-type well (p-
Well 3 and n-type well (n-Well) 4 were formed. Here, the B ⁺ ion implantation conditions are, for example, an ion acceleration energy of 280 keV and a dose of 1.6 × 1.
It was set to 0 ¹³ / cm ² . The P ⁺ ion implantation conditions are, for example, an ion acceleration energy of 330 keV and a dose amount of 8 × 10 ¹² / cm ² . Further, after ion implantation for adjusting the threshold voltage V _{th in} the surface layer of the active region, a gate oxide film 5 having a thickness of about 8 nm was formed on the surface of the active region by pyrogenic oxidation. FIG. 1 shows a state in which the steps up to this point have been completed.

Next, as shown in FIG. 2, an amorphous silicon film 6a (subscript a indicates an amorphous state) was deposited on the entire surface of the substrate by low pressure CVD. This low pressure CVD was carried out at a deposition temperature of 550 ° C. using SiH ₄ as a source gas as an example.

Subsequently, the amorphous silicon film, which is the greatest feature of the present invention, is annealed at a low temperature for a long time.
This annealing is performed, for example, in an N ₂ atmosphere at 600 ° C. for 5 hours.
It was carried out under the condition of 10 hours. By the solid phase growth at this time, the amorphous silicon film 6a was changed to a polysilicon film 6p (subscript p represents a polycrystalline state) having a maximum grain size of about 1 μm, as shown in FIG.

Then, the entire surface of the base body is subjected to WS by low pressure CVD.
The i _x film 7 was deposited. This low pressure CVD uses a WF ₆ / SiCl ₂ H ₂ mixed gas as an example, and a deposition temperature of 68
Performed at 0 ° C. As a result, the gate electrode is composed of the W-polycide film. Since heating at about 700 ° C. is performed in the process of forming the WSi _x film as described above, in the conventional method, the crystal growth of the amorphous silicon film slightly progresses during this period, and the crystal grains become smaller. It was a cause. However, in the present invention, since the amorphous silicon film 6a has already been changed to the polysilicon film 6p, there is no such concern.

Next, the W-polycide film was anisotropically processed by dry etching through a resist mask (not shown) to form a gate electrode G ₁ . This dry etching was performed by using, for example, a Cl ₂ / O ₂ mixed gas and a microwave plasma etching apparatus with a magnetic field while ensuring a sufficiently large selection ratio for the gate oxide film 5. Further, the PMOS portion is covered with a resist pattern (not shown), and the gate electrode G ₁ is used as a mask for NM.
By implanting As ⁺ low-concentration ions into the OS part,
An n ⁻ type LDD region 8 was formed. Then, this time NMO
A p ^- type LDD region 9 was formed by covering the S portion with a resist pattern (not shown) and performing low concentration ion implantation of BF ₂ ⁺ into the PMOS portion using the gate electrode G ₁ as a mask. FIG. 4 shows a state in which the steps up to here are completed.

Next, a SiO ₂ film having a thickness of about 150 nm is deposited on the entire surface of the substrate by low pressure CVD, and this is anisotropically etched back to form a sidewall 10 on the sidewall surface of the gate electrode G ₁ . . Then, the gate electrodes G ₁ ,
Using the sidewall 10 and a resist pattern (not shown) as a mask, As ⁺ , PM
BF ₂ ⁺ was introduced into the OS portion by high-concentration ion implantation to form the n ⁺ type source / drain regions 11 and the p ⁺ type source / drain regions 12, respectively. here,
The ion implantation conditions of As ⁺ and BF ₂ ⁺ are, for example, an ion acceleration energy of 20 keV and a dose of 3 ×.
It was set to 10 ¹⁵ / cm ² . During this ion implantation, since the ions are also implanted into the gate electrode G ₁ at the same time, the conductivity type of the gate electrode G _{1 in} the NMOS section is n ⁺ type, P type.
The conductivity type of the gate electrode G ₁ of the MOS portion is p ⁺ type.

After that, rapid thermal annealing (RTA) is performed under the conditions of, for example, 1050 ° C. for 10 seconds, whereby n ⁺ type source / drain regions 11 and p are formed.
The impurities in the ⁺ type source / drain region 12 were activated. In the present invention, the amorphous silicon film 6a has already been changed to the polysilicon film 6p as described above, and the number of grain boundaries that can serve as a B diffusion path is reduced. Therefore, even though F is mixed in the gate electrode G ₁ of the PMOS portion due to ion implantation or lamination with the WSi _x film 7, RTA
Even after the rapid high temperature heat treatment as described above, B did not diffuse into the gate oxide film 5 or penetrate through it and diffuse into the active region.

After that, an interlayer insulating film was deposited, connection holes were opened, and upper layer wirings were formed by a conventional method to complete the CMOS. The CMOS manufactured in this example exhibited stable high-speed operation without causing an increase in resistance, a change in threshold voltage V _th , and an increase in interface state.

Example 2 In this example, the regions other than the gate electrode forming portion of the amorphous silicon film were thoroughly amorphized by ion implantation before annealing at low temperature for a long time.
The grain size of the polysilicon film forming the gate electrode was further increased. The process of this embodiment will be described with reference to FIGS.

First, the steps up to the formation of the amorphous silicon film 6a (see FIG. 2) are performed in the same manner as in Example 1, and then the gate electrode forming portion is covered with the resist pattern 13 as shown in FIG. Ion implantation of Si ⁺ was performed. The ion implantation conditions at this time were, for example, an ion acceleration energy of 10 to 30 keV and a dose amount of 1 × 10 ¹⁶ / cm ² . As a result, the region other than the gate electrode forming portion was changed to the thoroughly amorphized silicon film 6aa.

After removing the resist pattern 13 by O ₂ plasma ashing, low temperature and long time annealing was performed under the same conditions as in Example 1. As a result of this annealing, as shown in FIG. 7, the amorphous silicon film 6 a is formed into a large grain size polysilicon film 6 in the gate electrode formation region covered with the resist pattern 13.
pl (subscript l indicates that the particle size is relatively large),
Small-sized polysilicon film 6ps in other regions
(The subscript s indicates that the particle size is relatively small.). However, the above-mentioned small grain polysilicon film 6p
Although s is referred to as a small grain size for convenience of comparison with the giant grain size, it has a large grain size similarly to the polysilicon film 6p described in the first embodiment.

It is considered that such a partial difference in particle size occurs due to the following mechanism. 9 to 11 are
It is a partial expanded sectional view of a PMOS part. First, in FIG. 9, when Si ⁺ is ion-implanted into the amorphous silicon film 6a covered with the resist pattern 13 at the gate electrode forming portion, the region other than the gate electrode forming portion is changed to the thoroughly amorphized silicon film 6aa, and the nucleus The formation rate is significantly reduced. When low temperature and long time annealing is performed after removing the resist pattern 13, as shown in FIG.
The nuclei 14 are first generated in the gate formation region, and the crystal grain growth is started from this as a starting point. As a result, as shown in FIG. 11, the grain size of the crystal grains in the gate formation region becomes larger than that in the other regions, and a large grain size polysilicon film 6pl is formed.

Thereafter, as shown in FIG. 8, a gate electrode G is formed by forming a W-polycide film and patterning the W-polycide film.
_2, the formation of LDD regions, the formation of sidewalls 10, the formation of source / drain regions 12, the introduction of impurities into the large-grain polysilicon film 6pl, and the impurity activation anneal were performed. Further, the CMOS is completed through the deposition of the interlayer insulating film, the opening of the connection hole, and the formation of the upper layer wiring. In the CMOS of this embodiment, the operating characteristics of the PMOS are further improved as compared with the first embodiment.

The present invention has been described above based on the two embodiments, but the present invention is not limited to these embodiments. For example, in the above-described embodiment, the p-type impurity is introduced into the amorphous silicon film 6a by the ion implantation of BF ₂ ⁺ , but this may be the co-ion implantation of B ⁺ and F ⁺ , or there is a possibility that F is mixed. It is also possible to replace it with the non-existent B ⁺ ion implantation. Further, in the above embodiment, the film forming the upper layer side of the gate electrode is the WSi _x film deposited by the low pressure CVD, but this WSi _x film is a SALICID.
It may be formed of E. Further alternatively, the upper layer side of the gate electrode may be a refractory metal film. Further, in the second embodiment, the ions to be completely amorphized may be Ar ⁺ instead of Si ⁺ .

In addition, the details of the structure of the CMOS circuit, the film thickness of each film, the deposition method and conditions, the annealing conditions, and the ion implantation conditions can be changed as appropriate.

[0039]

As is apparent from the above description, the application of the present invention effectively suppresses the diffusion of B even if F is contained together with B in the p-type polysilicon gate electrode of the PMOS. Therefore, it is possible to prevent the increase of the threshold voltage V _{th and} the increase of the subthreshold swing while _maintaining the effect of reducing the interface trap density by F. As a result, it is possible to configure a fine PMOS that is excellent in operation speed and reliability, and further to use it to configure a CMOS with improved signal transfer characteristics.

[Brief description of drawings]

FIG. 1 is a schematic cross-sectional view showing a state in which element isolation, well formation, and gate oxidation are performed on a Si substrate in a process example in which the present invention is applied to manufacturing a CMOS.

FIG. 2 is a schematic cross-sectional view showing a state in which an amorphous silicon film is deposited on the entire surface of the base body of FIG.

FIG. 3 is a schematic cross-sectional view showing a state in which the amorphous silicon film of FIG. 2 is changed to a polysilicon film by performing low temperature / long time annealing.

4 is a WSi _x film deposited on the polysilicon film of FIG. 3 to form a W-polycide film, which is patterned to form a gate electrode, and LDD is formed by low-concentration ion implantation.
It is a typical sectional view showing the state where a field was formed.

5 is a schematic view showing a state in which a side wall is formed on the side wall surface of the gate electrode in FIG. 4, source / drain regions are formed by high-concentration ion implantation, and impurities are also introduced into the polysilicon film. FIG.

FIG. 6 is a schematic cross-sectional view showing a state in which a region other than a gate electrode formation portion is thoroughly amorphized by performing ion implantation on an amorphous silicon film in another process example applied to manufacture of the CMOS of the present invention. It is a figure.

FIG. 7 is a schematic cross-sectional view showing a state in which the amorphous silicon film of FIG. 6 is changed to a polysilicon film having a particularly large grain size in the gate electrode formation portion by performing low temperature / long time annealing.

FIG. 8 is a schematic view showing a state in which a W-polycide film is formed, a gate electrode is formed by patterning the LDD region, a sidewall is formed, a source / drain region is formed, and impurities are introduced into the polysilicon film. FIG.

9 is a partially enlarged cross-sectional view of the PMOS portion of FIG. 6, showing a state in which ion implantation is performed to a region of the amorphous silicon film other than the gate electrode formation portion to make it completely amorphous.

10 is a schematic cross-sectional view showing a state in which nuclei are preferentially generated in the gate electrode formation portion of the amorphous silicon film of FIG. 9 by low temperature / long time annealing.

FIG. 11 is a schematic cross-sectional view showing a state in which a polysilicon film in which the grain size of the gate electrode formation portion is larger than that in other regions is formed.

[Explanation of symbols]

3 p-type well 4 n-type well 5 gate oxide film 6a amorphous silicon film 6p polysilicon film 6pl huge grain size polysilicon film 6ps small grain size polysilicon film 11 n ⁺ type source / drain region G ₁ gate electrode G ₂ ( Gate electrode 12 Source / drain region 13 Resist pattern 14 Nucleus

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical indication H01L 21/336 H01L 29/78 301P

Claims (6)

[Claims] 1. A method of manufacturing a MOS transistor having a gate electrode, at least a part of which is composed of a p-type semiconductor film, comprising: a first step of forming an amorphous silicon film on a gate insulating film; and the amorphous silicon. Membrane 1 at 550-700 ℃
Second annealing for more than 2 hours to change into polysilicon film
A step of patterning at least the polysilicon film to form a gate electrode, and ion-implanting a p-type impurity using the gate electrode as a mask to form a source / drain region and to form a gate electrode of the gate electrode. And a fourth step of setting the conductivity type to p-type. 2. The MOS according to claim 1, wherein after forming the amorphous silicon film in the first step, at least one of silicon and argon is ion-implanted into a region of the amorphous silicon film other than a gate electrode forming portion. Manufacturing method of transistor. 3. A polysilicon film is formed in the second step, and a refractory metal silicide film or a refractory metal film is laminated thereon to form a composite film. In the third step, the composite film is formed. The method of manufacturing a MOS transistor according to claim 1, wherein the gate electrode is formed by patterning. 4. The method of manufacturing a MOS transistor according to claim 1, wherein the gate electrode contains boron as a p-type impurity and incorporates fluorine. 5. The fluorine is taken into the gate electrode in accordance with the BF ₂ ⁺ ion implantation or the B ⁺ and F ⁺ co-ion implantation into the amorphous silicon film in the first step. 4. The method for manufacturing a MOS transistor according to 4. 6. The method of manufacturing a MOS transistor according to claim 4, wherein the fluorine is taken into the gate electrode from the refractory metal silicide film or the refractory metal film laminated on the polysilicon film.