JPH1167690A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To manufacture a semiconductor device operated at high speed even when it has high current driving capability, is fine and has low driving voltage and small power consumption by containing no only donor atoms having a specific atomic number but also P to an Si film in the pattern of a gate electrode. SOLUTION: P ions are injected to the polycrystalline Si film 41 of an N cannel region 33, and B ions are implanted to the polycrystalline Si film 41 of a P channel region 34. The polycrystalline Si films 41 are worked in the pattern of a gate electrode by dry etching. As ions and B ions are implanted to the Si substate 31 of the N channel region 33 and the P channel region 34 respectively while using the polycrystalline Si films 41, an SiO2 film 32 and a resist having a proper pattern as masks, and diffusion layers 42, 43 constituting source/drain having LDD structure and having low concentration are formed respectively. Accordingly, not only donor atoms having an atomic number 33 or higher but also P are contained to the Si films 41 in the pattern of the gate electrode.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device in which a source / drain surface and an upper surface of a gate electrode are formed into a silicide film in a self-aligned manner.

[0002]

2. Description of the Related Art In order to manufacture a fine semiconductor device,
It is necessary to reduce the line width of the source / drain and the depth, and also reduce the line width of the gate electrode. But,
If only these operations are performed, the sheet resistance of the source / drain and gate electrodes increases, and the operation speed decreases. Therefore, it has been considered that the surface of the source / drain and the upper surface of the gate electrode are self-aligned with a silicide film such as a TiSi ₂ film or a CoSi ₂ film.

FIG. 5 shows a conventional example of a method for manufacturing an NMOS transistor in which a TiSi ₂ film is formed in a self-aligned manner as a silicide film. In this conventional example, FIG.
As shown in (a), a SiO ₂ film 12 as an element isolation oxide film on the surface of the Si substrate 11, SiO ₂ as a gate oxide film on the surface of the element active region surrounded by the SiO ₂ film 12 After forming the film 13, the SiO ₂ films 12, 13
The polycrystalline Si film 14 is processed into a gate electrode pattern.

[0004] Then, a polycrystalline Si film 14 and the low concentration diffusion layer 15 by ion implantation of As constitute the source / drain of the LDD structure in the Si substrate 11 by an SiO ₂ film 12 as a mask, SiO ₂ Polycrystalline Si film 1 such as film 16
4 are formed.

Then, As is ion-implanted into the Si substrate 11 using the polycrystalline Si film 14 and the SiO ₂ films 12 and 16 as a mask to form a high-concentration diffusion layer 17 constituting the source / drain of the LDD structure. As, which is an impurity in the diffusion layers 15 and 17 and the polycrystalline Si film 14, is activated by a heat treatment. Oxide films (not shown) are formed on the surface of the Si substrate 11 and the upper surface of the polycrystalline Si film 14 by this heat treatment, and these oxide films are removed with dilute hydrofluoric acid.

Next, a Ti film (not shown) is deposited on the entire surface, and the surface of the Si substrate 11 and the upper surface of the polycrystalline Si film 14 are reacted with the Ti film by heat treatment to form a reaction shown in FIG. As shown, a low-resistance TiSi ₂ film 21 is formed on these surfaces in a self-aligned manner. And soak in ammonia peroxide, etc.
Ti remaining unreacted on the SiO ₂ films 12 and 16
The film is selectively removed.

[0007] Next, as shown in FIG. 5 (c), an interlayer insulating film of SiO ₂ film 22 or the like, to form a connection hole 23 to the SiO ₂ film 22 or the like, TiN / Ti film 24 and the blanket The connection hole 23 is filled with a W film 25 or the like by the CVD method.
Then, the Ti film 26 and the Al film 27 are processed into a wiring pattern.

In one conventional example as described above, the diffusion layers 15, 1
7 and the TiSi ₂ film 21 constitute the source / drain, and the polycrystalline Si film 14 and the TiSi ₂ film 21 constitute the gate electrode. The sheet resistance of the source / drain and the gate electrode is lower than that of only the gate electrode. Further, the diffusion layer 1 is made of As having a diffusion coefficient smaller than P.
5 and 17, these diffusion layers 15, 1
7 is shallow.

[0009]

However, as the line width of the source / drain and the gate electrode is reduced in order to advance the miniaturization of the NMOS transistor, particularly, As
Is high, TiSi ₂ reacts with As to form TiS
formation of i ₂ is inhibited. As a result, the TiSi ₂ film 21
Agglomeration and the like occur, and it becomes difficult to form source / drain and gate electrodes having low sheet resistance (for example,
IEICE Technical Report SDM95-202 (1996-01) p. 9
-15).

In addition, when shallow diffusion layers 15 and 17 are formed in order to manufacture a fine NMOS transistor, TiSi is used to suppress a junction leak current between the diffusion layers 15 and 17 and the Si substrate 11 due to alloy spikes or the like. ₂ membrane 2
One needs to be thin. Therefore, the TiSi ₂ film 21
Therefore, aggregation and the like are more likely to occur, and it becomes more difficult to form source / drain and gate electrodes having low sheet resistance.

On the other hand, if the concentration of As is lowered,
Source / drain and gate electrodes with low sheet resistance can be formed. However, if the concentration of As in the polycrystalline Si film 14 is not sufficiently high, a depletion layer occurs in the polycrystalline Si film 14 between the TiSi ₂ film 21 and the SiO ₂ film 13 when a gate voltage is applied, and the capacitance is increased. Occurs. Since this capacitance is connected in series with the capacitance of the SiO ₂ film 13,
The capacity of the entire gate electrode is reduced, and the current driving capability of the NMOS transistor is reduced.

On the other hand, when a CoSi ₂ film is formed as a silicide film, even if the concentration of As as an impurity is high, C
Since oSi ₂ does not react with As, it is considered that formation of CoSi ₂ is not inhibited. However, when the line width of the source / drain and the gate electrode is small and the concentration of As is high,
Still, a low-resistance CoSi ₂ film cannot be formed.

FIG. 1 shows the relationship between the dose of As to the polycrystalline Si film and the sheet resistance of the gate electrode formed by forming a CoSi ₂ film on the upper surface of the polycrystalline Si film in a self-aligned manner. Have been. As is apparent from FIG. 1, as the dose of As increases, the sheet resistance of the gate electrode greatly increases. The cause is considered as follows.

That is, when a large amount of heavy As is ion-implanted into the polycrystalline Si film, an amorphous layer is formed near the upper surface of the polycrystalline Si film. In the heat treatment, the amorphous layer is recrystallized so as to be aligned with the underlying crystal orientation. At this time, the crystal grain size of the polycrystalline Si film is relatively large when the line width is large, and relatively small when the line width is small. Many crystal grain boundaries are formed near the upper surface. This phenomenon occurs remarkably in Sb, which is a donor atom having a large atomic number, in addition to As.

Oxidation proceeds near the upper surface of the polycrystalline Si film at the same time as the heat treatment for activating the ion-implanted As. However, as described above, there are many crystal grain boundaries near the upper surface. Many non-uniform oxide films are formed along the boundary. This oxide film is removed with dilute hydrofluoric acid before depositing the Co film. However, among the non-uniform oxide films, the oxide film grown to a deep position along the crystal grain boundary cannot be completely removed.

Since Co is very easily oxidized, polycrystalline S
If the oxide film remains near the upper surface of the i-film,
In forming the Si ₂ film, the compounding reaction cannot be uniformly generated, and a low-resistance CoSi ₂ film cannot be formed. In contrast, A for the polycrystalline Si film
If the dose of s is reduced, the formation of an amorphous layer near the upper surface of the polycrystalline Si film can be suppressed, and a gate electrode with low sheet resistance can be formed.

However, if the concentration of As in the polycrystalline Si film is not sufficiently high, as in the case of the TiSi ₂ film 21, the polycrystalline Si film between the CoSi ₂ film and the gate oxide film when a gate voltage is applied is formed. A depletion layer occurs in the film. In FIG. 1,
The relationship between the dose of As to such a polycrystalline Si film and the depletion rate of the gate electrode is also shown. Note that C in FIG.
in is the above-described series capacitance, and Cox is the capacitance due to only the gate oxide film. Therefore, if Cin is equal to Cox without a depletion layer in the polycrystalline Si film, the depletion rate is zero.

As is clear from FIG. 1, when the dose of As with respect to the polycrystalline Si film is reduced to about 3 × 10 ¹⁵ / cm ² , the sheet resistance of the gate electrode is reduced, but about 20% is applied to the gate electrode. Depletion occurs. Conversely, when depletion is suppressed to about 10%, the sheet resistance increases. The phenomenon shown in FIG. 1 is noticeable in a fine MOS transistor having a line width of about 0.25 μm or less.
It is empirically known that the performance of an OS transistor is significantly reduced.

Accordingly, the invention of the present application provides a method capable of manufacturing a semiconductor device which has high current driving capability, is fine, and operates at high speed even with low driving voltage and low power consumption. The purpose is.

[0020]

In the method of manufacturing a semiconductor device according to the present invention, since the Si film of the pattern of the gate electrode contains not only donor atoms having an atomic number of 33 or more but also P, the content of the donor atoms is reduced. By increasing the P content even if the amount is small, a gate electrode which is hardly depleted can be formed. Further, since the content of the donor atoms may be small, aggregation or the like hardly occurs in the silicide film formed on the upper surface of the Si film, and a gate electrode with low sheet resistance can be formed.

On the other hand, since only the donor atoms having a small diffusion coefficient are introduced into the region where the source / drain is to be formed and P having a large diffusion coefficient is not introduced, a shallow source / drain diffusion layer can be formed. Further, since the content of the donor atoms may be small, even if the silicide film formed on the surface of the source / drain diffusion layer is thin, aggregation or the like is unlikely to occur. Source / drain with low sheet resistance can be formed while suppressing leakage current.

When a heat treatment for activating donor atoms and P is performed in a state where the Si film and the Si substrate are covered with the antioxidant film, the oxide film is formed on the upper surface of the Si film and the surface of the Si substrate. Is prevented. For this reason, a compounding reaction can be uniformly generated in the subsequent formation of the silicide film, and a gate electrode and a source / drain having a lower sheet resistance can be formed.

When an amorphous Si film is used as the Si film, the heat treatment for activating the donor atoms and P causes
Even if an oxide film is formed on the upper surface of the i film, the oxide film is formed uniformly, so that the oxide film can be easily removed prior to the subsequent formation of the silicide film. For this reason,
In the subsequent formation of the silicide film, a compounding reaction can be uniformly generated, and a gate electrode having a lower sheet resistance can be formed.

When a laminated film of a polycrystalline Si film and an amorphous Si film is used as a Si film, the underlying polycrystalline Si film becomes a seed by heat treatment for activating donor atoms and P. The amorphous Si film is recrystallized into large crystal grains having few crystal grain boundaries. As a result, even if heat treatment for activation is performed, a non-uniform oxide film along the crystal grain boundaries is hardly formed, and the oxide film can be easily removed prior to the subsequent formation of the silicide film. For this reason, a compounding reaction can be uniformly generated in the subsequent formation of the silicide film, and a gate electrode with a lower sheet resistance can be formed.

Further, if heat treatment for activating the donor atoms and P is performed in a non-oxidizing atmosphere, formation of an oxide film on the upper surface of the Si film and the surface of the Si substrate is prevented. For this reason, a compounding reaction can be uniformly generated in the subsequent formation of the silicide film, and a gate electrode and a source / drain having a lower sheet resistance can be formed.

[0026]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, CoS is used as a silicide film.
First to sixth embodiments of the present invention applied to a method of manufacturing a CMOS transistor in which an i ₂ film is formed in a self-aligned manner will be described with reference to FIGS.

FIG. 2 shows the first embodiment. In the first embodiment, as shown in FIG.
An SiO ₂ film 32 as an element isolation oxide film is formed on the surface of
After forming the P well 35 and the N well 36 in the i-substrate 31, respectively, an SiO ₂ film 37 as a gate oxide film is formed on the surface of the element active region surrounded by the SiO ₂ film 32.

Then, the thickness of 2 was obtained by the CVD method under the following conditions.
A polycrystalline Si film 41 of 00 nm is deposited on the SiO ₂ films 32 and 37. Gas: SiH ₄ / He / N ₂ = 100/400/200
sccm Pressure: 70 Pa Substrate temperature: 610 ° C

Then, 5 × 10 5 is applied to the polycrystalline Si film 41 in the N-channel region 33 at an acceleration energy of 10 keV by using a resist (not shown) having an appropriate pattern as a mask.
The P ions are implanted at a dose of ¹⁵ / cm ^2, the B at a dose of polycrystalline Si film 41 3 × 10 ¹⁵ / cm ² of P channel region 34 is ion-implanted.

Thereafter, the polycrystalline Si film 41 is processed into a gate electrode pattern by dry etching under the following conditions. Gas: Cl ₂ / O ₂ / HBr = 75/2/120 scc
m Pressure: 1 Pa High frequency power: 60 W Microwave power: 850 W

Then, using the polycrystalline Si film 41 and the SiO ₂ film 32 and a resist (not shown) having an appropriate pattern as a mask, an acceleration energy of 30 keV and 1 × 10 ¹³
At a dose of / cm ² , As and B are ion-implanted into the Si substrate 31 of the N-channel region 33 and the P-channel region 34, respectively, to form the low-concentration diffusion layers 42 and 43 forming the source / drain of the LDD structure. Form each.

Next, as shown in FIG. 2B, a 300 nm thick SiO ₂ film 44 is deposited on the entire surface by the CVD method under the following conditions. Gas: TEOS = 50 sccm Temperature: 720 ° C. Pressure: 40 Pa

[0033] Then, by etching back the entire surface of the SiO ₂ film 44 under the following conditions, polycrystalline S in the SiO ₂ film 44
A side wall spacer of the i film 41 is formed. Gas: C ₄ F ₈ = 50 sccm High frequency power: 1.2 kW Pressure: 2 Pa

After that, using the polycrystalline Si film 41 and the SiO ₂ films 32 and 44 and a resist (not shown) having an appropriate pattern as a mask, the N amount is set to 3 × 10 ¹⁵ / cm ² and
As ions are implanted into the Si substrate 31 in the channel region 33 at an acceleration energy of 60 keV, and BF ₂ ions are implanted into the Si substrate 31 in the P-channel region 34 at an acceleration energy of 40 keV to form a source / drain having an LDD structure. High concentration diffusion layers 45 and 46 are formed respectively.

Then, a short-time heat treatment at about 1000 ° C. is performed to diffuse the diffusion layers 42, 43, 45, 46 and the polycrystalline Si.
The impurities P, As, and B in the film 41 are activated. By this heat treatment, an oxide film (not shown) is formed on the surface of the Si substrate 31 and the upper surface of the polycrystalline Si film 41. Also,
Even if an oxide film is not formed, since a natural oxide film exists, these oxide films are removed with dilute hydrofluoric acid.

Next, a thickness of 2
A 0 nm Co film (not shown) is deposited on the entire surface. Power: 1 kW Gas: Ar = 100 sccm Pressure: 0.47 Pa

Instead of depositing a Co film having a thickness of 20 nm, a sputtering method under the following conditions is used.
An nm Co film and a 6 nm thick Ti film may be continuously deposited. Conditions for depositing Co film Conditions for depositing Ti film Power: 1 kW Power: 0.5 kW Gas: Ar = 100 sccm Gas: Ar = 100 sccm Pressure: 0.47 Pa Pressure: 0.47 Pa

Further, instead of depositing a Co film having a thickness of 20 nm, a sputtering method under the following conditions is used to deposit a Co film having a thickness of 10 nm.
A Co film having a thickness of 20 nm and a TiN film having a thickness of 20 nm may be continuously deposited. Conditions for depositing Co film Conditions for depositing TiN film Power: 1 kW Power: 5 kW Gas: Ar = 100 sccm Gas: Ar / N ₂ = 40/20 sccm Pressure: 0.47 Pa Pressure: 0.47 Pa

Then, the surface of the Si substrate 31 and the upper surface of the polycrystalline Si film 41 are reacted with the Co film by a short-time heat treatment in the first stage under the following conditions, and as shown in FIG. A CoSi ₂ film 47 is formed on these surfaces in a self-aligned manner. Gas: N ₂ = 5 L / min Temperature: 550 ° C Time: 30 seconds

Thereafter, the SiO ₂ film 3 is immersed in sulfuric acid and hydrogen peroxide.
A Co film, a Ti film, a TiN film, and the like remaining unreacted on the layers 2 and 44 are selectively removed. The TiN film is made of Co.
The oxidation of the surface of the film can be suppressed, and the Ti film can not only suppress the oxidation but also reduce the natural oxide film on the surface of the Si substrate 31 under the Co film and the upper surface of the polycrystalline Si film 41.

Then, the CoSi ₂ film 47 undergoes a phase transition to a stable and low-resistance crystal structure by the second-stage short-time heat treatment under the following conditions. Gas: N ₂ = 5 L / min Temperature: 700 ° C Time: 30 seconds

Next, as shown in FIG. 2D, an SiO ₂ film 51 having a thickness of 600 nm is deposited by a CVD method under the following conditions to form an interlayer insulating film. Gas: TEOS = 50 sccm Temperature: 720 ° C. Pressure: 40 Pa

[0043] Then, a resist is patterned (not shown) on the SiO ₂ film 51, dry etching under the following conditions with the resist as a mask to form a connection hole 52 in the SiO ₂ film 51. Gas: C ₄ F ₈ = 50 sccm High frequency power: 1.2 kW Pressure: 2 Pa

Thereafter, a Ti film having a thickness of 10 nm and a TiN film having a thickness of 70 nm are continuously deposited by a sputtering method under the following conditions to form a TiN / Ti film 53. Deposition conditions for Ti film Deposition conditions for TiN film Power: 8 kW Power: 5 kW Temperature: 150 ° C. Gas: Ar / N ₂ = 40/20 sccm Gas: Ar = 100 sccm Pressure: 0.47 Pa Pressure: 0.47 Pa

Then, a thickness of 4 was obtained by the CVD method under the following conditions.
A W film 54 of 00 nm is deposited. Gas: Ar / N ₂ / H ₂ / WF ₆ = 2200/300 /
500/75 sccm Temperature: 450 ° C Pressure: 10640 Pa

Thereafter, the W film 54 and the TiN
The entire surface of the / Ti film 53 is etched back to
The connection holes 52 are filled with the N / Ti film 53 and the W film 54. Gas: SF ₆ = 50 sccm High frequency power: 150 W Pressure: 1.33 Pa

Then, a 30 nm-thick Ti film 55 is deposited by sputtering under the following conditions. Power: 4 kW Temperature: 150 ° C. Gas: Ar = 100 sccm Pressure: 0.47 Pa

Then, an Al film 56 having a thickness of 0.5 μm is deposited by a sputtering method under the following conditions. Power: 22.5 kW Temperature: 150 ° C. Gas: Ar = 50 sccm Pressure: 0.47 Pa

Thereafter, a resist (not shown) is patterned on the Al film 56, and the Al film 56 and the Ti film 55 are processed into a wiring pattern by dry etching under the following conditions using the resist as a mask. Gas: BCl ₃ / Cl ₂ = 60/90 sccm Microwave power: 1 kW High frequency power: 50 W Pressure: 0.016 Pa

[0050] In the drawing 1, ions are implanted both the 3 × 10 ¹⁵ / cm ² dose of about of As and 3~5 × 10 ¹⁵ / cm ² dose of about of P into the polycrystalline Si film Data for the case is also shown, and this condition corresponds to the condition in the first embodiment described above. Therefore, in the first embodiment described above, it is possible to manufacture a CMOS transistor having a gate electrode which is hardly depleted and has a low sheet resistance.

FIG. 3 shows a step in the middle of the second embodiment. In the second embodiment, after the diffusion layers 45 and 46 are formed, a thickness of 30 nm is formed by a low pressure CVD method under the following conditions.
Is deposited. Gas: SiH ₂ Cl ₂ / NH ₃ / N ₂ = 0.05 / 0.
2 / 0.2 slm Pressure: 70 Pa Temperature: 760 ° C

Then, furnace heat treatment at 800 ° C. and 1000 ° C.
The heat treatment is performed for a short time to the extent that the diffusion layers 42, 43, 4
5, 46 and the impurities P and A in the polycrystalline Si film 41.
Activate s and B. Then, the SiN film 5 is heated with hot phosphoric acid.
After removing 7, the oxide film is removed with dilute hydrofluoric acid. Except for the above points, the second embodiment executes substantially the same steps as the above-described first embodiment.

Although the surface of the polycrystalline Si film 41 containing As is easily oxidized, in the second embodiment described above,
Since the film 57 serves as an antioxidant film, an oxide film is not easily formed on the upper surface of the polycrystalline Si film 41 even if heat treatment for activating impurities is performed. Therefore, the subsequent CoSi ₂ film 4
7, the silicidation reaction can be uniformly generated, and a CMOS transistor having a gate electrode with a lower sheet resistance can be manufactured.

Next, a third embodiment will be described. This third
In the embodiment, after forming the diffusion layers 45 and 46, a polycrystalline Si film having a thickness of 10 nm is deposited by the CVD method under the following conditions. Gas: SiH ₄ / He / N ₂ = 100/400/200
sccm Pressure: 70 Pa Substrate temperature: 610 ° C

Then, furnace heat treatment at 800 ° C. and 1000 ° C.
The heat treatment is performed for a short time to the extent that the diffusion layers 42, 43, 4
5, 46 and the impurities P and A in the polycrystalline Si film 41.
Activate s and B. Thereafter, the oxide film is removed with dilute hydrofluoric acid. Except for the above points, the third embodiment executes substantially the same steps as those of the first embodiment.

In the third embodiment, the diffusion layers 45, 4
The polycrystalline Si film deposited after the formation of 6 becomes an antioxidant film, and this polycrystalline Si film becomes an SiO ₂ film by furnace heat treatment. Therefore, when the oxide film is subsequently removed with dilute hydrofluoric acid, this SiO ₂ film can be removed at the same time, and an additional removal step is not required.

Next, a fourth embodiment will be described. In the above-described first embodiment, the substrate temperature when depositing the polycrystalline Si film 41 is 610 ° C., but in the fourth embodiment, the temperature at this time is also set to 580 ° C. Instead, substantially the same steps as those of the first embodiment are performed except that an amorphous Si film is formed.

In the fourth embodiment, even if an oxide film is formed on the upper surface of the amorphous Si film by the heat treatment for activating the impurities, the oxide film is uniformly formed. This oxide film can be easily removed by treatment with dilute hydrofluoric acid. For this reason, a silicidation reaction can be uniformly generated in the subsequent formation of the CoSi ₂ film 47, and a CMO having a gate electrode with a lower sheet resistance can be obtained.
An S transistor can be manufactured.

FIG. 4 shows a step in the middle of the fifth embodiment. In the fifth embodiment, after forming the SiO ₂ film 37 as a gate oxide film, by a CVD method under the following conditions, the polycrystalline Si film 61 having a thickness of 150 nm SiO ₂ film 3
2. Deposit on 37. Gas: SiH ₄ / He / N ₂ = 100/400/200
sccm Pressure: 70 Pa Substrate temperature: 620 ° C

Subsequently, the amorphous Si film 62 having a thickness of 50 nm is formed on the polycrystalline Si film 6 by the CVD method under the following conditions.
1 on top. Gas: SiH ₄ / He / N ₂ = 100/400/200
sccm Pressure: 70 Pa Substrate temperature: 580 ° C

That is, the polycrystalline Si film 61 and the polycrystalline S
and an amorphous Si film 62 laminated on the i-film 61
Except that the fifth embodiment is formed instead of the i-film 41, the fifth embodiment performs substantially the same process as the first embodiment. In the fifth embodiment as described above, the heat treatment for activating the impurities causes the underlying polycrystalline Si film 61 to become a seed and recrystallize the amorphous Si film 62 into large crystal grains having few crystal grain boundaries. Become

As a result, even if heat treatment for activation is performed, a non-uniform oxide film along the crystal grain boundaries is hardly formed, and this oxide film can be easily removed by the subsequent treatment with dilute hydrofluoric acid. . For this reason, the silicidation reaction can be uniformly caused in the subsequent formation of the CoSi ₂ film 47, and the CSi having the gate electrode with a lower sheet resistance can be formed.
MOS transistors can be manufactured.

Next, a sixth embodiment will be described. This sixth
The embodiment also performs substantially the same steps as the above-described first embodiment, except that the impurities are activated by a short-time heat treatment in a non-oxidizing atmosphere such as nitrogen. However, the rate of temperature rise and fall during the short-time heat treatment is set to 10 ° C./sec or less,
The generation of stress due to the short-time heat treatment is suppressed, and the junction leakage current via crystal defects is suppressed.

In the sixth embodiment, no oxide film is formed on the upper surface of the polycrystalline Si film 41 even if heat treatment for activating impurities is performed. For this reason, the subsequent CoSi
_A silicidation reaction can be uniformly generated when the _second film 47 is formed, and a CMOS transistor having a gate electrode with a lower sheet resistance can be manufactured.

As is clear from the above description of the first to sixth embodiments, any of these first to sixth embodiments is
Since only simple steps that are an extension of the conventional manufacturing method are performed, an increase in manufacturing cost due to a decrease in yield or the like can be suppressed. In each of the first to sixth embodiments, As is ion-implanted in order to form the diffusion layers 42 and 45, but the atomic number is larger than 33 and acts as a donor for Si. An atom such as Sb may be ion-implanted instead of As.

In each of the first to sixth embodiments, a CoSi ₂ film is formed as a silicide film.
A film of any of Ti, W, Ni, Pt, Zr, Hf, Pd or Mo is formed instead of the Co film, and TiSi ₂ ,
WSi ₂ , NiSi, NiSi ₂ , PtSi, PtSi
₂ , ZrSi ₂ , HfSi ₂ , Pd ₂ Si, PdSi,
PdSi ₂ , PdSi ₃ , PdSi ₄ or MoSi ₂
May be formed in place of the CoSi ₂ film 47.

In each of the first to sixth embodiments, a Co film is deposited by a sputtering method. However, a Co film may be deposited by a CVD method. In each of the first to sixth embodiments, the present invention is applied to a method for manufacturing a CMOS transistor. However, the present invention is also applied to a method for manufacturing other semiconductor devices such as only an NMOS transistor or a CCD. The invention can be applied.

[0068]

According to the method of manufacturing a semiconductor device according to the present invention, a gate electrode which is hardly depleted and has low sheet resistance and a source / drain which is shallow and has low sheet resistance can be formed. , Fine,
In addition, a semiconductor device which operates at high speed even with low driving voltage and low power consumption can be manufactured.

When a heat treatment for activating donor atoms and P is performed in a state where the Si film and the Si substrate are covered with the antioxidant film, a gate electrode and a source / drain having a lower sheet resistance can be formed. Therefore, a semiconductor device with higher operation speed can be manufactured.

Further, when an amorphous Si film or a laminated film of a polycrystalline Si film and an amorphous Si film is used as a Si film, a gate electrode having a further lower sheet resistance can be formed. Further, a high-speed semiconductor device can be manufactured.

If a heat treatment for activating the donor atoms and P is performed in a non-oxidizing atmosphere, a gate electrode and a source / drain having a lower sheet resistance can be formed. A semiconductor device can be manufactured.

[Brief description of the drawings]

FIG. 1 is a graph showing a relationship between a dose amount of As, a sheet resistance of a gate electrode, and a depletion ratio.

FIG. 2 is a side sectional view showing the first embodiment of the present invention in the order of steps.

FIG. 3 is a side sectional view showing a step in the middle of a second embodiment of the present invention.

FIG. 4 is a side sectional view showing a step in the middle of a fifth embodiment of the present invention.

FIG. 5 is a side sectional view showing a conventional example of the invention of the present application in the order of steps.

[Explanation of symbols]

31 ... Si substrate, 41 ... Polycrystalline Si film (Si film), 47
... CoSi ₂ film (silicide film), 57 ... SiN film (antioxidant film), 61 ... polycrystalline Si film, 62 ... amorphous Si film

Claims (10)

[Claims] A step of forming a Si film containing P and having a pattern of a gate electrode on a Si substrate; and forming a source / drain region on the Si substrate and the Si film. Introducing an atom having an atomic number of 33 or more and acting as a donor with respect to Si;
Manufacturing a semiconductor device, comprising: forming a metal film on a film; and forming a silicide film by performing a chemical reaction between the surface of the region and the upper surface of the Si film and the metal film. Method. A step of forming an antioxidant film covering the Si film and the Si substrate after introducing the atoms and before forming the metal film; and forming the antioxidant film on the Si film and the Si substrate. 2. The method of manufacturing a semiconductor device according to claim 1, further comprising: performing a heat treatment for activating the atoms and the P in a state of being covered with a film. 3. The method for manufacturing a semiconductor device according to claim 1, wherein an amorphous Si film is used as said Si film. 4. The method according to claim 1, wherein a polycrystalline Si film and an amorphous Si film laminated on the polycrystalline Si film are used as the Si film. 5. The method according to claim 1, wherein the heat treatment for activating the atoms and the P is performed in a non-oxidizing atmosphere. 6. The method according to claim 1, wherein the content of P is 5 × 10 ¹⁵ / cm ² or more. 7. An atomic content of 4 × 10 ¹⁵ / cm ^2.
2. The method for manufacturing a semiconductor device according to claim 1, wherein: 8. The method according to claim 1, wherein an SiN film or a polycrystalline Si film is used as the oxidation preventing film. 9. Co, Ti, W, Ni, Pt, Zr, H
2. The method according to claim 1, wherein one of f, Pd, and Mo is used as the metal. 10. CoSi ₂ , TiSi ₂ , WSi ₂ ,
NiSi, NiSi ₂ , PtSi, PtSi ₂ , ZrS
i ₂ , HfSi ₂ , Pd ₂ Si, PdSi, PdS
_{2. The} method according to claim 1, wherein one of i ₂ , PdSi ₃ , PdSi _{4 and} MoSi ₂ is formed as the silicide.