KR100620235B1 - Method for manufacturing Ti-silicide - Google Patents

Abstract

The present invention relates to a method for manufacturing titanium silicide, and more particularly, forming a gate electrode and a spacer on a semiconductor substrate, performing a sputtering process of Ti on the structure, implanting Mo ions after forming a Ti layer, and annealing. Depositing an amorphous silicon layer on the Ti layer, depositing a TEOS film on the amorphous silicon layer, performing a chemical mechanical polishing process, performing an etch back using wet etching using BOE, The technical features include removing the amorphous silicon layer in front of the gate, wet etching the amorphous layer except the amorphous silicon layer in the silicon subregion, removing the remaining TEOS film, and forming Ti silicide by primary annealing. have.

Therefore, the titanium silicide manufacturing method of the present invention can easily form a C54 phase by forming Ti silicide having a low resistance by only performing primary annealing at low temperature and Mo ion implantation which can be easily phase-shifted to the C54 phase of the Ti embodiment. And the junction leakage is small due to the large gap between the Ti silicide layer and the source / drain junction. In addition, process margins are increased by reducing the thermal budget through low temperature annealing, and the increase in resistance due to the reduction of the line width is reduced due to the effective C54 phase formation.

Silicide, PAL

Description

Titanium silicide manufacturing method {Method for manufacturing Ti-silicide}             

1A to 1D are cross-sectional views showing a method for preparing titanium silicide according to the prior art.

Figure 2a to 2e is a cross-sectional view showing a method for producing titanium silicide according to the present invention.

The present invention relates to a method for preparing titanium silicide, and more particularly, to form Ti silicide having low resistance by performing Mo ion implantation, which can be easily phase-converted to the C54 phase of the Ti embodiment, and primary annealing at a low temperature, thereby forming a C54 phase. Can be easily formed, and the junction leakage is small due to the large gap between the Ti silicide layer and the source / drain junction. It also relates to increased process margins by reducing the thermal budget through low temperature annealing.

As semiconductor devices become more integrated, higher in performance, and lower in voltage, low resistance gate materials are required to reduce transistor and cell gate lengths and improve device characteristics through the formation of fine patterns, and channel currents of transistors and cells due to lower voltage are increased. In order to increase the thickness of the gate oxide film is gradually reduced.

In addition, the junction depth of the source / drain regions should be shallow in order to prevent short channel effects due to the reduction of the gate length of the transistor and to secure a margin for punchthrough. At the same time, the parasitic resistance of the source / drain regions, such as sheet resistance and contact resistance, must be reduced.

Accordingly, studies have been made on silicide processes for reducing the resistivity of the gate electrode and the sheet resistance and contact resistance of the source / drain regions by forming a silicide layer on the surfaces of the gate electrode and the source / drain regions. The salicide process is a method of selectively forming a silicide material such as titanium (Ti) -silicide (TiSix) only in the gate and source / drain regions.

1A to 1D are cross-sectional views showing a method for preparing titanium silicide according to the prior art.

First, as shown in FIG. 1A, the semiconductor substrate 11 is separated from each other by a well-known shallow trench isolation (STI) technique. Then, a conductive material for a gate, such as polycrystalline silicon, is deposited thereon, and the photolithography process is performed. The gate electrode 103 is formed by patterning.

Next, a low concentration source / drain region (not shown) self-aligned to the gate electrode 103 by implanting P-type impurities such as boron ions at a low concentration in the case of an N-channel MOS transistor on the gate electrode 103. ).

Next, a spacer 102 is formed on the sidewall of the gate electrode 103 by depositing silicon nitride with an insulating material on the front surface and then anisotropically etching the silicon nitride. By implanting ions at a high concentration after the process, a high concentration source / drain region (not shown) is self-aligned to the spacer 102. As a result of the above process, a source / drain of a lightly doped drain (LDD) structure is formed.

Next, in order to form silicide using titanium, an amorphous ion implantation pretreatment (PAI) process is performed to inject arsenide ions onto the entire surface of the semiconductor substrate 101 before titanium deposition.

The amorphous ion implantation pretreatment process is used to amorphize the surface of the drain / source region and the gate to increase grain boundary intersection regions in the drain / source region and the gate to facilitate silicide formation.

Next, as shown in FIG. 1B, a transition metal film having magnetic properties in the gate electrode 103 and the source / drain regions is formed by plasma vapor deposition (PVD) or chemical vapor deposition (CVD) using plasma. The transition metal film uses Ti, but may be selected from the group consisting of Co, Ni and the like.

Next, a Ti silicide layer 104 may be formed on both the polysilicon gate 103 and the source / drain region by reaction of the polysilicon gate 103, the source / drain region, and the transition metal film. Heat treatment is performed.

In this embodiment, the heat treatment is performed by two successive steps, low temperature rapid thermal annealing (RAT) and high temperature thermal treatment. After forming the silicide layer 104, the unreacted portions of the transition metal film are selectively removed.

Next, as shown in FIG. 1C, a second heat treatment process is performed in a gas atmosphere using one of ammonia, nitrogen, and argon, and the silicon of the semiconductor substrate 101 and the gate electrode 103 on which the source / drain regions are formed. Ti in the Ti film is reacted to form a TiSi ₂ silicide film 104.

The Ti silicide formation is annealed in two steps. That is primary is to remove the Ti is not conducted, and the reaction of the annealing at a low temperature at 720 ℃ a wet cleaning (wet cleaning) (the chemical structure of TiSi ₂ (C49 formed by primary annealing), 2 car rather high temperature of 825 ℃ Annealing with TiO ₂ forms a C54 phase with low resistance.

In order to better form the lattice structure with TiSi ₂ on C54, a silicon substrate is formed into an amorphous layer by performing a PAI process before Ti sputtering.

However, even with PAI, phase change does not occur completely with low C54 resistance, and when annealing at a higher temperature, the resistance rapidly increases due to agglomeration of Ti silicide.

In addition, since the annealing of the silicide is performed in two stages, the cost is increased, and the resistance of the silicide is increased as the line width is reduced by the sudden design rule of the semiconductor device. The high temperature of the second step during the second step of annealing causes a process problem such as an increase in the junction depth of the previous process due to the thermal budget.

Accordingly, the present invention is to solve the above-mentioned disadvantages and problems of the prior art, the Ti silicide is low resistance by performing only the first annealing at low temperature and Mo ion implantation that can be easily phase-shifted to the C54 phase of Ti silicide. The C54 phase can be easily formed, and the junction leakage is small due to the large gap between the Ti silicide layer and the source / drain junction. It is also an object of the present invention to reduce heat loss through annealing at lower temperatures to provide an increase in process margins.

layer

The above object of the present invention is to form a gate electrode and a spacer on a semiconductor substrate, to perform a sputtering process of the Ti layer on the structure, and after the Ti layer formation Mo ion implantation, annealing, on the Ti layer Depositing an amorphous silicon layer, depositing a TEOS film on the amorphous silicon layer, performing a chemical mechanical polishing process, performing an etch back using wet etching using BOE, an amorphous silicon layer in front of the gate It is achieved by a method of manufacturing a titanium silicide comprising the steps of: removing the wet, wet etching the amorphous layer except the amorphous silicon layer of the silicon sub-region, removing the remaining TEOS film, and forming Ti silicide by primary annealing.

Details of the above object and technical configuration of the present invention and the effects thereof according to the present invention will be more clearly understood by the following detailed description with reference to the drawings showing preferred embodiments of the present invention.

The performance of the transistor is closely related to the speed, drive current, and leakage current of the transistor. In order to improve the performance of the transistor, the speed and driving current of the transistor must be large and the leakage current must be small.

In order to increase the speed and driving current of the transistor and to reduce the leakage current, the resistance of the source and drain of the transistor, the resistance of the gate of the transistor, and the contact resistors must be made small.

A silicide process is used to silicide the interface of the drain / source and the interface of the gate to reduce the resistance of the source and drain of the transistor, the resistance of the gate of the transistor, and the resistance of the contact resistors.

2A to 2E are cross-sectional views showing a silicide manufacturing method according to the present invention.

First, as shown in Figure 2a. Ti is sputtered on the structure of the gate electrode 203 in which the gate electrode 203 and the spacer 202 are formed on the semiconductor substrate 201. After the Ti layer 204 is formed, a Mo ion implantation process is performed. The annealing process for activating the ion implanted Mo is performed for 30 seconds to 40 seconds at 600 ℃ to 650 ℃.

Next, an amorphous silicon layer 205 is deposited on the Ti layer 204 as shown in FIG. 2B. The amorphous silicon layer reduces the Ti silicide thickness to the silicon sub and increases the silicide thickness upwards to lower contact resistance and reduce source / drain junction leakage.

Next, as shown in FIG. 2C, a TEOS (Tetra Ethyl Ortho Silicate) film 206 is deposited on the amorphous silicon layer 205. Thereafter, a chemical mechanical polishing (CMP) process is performed to perform a planarization process.

Next, as shown in FIG. 2D, etching back is performed using wet etching using a buffered oxide etchant (BOE), and the amorphous silicon layer 205 in front of the gate is removed.

Next, as shown in FIG. 2E, the amorphous layer except for the amorphous silicon layer of the silicon subregion is removed by wet etching. Thereafter, the remaining TEOS film is removed and Ti silicide 204 is formed by primary annealing.

The embodiment of the present invention described above can easily form a C54 phase by forming Ti silicide with low resistance by only performing primary annealing at low temperature and Mo ion implantation which can be easily phase-shifted to the C54 phase of the Ti implementation side, The junction leakage is small due to the large gap between the silicide layer and the source / drain junction. In addition, process margins can be increased by reducing heat loss through low temperature annealing, and the increase in resistance due to line width reduction can be alleviated due to effective C54 phase formation.

Although the present invention has been shown and described with reference to the preferred embodiments as described above, it is not limited to the above embodiments and those skilled in the art without departing from the spirit of the present invention. Various changes and modifications will be possible.

Therefore, the method for preparing titanium silicide of the present invention can easily form a C54 phase by forming Ti silicide having low resistance by only performing primary annealing at low temperature and Mo ion implantation which can easily phase-change the C54 phase of the Ti implementation side. And the junction leakage is small due to the large gap between the Ti silicide layer and the source / drain junction. In addition, process margins are increased by reducing the thermal budget through low temperature annealing, and the increase in resistance due to the reduction of the line width is reduced due to the effective C54 phase formation.

Claims (3)

In the method for producing titanium silicide, (A) forming a gate electrode and a spacer on the semiconductor substrate; (B) performing a sputtering process of Ti on the structure, implanting Mo ions after forming the Ti layer, and performing an annealing process for activating the Mo; (C) depositing an amorphous silicon layer on the Ti layer; (D) depositing a TEOS film on the amorphous silicon layer and performing a chemical mechanical polishing process; (E) performing etch back using wet etching using BOE; (F) removing the amorphous silicon layer in front of the gate; (G) wet etching the amorphous layer except for the amorphous silicon layer of the silicon subregion; And (H) removing the remaining TEOS film and forming Ti silicide by annealing Titanium silicide manufacturing method comprising a. The method of claim 1, The annealing process for activating Mo in the (b) step is a temperature of 600 ℃ to 650 ℃, 30 seconds to 40 seconds time, characterized in that the titanium silicide manufacturing method. The method of claim 1, The Ti embodiment is a titanium silicide manufacturing method, characterized in that the C54 phase silicide.

Images