JP2014036213A - Semiconductor device and method for manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device capable of easily controlling a height and a width of a schottky barrier regardless of the kind of metal material, having low parasitic resistance and effectively suppressing short channel effect, and a method for manufacturing the same.SOLUTION: A gate electrode 3 is formed on a p-type silicon substrate 1 via a gate insulating film 2, and metal source drain electrodes 8 are formed on both sides of the gate electrode 3 on the p-type silicon substrate 1. A region 5 as an insulating layer is provided between the gate electrode 3 and the metal source drain electrode 8 on a surface of the p-type silicon substrate 1, a cesium-containing region 7 containing cesium is formed on a part or a whole of a region contacting with the metal source drain electrodes 8 on the p-type silicon substrate 1. Fixed charges exist in the insulating layer 5.

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof.

  Semiconductor integrated circuits have been improved in performance with miniaturization of MOSFETs (MOS field effect transistors), but in order to continue miniaturization of MOSFETs in the future, due to the short channel effect that becomes more prominent with miniaturization. It is essential to suppress characteristic deterioration. Here, in order to suppress the short channel effect, it is very effective to form the source / drain shallower. At the same time, in order to obtain a high on-current, the source / drain needs to have a low resistance.

  Usually, the source / drain is formed by ion-implanting a high concentration donor or acceptor into a semiconductor and then performing activation annealing. In order to reduce the source / drain junction depth formed in this way, it is necessary to reduce ion implantation energy (acceleration energy). However, if the ion implantation energy is extremely small (for example, 1 keV or less), it becomes difficult to secure a sufficient dose per unit time, which makes it very difficult to apply to a mass production process. Also, the junction depth becomes deep due to thermal diffusion of impurities by activation annealing. On the other hand, the source / drain resistance increases as the junction depth decreases. For these reasons, the shallow junction of the source / drain has become increasingly difficult in recent years.

  As a method for solving such a problem, a metal source / drain structure in which a source / drain is formed using a metal such as metal silicide has been proposed (for example, Non-Patent Document 1). The metal silicide is formed by depositing a metal on silicon as a semiconductor and then performing heat treatment such as RTA (Rapid Thermal Annealing). Since the film thickness of such a metal silicide can be controlled by the film thickness of the deposited metal, it is easy to control. Therefore, a very shallow source / drain can be easily formed. In addition, since the source and drain are made of metal, it is expected that the resistance can be very low.

  However, in the metal source / drain structure, since a Schottky junction is formed between the metal and the semiconductor, a leakage current between the source / drain and the semiconductor is large, and the channel and the source / drain are also formed. There is a problem that the on-current is reduced due to the Schottky barrier formed between the two.

  As an invention that can solve such a problem, there is a field effect transistor described in JP-A-2005-101588 (Patent Document 1). In this field effect transistor, impurities such as As and B are implanted into a silicon substrate as a semiconductor, and then metal silicide (metal source / drain) is formed to a region deeper than the region into which the impurity is implanted. Impurities are segregated in the vicinity of the interface between the metal silicide and silicon, and a depleted impurity-containing region having a conductivity type opposite to that of the silicon substrate is formed in a region in contact with the metal silicide.

  In this field effect transistor, since the junction characteristics between the metal source / drain and the semiconductor are intermediate characteristics between the pn junction and the Schottky junction, the leakage current is suppressed more than the structure of Non-Patent Document 1. be able to. Further, compared to the case of Non-Patent Document 1, the height of the Schottky barrier formed between the channel and the source / drain can be effectively reduced, and the on-current can be improved.

  However, in the technique disclosed in Patent Document 1, since it is necessary to form metal silicide to a position deeper than the region into which the impurity is implanted, the source / drain depth may be shallower than the impurity implantation depth. Can not. That is, there is a problem that it is impossible in principle to form a shallower source / drain than a conventional method of forming a source / drain using a pn junction.

  In addition, since the impurity used is a semiconductor donor impurity or acceptor impurity, the impurity is heated when heat treatment for recovering crystal defects caused by impurity activation or ion implantation is performed after the impurity implantation. Therefore, there is a problem that it becomes more difficult to form a shallow source / drain.

  Furthermore, in a MOSFET in which a source and a drain are formed using the technique disclosed in Patent Document 1, a drain leakage current due to GIDL (Gate Induced Drain Leakage) is large, so that power consumption increases. There are problems such as circuit malfunction. Further, since the gate electrode and the metal source / drain electrode are in contact with each other through a thin gate insulating film, there is a problem that a tunnel current increases and a leak current between the gate-source / drain increases. Such an increase in leakage current is particularly noticeable when the gate insulating film is thinned to 3 nm or less.

JP 2005-101588 A

See Wang, John P. Snyder, J. P. Snyder, JRTucker, "Applied Physics Letters", American Institute of the United States・ Physics (American Institute of Physics), Volume 74 (VOL.74), 1999, P.1174-1176

  Accordingly, an object of the present invention is to provide a semiconductor device capable of easily controlling the height and width of a Schottky barrier regardless of the type of metal material, having a low parasitic resistance, and effectively suppressing the short channel effect, and its It is to provide a manufacturing method.

In order to solve the above problems, a semiconductor device of the present invention is
A semiconductor layer;
A gate electrode formed on the semiconductor layer via a gate insulating film;
Metal source / drain electrodes formed on both sides of the gate electrode on the semiconductor layer;
Of the surface of the semiconductor layer, comprising an insulating layer provided on the portion sandwiched between the gate electrode and the metal source / drain electrode,
The semiconductor layer has a cesium-containing region containing cesium in part or all of a region in contact with the metal source / drain electrode,
A positive fixed charge is present in the insulating layer.

  According to the present invention, the semiconductor layer has a cesium-containing region containing cesium in part or all of the region in contact with the metal source / drain electrode. Here, since the ionization potential of cesium is the lowest among all elements, the energy level (impurity level) formed by cesium in the cesium-containing region is higher than the Fermi level of the metal source / drain electrode. Will be located. As a result, electrons are emitted from the cesium to the metal source / drain electrode side, and the cesium is positively ionized. In the cesium ionized region, the Schottky barrier at the interface between the metal source / drain electrodes and the cesium-containing region is greatly modulated (Schottky barrier modulation effect). That is, the Schottky barrier height with respect to holes increases effectively and the Schottky barrier height with respect to electrons decreases effectively. Therefore, in the N-type MOSFET, the leakage current between the semiconductor layer and the metal source / drain electrode can be remarkably suppressed, and the resistance between the channel and the metal source / drain electrode can be significantly reduced.

  Band bending occurs to the extent that the impurity level at a position sufficiently far from the metal source / drain electrode and the Fermi level of the metal source / drain electrode coincide with each other. As the energy difference from the level to the impurity level increases, the band bending increases and the Schottky barrier modulation effect increases. Since cesium has the smallest ionization potential (3.89 eV) among all elements, the Schottky barrier modulation effect can be most effectively obtained.

  According to the present invention, since positive fixed charges are present in the insulating layer, an electron carrier layer is induced on the surface of the semiconductor layer under the fixed charges, and functions as a very shallow source / drain extension. . Therefore, very good short channel effect characteristics can be obtained. Furthermore, due to the strong electric field effect due to the fixed charge, the thickness of the Schottky barrier for electrons between the semiconductor layer and the metal source / drain electrode is remarkably reduced, and further, the reduction of the Schottky barrier height due to the mirror image effect is enhanced. Therefore, the effective Schottky barrier height can be significantly reduced. Therefore, low resistance connection between the electron carrier layer and the metal source / drain electrodes is realized. Therefore, the parasitic resistance between the channel and the metal source / drain electrode can be remarkably suppressed by the ionization of cesium in the cesium-containing region and the strong electric field effect due to the fixed charge.

  In addition, since the metal source / drain electrode is separated from the gate electrode in the lateral direction (channel length direction), the influence of the electric field from the gate electrode is difficult to reach the metal source / drain electrode and the semiconductor layer in the vicinity thereof, and Since there is a strong electric field on the semiconductor surface under the fixed charge, even if a gate voltage in the off direction (negative bias direction in the case of N-type MOSFET, positive bias direction in the case of P-type MOSFET) is applied, Since the direction of the electric field on the surface of the semiconductor layer is not easily reversed, GIDL is reduced. Therefore, the leakage current can be significantly reduced.

In one embodiment,
The semiconductor layer is made of a semiconductor having an electron affinity greater than 3.89 eV.

  According to the embodiment, since the electron affinity of the semiconductor layer is larger than the ionization energy (3.89 eV) of cesium, the impurity level produced by cesium in the cesium-containing region is higher than the lower end of the conduction band of the semiconductor. It can be located on the energy side. In this case, the energy band of the semiconductor layer near the metal source / drain electrode is bent to the extent that the lower end of the conduction band of the semiconductor layer coincides with the Fermi level of the metal source / drain electrode. Can be obtained. At this time, since the band bending in the region where cesium is ionized becomes very steep, the thickness of the Schottky barrier against electrons becomes very thin between the metal source / drain electrodes and the semiconductor layer. Since the effect of reducing the Schottky barrier height due to the mirror image effect becomes significant, the Schottky barrier height for electrons is effectively very small. Therefore, the channel and the metal source / drain electrode can be connected to each other with extremely low resistance. At the same time, since the energy barrier height against holes becomes very large, the leakage current between the metal source / drain-semiconductor layer can be remarkably suppressed.

In one embodiment,
The semiconductor layer is made of any one of silicon, germanium, silicon germanium, gallium arsenide, and gallium nitride.

  According to the above embodiment, the electron affinity of silicon, germanium, silicon germanium, gallium arsenide, and gallium nitride is 4.05 eV, 4.0 eV, 4.0 eV, 4.07 eV, and 4.1 eV, respectively. The electron affinity of the semiconductor layer can be made larger than 3.89 eV.

  Further, since the cesium is not a silicon donor and acceptor, carriers are hardly generated in the bulk of the semiconductor layer. Therefore, even when the cesium-containing region is formed deeper than the metal source / drain electrode, the short channel effect characteristics are not deteriorated, and the source / drain is formed in a region shallower than the impurity implantation depth. It is possible to form a very shallow source / drain. Therefore, good short channel effect characteristics can be obtained.

  In addition, when ion implantation is used to form the cesium-containing region, the mass number of cesium (133) is very large and is larger than the mass number of normal donor impurities (for example, the arsenic room rainfall number is 75). The ions can be implanted into a region shallower than the arsenic at the same ion implantation energy. Conversely, when ion implantation is performed at the same depth, the ion implantation energy of the cesium can be made larger than the ion implantation energy of the arsenic, so that the amount of ion current can be increased and the process time can be shortened. Can do. In particular, according to the above impurities, it is possible to avoid the problem that a sufficient dose cannot be secured when ion implantation is performed with very small ion implantation energy.

In one embodiment,
It is cesium that constitutes at least a part of the fixed charges.

  According to the above embodiment, cesium has the smallest ionization potential (3.89 eV) among all elements, and therefore can form a high-density fixed charge most easily. When the semiconductor layer has a semiconductor with an electron affinity greater than 3.89 eV (eg, silicon, germanium, GaAs, GaN, etc., the electron affinity is 4.05 eV, 4.0 eV, 4.07 eV, 4.1 eV, respectively) Since the cesium forms an energy level (impurity level) on the higher energy side than the lower end of the conduction band of the semiconductor layer, it can form a higher-density fixed charge and has a high concentration on the surface of the semiconductor layer. The electron carrier layer can be induced.

  Note that, as a result of charge transfer between the impurity level and the semiconductor layer, band bending occurs to the extent that the impurity level and the Fermi level coincide with each other on the surface of the semiconductor layer, so the ionization potential of the impurity is small. The induced electron carrier concentration increases, and if the impurity level is on the higher energy side than the lower end of the conduction band of the semiconductor layer, the surface of the semiconductor layer can be strongly inverted, and an extremely high concentration of electron carriers A layer can be formed.

In one embodiment,
The insulating layer contains a nitrogen element.

  According to the embodiment, a fixed charge can be easily formed in the insulating layer. This is because, for example, in silicon nitride, the higher the refractive index, the higher the density of positive fixed charges, and the lower the refractive index, the higher the density of negative fixed charges. This is because it is formed.

In one embodiment,
The cesium concentration at the interface between the cesium-containing region and the metal source / drain electrode is 1 × 10 ¹⁹ cm ⁻³ or more.

  According to the embodiment, the cesium concentration at the interface with the metal source / drain electrode is sufficiently high. For this reason, the Schottky barrier can be greatly modulated, the leakage current between the semiconductor layer and the metal source / drain electrode can be remarkably suppressed, and the resistance between the channel and the metal source / drain electrode can be significantly reduced.

In one embodiment,
The concentration of the cesium in the cesium-containing region has a peak at a position deeper than the interface between the cesium-containing region and the metal source / drain electrode.

  According to the above embodiment, since a wide range of the metal source / drain electrode can be covered with a high concentration cesium-containing region, the leakage current between the semiconductor layer and the metal source / drain electrode is effectively reduced. be able to.

In one embodiment,
The metal source / drain electrodes are composed of a compound of a semiconductor constituting the semiconductor layer and a metal.

  The depth of the metal source / drain electrode can be controlled by the thickness of the metal deposited on the semiconductor layer. According to the embodiment, shallow metal source / drain electrodes can be easily formed by thinly depositing the metal on the semiconductor layer by sputtering or the like.

In one embodiment,
The semiconductor constituting the semiconductor layer includes at least one of silicon and germanium,
The metal includes one or more of nickel, cobalt, titanium, platinum, erbium and ytterbium.

  According to the embodiment, since the self-aligned silicide process or the self-aligned germanide process can be used, the shallow metal source / drain electrodes are easily formed in a self-aligned position with respect to the gate electrode. be able to.

In one embodiment,
The semiconductor layer is provided on an insulator,
At least a part of the metal source / drain electrode is in contact with the insulator.

  According to the embodiment, in a semiconductor device having an SOI (Semiconductor On Insulator) structure, the leakage current between the semiconductor layer and the metal source / drain electrode can be remarkably suppressed, and the resistance between the channel and the metal source / drain electrode can be reduced. Can be significantly reduced. Furthermore, it is possible to form a very shallow source / drain and to obtain good short channel effect characteristics.

In addition, a method for manufacturing a semiconductor device of the present invention includes:
In the manufacturing method of a semiconductor device for manufacturing the semiconductor device of the present invention,
Forming a gate electrode on the semiconductor layer via a gate insulating film;
Forming an insulating layer on both sides of the gate electrode on the semiconductor layer;
Introducing cesium into the insulating layer;
Forming a fixed charge by segregating the cesium at the interface between the insulating layer and the semiconductor layer by annealing;
Anisotropically etching the insulating layer such that a part of the surface of the semiconductor layer is exposed to form a gate sidewall made of the insulating layer;
Introducing the cesium into a region where the surface of the semiconductor layer is exposed to form the cesium-containing region;
Forming a metal source / drain electrode so as to be in contact with the cesium-containing region.

  According to the present invention, since the cesium-containing region is formed in part or all of the region in contact with the metal source / drain electrode in the semiconductor layer, the region between the semiconductor layer and the metal source / drain electrode is formed. A semiconductor device can be formed in which the leakage current can be remarkably suppressed and the resistance between the channel and the metal source / drain electrode can be significantly reduced.

  According to the present invention, since the cesium is segregated at the interface between the insulating layer and the semiconductor layer, a positive fixed charge can be formed in the vicinity of the interface between the insulating layer and the semiconductor layer. it can. Therefore, an electron carrier layer is induced on the surface of the semiconductor layer under a fixed charge, and functions as a very shallow source / drain extension. Therefore, very good short channel effect characteristics can be obtained. Also, due to the strong electric field effect due to the fixed charge, the thickness of the Schottky barrier against electrons between the semiconductor layer and the metal source / drain electrode is remarkably reduced, and further, the reduction of the Schottky barrier height due to the mirror effect is enhanced. Therefore, the effective Schottky barrier height is remarkably reduced, and a low resistance connection between the electron carrier layer and the metal source / drain electrodes can be realized. Therefore, good short channel effect characteristics and low parasitic resistance can be realized at the same time.

In addition, a method for manufacturing a semiconductor device of the present invention includes:
In the manufacturing method of a semiconductor device for manufacturing the semiconductor device of the present invention,
Forming a gate electrode on the semiconductor layer via a gate insulating film;
At least a region adjacent to the gate electrode in the surface of the semiconductor layer includes an atmosphere containing at least one of a plasma state of nitrogen, a nitrogen radical, and a gas containing an oxidant composed of a molecule containing a nitrogen element. Exposing to an insulating layer to form a positive fixed charge;
Anisotropically etching the insulating layer such that a part of the surface of the semiconductor layer is exposed to form a gate sidewall made of the insulating layer;
Introducing cesium into a region where the surface of the semiconductor layer is exposed to form a cesium-containing region;
Forming a metal source / drain electrode in contact with the cesium-containing region.

  According to the present invention, at least a region adjacent to the gate electrode in the surface of the cesium-containing region is a plasma state of nitrogen, a nitrogen radical, and a gas containing an oxidant composed of molecules containing a nitrogen element. By exposing at least one to the atmosphere, an insulating layer containing a positive fixed charge can be formed.

In addition, a method for manufacturing a semiconductor device of the present invention includes:
In the manufacturing method of a semiconductor device for manufacturing the semiconductor device of the present invention,
Forming a gate electrode on the semiconductor layer via a gate insulating film;
Introducing cesium on both sides of the gate electrode in the upper part of the semiconductor layer to form a cesium-containing region;
By reacting the upper part of the cesium-containing region with an element different from the elements constituting the cesium-containing region to form an insulating layer, the cesium is segregated at the interface between the semiconductor layer and the insulating layer to be positive. Forming a fixed charge of
Etching part of the insulating layer to form an opening of the insulating layer so that at least part of the surface of the cesium-containing region in the semiconductor layer is exposed;
Forming a metal source / drain electrode so as to be in contact with the cesium-containing region.

  According to the present invention, the insulating layer is formed on the cesium-containing region by reacting with an element different from the element constituting the cesium-containing region by oxidizing, oxynitriding, or nitriding the cesium-containing region. Simultaneously with the formation, a part of the cesium is segregated at the interface between the insulating layer and the cesium-containing region to form a positive fixed charge. Therefore, since it is not necessary to introduce the cesium into the insulating layer separately from the step of forming the cesium-containing region in order to form the fixed charge, the process can be simplified. Further, since the fixed charge and the cesium-containing region are formed using the same material, the manufacturing cost can be reduced.

In addition, a method for manufacturing a semiconductor device of the present invention includes:
In the manufacturing method of a semiconductor device for manufacturing the semiconductor device of the present invention,
Forming a gate electrode on the semiconductor layer via a gate insulating film;
Introducing cesium on both sides of the gate electrode on the semiconductor layer to form a cesium-containing region;
Forming an insulating layer so as to cover at least a region adjacent to the gate electrode in the surface of the cesium-containing region;
Forming a positive fixed charge by segregating the cesium at the interface between the insulating layer and the semiconductor layer by annealing;
Etching part of the insulating layer to form an opening of the insulating layer so that at least part of the surface of the cesium-containing region in the semiconductor layer is exposed;
Forming a metal source / drain electrode so as to be in contact with the cesium-containing region.

  According to the present invention, the insulating layer is formed on the cesium-containing region and then annealed, whereby a part of the cesium is segregated at the interface between the insulating layer and the cesium-containing region. A charge is formed. Therefore, since it is not necessary to introduce the cesium into the insulating layer separately from the step of forming the cesium-containing region in order to form the fixed charge, the process can be simplified. In addition, since the fixed charge and the cesium-containing region are formed using the same material, the manufacturing cost can be reduced.

In addition, a method for manufacturing a semiconductor device of the present invention includes:
In the manufacturing method of a semiconductor device for manufacturing the semiconductor device of the present invention,
Forming a gate electrode on the semiconductor layer via a gate insulating film;
Forming an insulating layer on both sides of the gate electrode of the surface of the semiconductor layer;
Introducing cesium on both sides of the gate electrode on the semiconductor layer and in the insulating layer to form a cesium-containing region and forming a fixed charge in the insulating layer;
Etching part of the insulating layer to form an opening of the insulating layer so that at least part of the surface of the cesium-containing region in the semiconductor layer is exposed;
Forming a metal source / drain electrode so as to be in contact with the cesium-containing region.

  According to the present invention, it is not necessary to introduce a step of forming the fixed charge in the insulating layer separately from the step of forming the cesium-containing region in order to form the fixed charge, thereby simplifying the process. can do. In addition, since the fixed charge and the cesium-containing region are formed using the same material, the manufacturing cost can be reduced.

In one embodiment,
The step of forming the metal source / drain electrode includes:
Depositing a metal on the cesium-containing region;
Performing annealing to react the semiconductor constituting the semiconductor layer with the metal;
And a step of removing an unreacted portion that has not reacted with the semiconductor constituting the semiconductor layer among the metals.

  According to the embodiment, since the metal source / drain electrodes are formed by reacting the semiconductor layer and the metal, the adhesion and adhesion at the interface between the metal source / drain electrodes and the semiconductor layer are improved. In addition, since the interface state density can be reduced, good rectification characteristics can be obtained. Further, the metal source / drain electrodes can be formed at positions that are self-aligned with the gate electrode.

In one embodiment,
The semiconductor constituting the semiconductor layer includes at least one of silicon and germanium,
The metal includes at least one of nickel, cobalt, titanium, platinum, erbium, and ytterbium.

  According to the above embodiment, since the self-aligned silicide process and the self-aligned germanide process can be applied, the shallow metal source / drain electrodes are easily formed in a self-aligned position with respect to the gate electrode. can do.

  According to the present invention, the semiconductor layer has a cesium-containing region containing cesium in part or all of the region in contact with the metal source / drain electrode, and further includes a gate insulating film and a metal source / drain electrode. Since the insulating layer provided on the sandwiched region has a positive fixed charge, leakage current between the semiconductor layer and the metal source / drain electrode can be remarkably suppressed, and the channel and the metal source / The resistance between the drain electrodes can be significantly reduced.

  In addition, since the cesium hardly generates carriers in the bulk of the semiconductor layer (for example, silicon), even when the cesium-containing region is formed deeper than the metal source / drain electrode, the short channel effect characteristic is obtained. Will not deteriorate. That is, a source / drain can be formed in a region shallower than the cesium implantation depth, and an extremely shallow source / drain can be formed. Therefore, good short channel effect characteristics can be obtained.

  Further, since the source / drain extension has an extremely shallow electron carrier layer induced by a fixed charge, extremely good short channel effect characteristics can be obtained. In addition, since the metal source / drain electrode is separated from the gate electrode in the lateral direction (channel length direction), the influence of the electric field from the gate electrode is difficult to reach the metal source / drain electrode and the semiconductor layer in the vicinity thereof, and Since there is a strong electric field on the semiconductor surface under the fixed charge, even if a gate voltage in the off direction (negative bias direction in the case of N-type MOSFET, positive bias direction in the case of P-type MOSFET) is applied, Since the direction of the electric field on the surface of the semiconductor layer is not easily reversed, GIDL is reduced. Therefore, the leakage current can be significantly reduced.

It is a schematic cross section showing the state in the middle of manufacture of the semiconductor device of a 1st embodiment. It is a schematic cross section showing the state in the middle of manufacture of the semiconductor device of a 1st embodiment. It is a schematic cross section showing the state in the middle of manufacture of the semiconductor device of a 1st embodiment. It is a schematic cross section showing the state in the middle of manufacture of the semiconductor device of a 1st embodiment. It is a schematic cross section showing the state in the middle of manufacture of the semiconductor device of a 1st embodiment. It is a schematic cross section showing the state in the middle of manufacture of the semiconductor device of a 1st embodiment. It is sectional drawing of the semiconductor device manufactured by the manufacturing method shown to FIG. 1A-FIG. 1F. It is the figure which compared the drain current-gate voltage characteristic of the semiconductor device of this Embodiment, and MOSFET (DS-FET) produced using the prior art (impurity segregation technique of patent document 1). 2C is a cross-sectional view of a diode manufactured by a method similar to that for the metal source / drain electrodes in FIG. The current-voltage characteristic measured between the nickel silicide in FIG. 4 and the back surface of P-type silicon is shown. It is an energy band figure in the CC 'cross section in FIG. In FIG. 4, it is an energy band figure in the cross section corresponding to CC 'cross section in FIG. 4 in the form in which a cesium containing area | region does not exist. It is a figure which shows the current-voltage characteristic of the diode using N type silicon. FIG. 5 is an energy band diagram in a CC ′ section of a diode using N-type silicon instead of P-type silicon in FIG. 4. FIG. 5 is an energy band diagram in a cross section corresponding to a CC ′ cross section in FIG. 4 in which N type silicon is used instead of P type silicon in FIG. 4 and no cesium-containing region exists. It is an energy band figure in the BB 'cross section in FIG. In FIG. 2, it is an energy band figure in the cross section corresponding to the BB 'cross section in the form which a cesium containing area | region and a cesium containing area | region do not exist. It is a schematic cross section showing the state in the middle of manufacture of the semiconductor device of a 2nd embodiment. It is a schematic cross section showing the state in the middle of manufacture of the semiconductor device of a 2nd embodiment. It is a schematic cross section showing the state in the middle of manufacture of the semiconductor device of a 2nd embodiment. It is a schematic cross section showing the state in the middle of manufacture of the semiconductor device of a 2nd embodiment. It is a schematic cross section showing the state in the middle of manufacture of the semiconductor device of a 2nd embodiment. It is a schematic cross section showing the state in the middle of manufacture of the semiconductor device of a 3rd embodiment. It is a schematic cross section showing the state in the middle of manufacture of the semiconductor device of a 3rd embodiment. It is a schematic cross section showing the state in the middle of manufacture of the semiconductor device of a 3rd embodiment. It is a schematic cross section showing the state in the middle of manufacture of the semiconductor device of a 3rd embodiment. It is a schematic cross section showing the state in the middle of manufacture of the semiconductor device of a 3rd embodiment. It is a schematic cross section showing the state in the middle of manufacture of the semiconductor device of a 4th embodiment. It is a schematic cross section showing the state in the middle of manufacture of the semiconductor device of a 4th embodiment. It is a schematic cross section showing the state in the middle of manufacture of the semiconductor device of a 4th embodiment. It is a schematic cross section showing the state in the middle of manufacture of the semiconductor device of a 4th embodiment. It is a schematic cross section showing the state in the middle of manufacture of the semiconductor device of a 4th embodiment. It is a schematic cross section showing the state in the middle of manufacture of the semiconductor device of a 5th embodiment. It is a schematic cross section showing the state in the middle of manufacture of the semiconductor device of a 5th embodiment. It is a schematic cross section showing the state in the middle of manufacture of the semiconductor device of a 5th embodiment. It is a schematic cross section showing the state in the middle of manufacture of the semiconductor device of a 5th embodiment. It is a schematic cross section showing the state in the middle of manufacture of the semiconductor device of a 5th embodiment. It is a schematic cross section showing the state in the middle of manufacture of the semiconductor device of a 5th embodiment. It is a schematic cross section showing the state in the middle of manufacture of the semiconductor device of a 6th embodiment. It is a schematic cross section showing the state in the middle of manufacture of the semiconductor device of a 6th embodiment. It is a schematic cross section showing the state in the middle of manufacture of the semiconductor device of a 6th embodiment. It is a schematic cross section showing the state in the middle of manufacture of the semiconductor device of a 6th embodiment. It is a schematic cross section showing the state in the middle of manufacture of the semiconductor device of a 6th embodiment. It is DD 'arrow sectional drawing of FIG. 17E. It is EE 'arrow sectional drawing of FIG. 17E. It is a figure corresponding to DD 'arrow sectional drawing of FIG. 17E in the semiconductor device of the modification of 6th Embodiment. It is a figure corresponding to the EE 'arrow sectional view of Drawing 17E in the semiconductor device of the modification of a 6th embodiment.

  Hereinafter, the present invention will be described in detail with reference to the drawings.

  The semiconductor layer that can be used in the present invention is not particularly limited. For example, a silicon layer, a germanium layer, a SiGe layer, a GaAs layer, a GaN layer, a carbon nanotube layer, or the like can be used as the semiconductor layer. . Further, as the substrate, an SOI (Semiconductor On Insulator) substrate or a strained semiconductor substrate in which carrier mobility is improved by applying strain to the crystal can be suitably used. In addition, a substrate formed by forming a polycrystalline semiconductor on a glass substrate or the like can be used, and a substrate formed by forming an amorphous semiconductor on a glass substrate or the like can also be used.

(First embodiment)
1A to 1F are cross-sectional views in each manufacturing process of the semiconductor device of the first embodiment. FIG. 2 is a cross-sectional view of the semiconductor device manufactured by the manufacturing method shown in FIG. Hereinafter, the method for manufacturing the semiconductor device of the present embodiment will be described with reference to FIGS. 1A to 1F and FIG.

  First, an element isolation region (not shown) is formed on one main surface of a P-type silicon substrate 1 as an example of a semiconductor layer by a known method such as an STI (Shallow Trench Isolation) method. The element formation region is divided by the element isolation region.

  Next, as shown in FIG. 1A, by using a thermal oxidation method, a CVD (Chemical Vapor Deposition) method, an ALD (Atomic Layer Deposition) method, or the like, the element formation region is formed. A gate insulating film 2 made of silicon oxide is formed on the surface, and then an N-type polycrystalline silicon film is deposited on the gate insulating film 2 using a CVD method or the like. Next, the gate electrode 3 is formed by patterning the polycrystalline silicon film using a lithography method, a reactive ion etching (RIE) method, or the like. Next, a silicon oxide film 4 is formed using a CVD method or the like. The film thickness of the silicon oxide film 4 is 15 nm, for example.

  As the material of the gate insulating film 2, silicon oxynitride, silicon nitride, hafnium oxide, lanthanum oxide, or a material containing these materials containing nitrogen, silicon, aluminum, or the like may be used instead of silicon oxide. Good.

  Since the material of the gate insulating film 2 is preferably one in which cesium is less likely to diffuse than the silicon oxide film 4, it preferably contains nitrogen. In this case, it is possible to prevent cesium introduced into the silicon oxide film 4 from being thermally diffused into the gate insulating film 2 in a later step.

  Further, although polycrystalline silicon is used as the material of the gate electrode 3, amorphous silicon, germanium, silicon containing germanium, or the like may be used.

Next, as shown in FIG. 1B, cesium-containing regions 5 are formed by introducing cesium into the silicon oxide film 4 using, for example, an ion implantation method. The ion implantation conditions can be, for example, acceleration energy: 5 keV, dose amount: 4 × 10 ¹⁴ cm ⁻² . The ion implantation conditions may be selected so that the peak position of the cesium concentration distribution after ion implantation is located near the center of the silicon oxide film 4.

  Next, as shown in FIG. 1C, a silicon nitride film 6 is formed using, for example, a CVD method. Subsequently, annealing is performed by, for example, RTA (Rapid Thermal Annealing) method. The annealing conditions may be, for example, 750 to 950 ° C. and 1 to 10 seconds. As a result, cesium is segregated at the interface between the silicon oxide film 4 and the P-type silicon substrate 1 and becomes a positive fixed charge. In addition, since cesium hardly diffuses in silicon nitride, it is possible to suppress cesium from diffusing outwardly by annealing.

  Note that, instead of the RTA method, a flash lamp annealing method, a laser annealing method, or the like may be used to perform annealing at a higher temperature for a shorter time.

  Next, as shown in FIG. 1D, gate sidewalls are formed by anisotropically etching the silicon nitride film 6 and the silicon oxide film 4 by RIE or the like. In the present embodiment, since positive fixed charges are contained in the gate sidewall (in the silicon oxide film 4), an electron carrier layer is induced on the silicon surface as a semiconductor under the gate sidewall. Since this electron carrier layer functions as a very shallow source / drain extension, extremely good short channel effect characteristics can be obtained.

The fixed charge density σ _FC (cm ⁻² ) in the gate side wall (in the silicon oxide film 4) is the P-type impurity concentration N _A (cm ⁻³ ) in the silicon near the end of the gate electrode 3. The above-mentioned electron carrier layer can be formed by satisfying the following conditions.
However,

Where κ: relative dielectric constant of silicon (semiconductor), ε: dielectric constant of vacuum (F / cm), q: elementary charge (C), _Ni : intrinsic carrier density of silicon (semiconductor) (cm ⁻³⁾ ), K _B : Boltzmann constant (eV / K), T: absolute temperature (K). For example, when N _A = 1 × 10 ¹⁸ cm ⁻³ ,
σ _FC ≧ 3.5 × 10 ¹² cm ^-2
Thus, the electron carrier layer can be formed.

More preferably, σ _FC = 1 × 10 ¹³ cm ^{−2 to} 3 × 10 ¹³ cm ⁻² . At this time, the resistance of the electron carrier layer is the lowest, and the resistance of the source / drain can be reduced most effectively. As σ _FC increases, the electron carrier density increases, but the mobility decreases. ^Therefore , the resistance of the electron carrier layer is lowest at σ _FC = 1 × 10 ¹³ cm ^{−2 to} 3 × 10 ¹³ cm ^−2. Become.

Next, as shown in FIG. 1E, cesium as an impurity that modulates the Schottky barrier between the semiconductor layer and the metal source / drain electrodes is subjected to, for example, acceleration energy of 5 keV and a dose of 1 × 10 ¹⁴ cm ⁻² . A cesium-containing region 7 is formed by ion implantation. The ion implantation conditions are not limited to the above conditions, but the cesium-containing region 7 may be formed to a position deeper than nickel silicide 8 (see FIG. 1F) formed in a later step. .

  Cesium (mass number 133) has a larger mass number than P (mass number 31), As (mass number 75), etc., which are normal donor impurities. Can be ion-implanted. In ion implantation, the smaller the ion implantation energy and the smaller the number of implanted species, the smaller the amount of current during ion implantation. There is a problem that it becomes long. Cesium has a larger mass number than normal donor impurities such as P and As, so it can take a larger amount of current. Therefore, the ion implantation time can be greatly shortened or ion implantation can be performed at a lower energy. It becomes possible. As a result, since the metal source / drain electrodes can be formed at extremely shallow positions, the short channel effect characteristics can be improved. In addition, a manufacturing facility can be simplified by forming the fixed charge in the cesium containing area | region 5 and a gate side wall using the same material.

  Thereafter, annealing may be performed to recover the implantation damage. In that case, for example, RTA method, FLA (Flash Lamp Annealing) method, laser annealing method or the like is used.

  Next, as shown in FIG. 1F, nickel is deposited by, for example, about 2 nm by sputtering or the like, and then TiN (titanium nitride) is deposited by, for example, about 10 nm. Annealing is performed to form a silicide. Thereafter, unreacted nickel and TiN are removed to form the nickel silicide 8 as an example of a metal source / drain electrode. Thereafter, the resistance of the nickel silicide 8 is lowered by annealing under conditions of 350 ° C. to 500 ° C. and 30 seconds to 200 seconds. In that case, the metal source / drain electrode (nickel silicide 8: hereinafter may be referred to as the metal source / drain electrode 8) is in contact with the semiconductor layer (P-type silicon substrate 1) via the cesium-containing region 7. The nickel silicide 8 is formed so that at least its thickness (depth) is thinner (shallow) than the cesium-containing region 7. The thickness of the nickel silicide 8 is about 3 times the thickness of the sputtered nickel film (for example, about 6 nm).

  As a result of the above process, the metal source / drain electrode (nickel silicide 8) may contain a part of cesium as an impurity that modulates the Schottky barrier between the semiconductor layer and the metal source / drain electrode. . In this case, since the work function of cesium (1.93 eV) is smaller than that of nickel silicide (NiSi) (4.9 eV), the work function of the metal source / drain electrodes is reduced, and the Schottky barrier height against electrons is increased. Can be further reduced.

  The nickel silicide 8 functions as a source / drain. When the nickel silicide 8 is formed, the upper portion of the gate electrode 3 is also silicided to form nickel silicide. Thus, a semiconductor device as shown in FIG. 2 is formed. In FIG. 2, the cesium-containing region 5 constitutes an insulating layer.

  In this case, the gate electrode 3 may be entirely silicided to have a metal gate structure. In the case of a metal gate structure, the polycrystalline silicon film may be either i-type or P-type.

  As an example of the metal source / drain electrodes, when cobalt silicide is formed instead of nickel silicide 8, cobalt is deposited by, for example, about 3 nm by sputtering or the like, and then TiN is deposited by, for example, about 10 nm. The material deposited is annealed under conditions of 400 ° C. to 600 ° C. and 30 seconds to 200 seconds, thereby siliciding. Then, after removing unreacted cobalt, the resistance of cobalt silicide may be reduced by annealing under conditions of 700 ° C. to 900 ° C. and 30 seconds to 200 seconds.

  Also in this case, at least the thickness of the cobalt silicide is larger than that of the cesium-containing region 7 so that the metal source / drain electrode (cobalt silicide) is in contact with the semiconductor layer (P-type silicon substrate 1) via the cesium-containing region 7. It is formed to be thin. The thickness of the cobalt silicide is about twice the thickness of the sputtered cobalt (for example, about 6 nm).

  As described above, the case of nickel silicide 8 and cobalt silicide has been described as an example of the metal source / drain electrode. However, the metal source / drain electrode is not limited thereto. For example, a metal silicide using a metal composed of one or more elements of Ni, Co, Ti, Er, and Yb may be used.

  Finally, an interlayer insulating film (not shown), an upper wiring (not shown), and the like are formed by a known method, thereby completing the semiconductor device.

  According to the semiconductor device of the present embodiment, since positive fixed charges are included in the gate sidewall (silicon oxide film 4), the surface of the semiconductor layer (P-type silicon substrate 1) under the gate sidewall is extremely shallow. A layer is induced. Since this electron carrier layer functions as a very shallow source / drain extension, a very good short channel effect can be obtained. In addition, since the strong electric field generated between the fixed charge and the semiconductor layer (P-type silicon substrate 1) effectively reduces the Schottky barrier height against electrons between the metal source / drain electrode 8 and the semiconductor layer, the metal The resistance between the source / drain electrode 8 and the electron carrier layer can be significantly reduced. Further, since the cesium-containing region 7 is formed between the metal source / drain electrode 8 (nickel silicide 8) and the semiconductor layer (P-type silicon substrate 1), cesium near the metal source / drain electrode 7 is ionized. This increases the height of the energy barrier against holes. As a result, the leakage current between the source / drain and the semiconductor layer can be significantly reduced as compared with a simple Schottky junction (without the cesium-containing region 7). At the same time, since the Schottky barrier height for electrons between the channel and the source / drain is effectively reduced, the parasitic resistance can be significantly reduced as compared with the Schottky junction.

  Further, the metal source / drain electrode 8 is formed at a position laterally separated from the gate electrode 3, and the fixed charge is formed, whereby the electron carrier layer which is a part of the source / drain is formed The electric field strength between the gate electrode 3 is weakened and GIDL is significantly reduced. Therefore, the leakage current can be significantly reduced.

In that case, if the concentration of cesium at the interface with the metal source / drain electrode 8 in the cesium-containing region 7 is set to 1 × 10 ¹⁹ cm ⁻³ or more, the concentration of cesium at the interface with the metal source / drain electrode 8 is increased. Can be big enough. Therefore, the Schottky barrier is modulated more greatly to reduce the leakage current between the source / drain and the semiconductor layer and to reduce the parasitic resistance between the channel and the source / drain more effectively. Can do.

  Further, if the cesium concentration in the cesium-containing region 7 is set to have a peak at a position deeper than the interface with the metal source / drain electrode 8 in the cesium-containing region 7, a wide range of the metal source / drain electrode 8 can be obtained. Can be covered with a high concentration cesium region. Therefore, the leakage current between the source / drain and the semiconductor layer can be further effectively reduced.

  In addition, since cesium is not a silicon donor and acceptor, cesium is not ionized in a region sufficiently distant from the metal source / drain electrode 8 in the cesium-containing region 7. Therefore, it is not necessary to extremely reduce the thickness of the cesium-containing region 7 between the metal source / drain electrode 8 and the semiconductor layer (P-type silicon substrate 1) (that is, there is no restriction in ion implantation of cesium). ), It is not necessary to use an impurity segregation technique as disclosed in Patent Document 1 above.

  As described above, in the semiconductor device of the present embodiment, since the thickness (depth) of the metal silicide can be determined without restriction by ion implantation, it is possible to form extremely shallow metal sources / drains. The channel effect can be suppressed very well.

  FIG. 3 is a diagram comparing drain current-gate voltage characteristics between the semiconductor device of the present embodiment and a MOSFET (DS-FET) manufactured using the conventional technique (impurity segregation technique described in Patent Document 1). is there. Hereinafter, a GIDL comparison (with drain voltage Vd = 1V, gate length Lg = 240 nm) with / without fixed charge will be described with reference to FIG.

  In order to confirm the GIDL reduction effect in the semiconductor device of the present embodiment, a MOSFET (DS-FET) manufactured using the semiconductor device of the present embodiment and a conventional technique (impurity segregation technique described in Patent Document 1) The drain current-gate voltage characteristics are compared. Here, in order to pay attention to GIDL, the gate length is set to 240 nm so that the short channel effect can be ignored. The measurement was performed under the condition of a drain voltage of 1V.

The DS-FET was manufactured by a method similar to that of the semiconductor device of this embodiment except for a method of forming a source / drain. That is, after patterning the gate electrode, silicon oxide was formed by a thermal oxidation method, and anisotropic etching was performed to form a gate sidewall having a thickness of 2 nm. Next, As was ion-implanted into a P-type silicon substrate under conditions of an acceleration energy of 5 keV and a dose of 1 × 10 ¹⁵ cm ⁻² , annealing was performed at 800 ° C. for 10 seconds by the RTA method. Next, after depositing 5 nm of nickel by sputtering and subsequently depositing 10 nm of TiN, nickel silicide was formed by the same method as in FIG. 1F. Since nickel silicide is formed to a position deeper than the implantation peak depth of As, As is segregated at the interface between the nickel silicide and the P-type silicon substrate.

  As shown in FIG. 3, it was confirmed that the GIDL current was significantly reduced in the semiconductor device of the present embodiment as compared with the DS-FET. This is considered to be due to the following reason. That is, in the DS-FET, when a negative bias is applied to the gate electrode, a storage layer is formed on the surface of the semiconductor layer near the channel region and the metal source / drain electrode (nickel silicide), and the storage layer-metal source / drain electrode A large leak current (GIDL) occurs due to a tunnel current flowing between them. This is because the impurity segregation region is very narrow, so that a (hole) accumulation layer is easily formed, and even if the polarity of the impurity segregation region itself is not reversed, the width of the impurity segregation region is very narrow, It is thought that the tunnel current flows through the.

  On the other hand, in the semiconductor device of this embodiment, since the metal source / drain electrodes are separated from the gate electrode in the lateral direction (channel length direction), even if a negative bias is applied to the gate electrode, the electric field from the gate electrode is reduced. The influence of the influence on the metal source / drain electrode 8 and the semiconductor layer in the vicinity thereof is difficult, and there is a strong electric field on the surface of the semiconductor under a fixed charge. Therefore, even if a negative bias is applied to the gate electrode, the semiconductor under the fixed charge This is probably because GIDL is unlikely to occur due to the fact that the direction of the electric field on the layer surface is difficult to reverse (the accumulation layer is difficult to form).

  The present inventor conducted the following experiment in order to confirm the effect of the semiconductor device of the present embodiment having the cesium-containing region 7.

FIG. 4 is a cross-sectional view of a diode manufactured by the same method as that for the metal source / drain electrode 8 in FIG. 1F. That is, this diode is obtained by forming a cesium-containing region 12 on the surface of P-type silicon 11 and then forming nickel silicide 13. Nickel silicide 13 is in contact with P-type silicon 11 through cesium-containing region 12. As a result of analysis by SIMS (secondary ion mass spectrometry), the cesium concentration in the cesium-containing region 12 was 1 × 10 ¹⁹ cm ⁻³ at the interface with the nickel silicide 13. Further, the distribution of cesium had a peak at 11 in the P-type silicon outside the nickel silicide 13.

  FIG. 5 shows current-voltage characteristics (IV characteristics: P-type Si) measured between the nickel silicide 13 in FIG. 4 and the back surface of the P-type silicon 11 (solid line). For comparison, FIG. 5 also shows the current-voltage characteristics of a diode that does not have the cesium-containing region 12 (broken line). The bias voltage on the horizontal axis is a voltage applied to the nickel silicide 13 with respect to the P-type silicon 11.

  As can be seen from FIG. 5, the reverse bias current is significantly smaller when the cesium-containing region 12 is provided (solid line) than when the cesium-containing region is not provided (broken line). This indicates that in the source / drain structure shown in FIG. 2, the leakage current between the metal source / drain electrode 8 and the P-type silicon substrate 1 can be remarkably reduced.

  Hereinafter, the reason for this will be described with reference to FIGS.

  FIG. 6 is an energy band diagram in a CC ′ section in FIG. 4. FIG. 7 is an energy band diagram in a cross section corresponding to the CC ′ cross section in FIG. 4 in a form in which the cesium-containing region 12 does not exist in FIG. Specifically, FIG. 6 corresponds to the energy band diagram in the vicinity of the interface between the P-type silicon and nickel silicide in FIG. 2 (between AA ′ in FIG. 2) (when there is a cesium-containing region 7). FIG. 2 corresponds to an energy band diagram (corresponding to AA ′ in FIG. 2) in the vicinity of the interface between P-type silicon and nickel silicide when there is no cesium-containing region 7.

6 and 7, “E _C ^Si ” is the lower conduction band of silicon, “E _F ^Si ” is the Fermi level of silicon, and “E _V ^Si ” is the upper end of the valence band of silicon. “E _F ^M ” indicates the Fermi level of the nickel silicide 13, and “φ _b ^h ” indicates the barrier height against holes.

Since the diode shown in FIG. 7 is a Schottky barrier diode, the reverse bias current I _rp is expressed by the following formula (1).
Where φ _b ^h is the Schottky barrier height for holes, k _B is the Boltzmann constant, and T is the absolute temperature. Incidentally, phi _b ^h is the energy difference between the nickel silicide 13, and the Fermi level _E ^{F M} of the nickel silicide 13 at the interface between the P-type silicon 11, and the valence band maximum _E ^{V Si} of P-type silicon 11 .

Referring to FIG. 6, the ionization potential of cesium is 3.89 eV, whereas the electron affinity of silicon is 4.05 eV. Therefore, cesium is on the higher energy side than the lower conduction band E _C ^Si of silicon. It is thought to form an energy level. In this case, electrons are emitted from the energy level produced by cesium to the nickel silicide 13 side, and cesium is positively ionized. In the region where cesium is ionized, the energy band of silicon is greatly pushed down according to the density of cesium. That is, when the density of the cesium is sufficiently large, to the lowest point of the bottom of the conduction band E _C ^Si of the silicon is substantially coincident with the Fermi level E _F ^M of the nickel silicide 13, the energy band of the silicon is bent.

  On the other hand, since cesium does not activate as a donor for silicon, cesium at a position sufficiently far from nickel silicide 13 in cesium-containing region 12 remains neutral. In addition, since the emission of electrons from cesium at a position away from the interface with the P-type silicon 11 in the cesium-containing region 12 to the nickel silicide 13 mainly occurs due to the tunnel effect, the cesium ionizes the nickel silicide 13. And from the interface between the cesium-containing region 12 and the range of about 3 nm.

In order to measure the activation rate of cesium as a donor in silicon, hole measurement was performed. The sample was prepared as follows. Cesium was ion-implanted with an ion implantation energy of 100 keV on a 12-mm square sample in which SiO ₂ was formed to 10 nm on silicon. In that case, most of the cesium is distributed in the silicon. Next, P ions were implanted using a resist having openings at the four corners of the sample as a mask. Subsequently, after removing the resist, annealing was performed at 900 ° C. for 10 seconds to form an n ⁺ region, and damage caused by cesium ion implantation was recovered. Next, SiO ₂ on the four n ⁺ regions was opened using the lithography method and the RIE method, and subsequently, a Ti electrode was formed on each n ⁺ region using the lift-off method. Using this sample, hole measurement was performed by the Van der Pauw method. As a result, an electron surface density of 3.0 × 10 ¹² cm ⁻² was obtained. As a result of SIMS analysis, the amount of cesium contained in silicon was 1.7 × 10 ¹⁵ cm ⁻² . Therefore, the activation rate of cesium in silicon was a sufficiently low 0.18%. However, since cesium injected into SiO ₂ becomes a positive fixed charge and induces electron carriers in silicon, the activation rate of cesium in actual silicon as a donor is lower than 0.18%. It is thought that. Thus, it has been found that cesium hardly generates carriers in the bulk of silicon as a semiconductor.

As a result, the energy barrier height against holes in the diode shown in FIG. 6 is represented by φ _b ^h (Cs) in FIG. 6, and the reverse bias current I _rp (Cs) is represented by the following formula (2). The

As can be seen from FIG. 6, since φ _b ^h (Cs)> φ _b ^h , I _rp (Cs) << I _rp . In the case of many metal silicides, φ _b ^h is about 0.4 eV to 0.5 eV, whereas φ _b ^h (Cs) can be increased up to about 1.1 eV of silicon band gap. The reverse bias current is significantly reduced.

  Thus, the reverse bias current can be remarkably reduced by having the cesium-containing region in the semiconductor layer at the interface between the metal and the semiconductor layer. In the structure of the semiconductor device shown in FIG. 2, it can be seen that the leakage current between the metal source / drain electrode 8 and the P-type silicon substrate 1 can be remarkably reduced by having the cesium-containing region 7.

  2 is the same as the energy band diagram of FIG. 6 in the semiconductor device shown in FIG.

  Next, a description will be given of a diode formed by using N-type silicon instead of P-type silicon 11 with the same structure as the diode shown in FIG.

  The solid line in FIG. 8 shows the current-voltage characteristics (IV characteristics) of a diode using N-type silicon. Moreover, the broken line of FIG. 8 has shown the current-voltage characteristic when there is no cesium containing area | region. As can be seen from FIG. 8, when the cesium-containing region is included, the reverse bias current is remarkably increased as compared with the case where the cesium-containing region is not included. This indicates that the resistance between nickel silicide and N-type silicon is reduced by forming the cesium-containing region. This indicates that the resistance between the metal source / drain electrode 8 and the electron carrier layer induced by the fixed charge can be reduced in the source / drain structure shown in FIG.

  Hereinafter, this reason will be described with reference to FIGS.

  FIG. 9 is an energy band diagram in a cross section corresponding to a CC ′ cross section of a diode using N-type silicon instead of P-type silicon 11 in FIG. FIG. 10 shows an energy band in a cross section corresponding to the CC ′ cross section in FIG. 4 in which N type silicon is used instead of P type silicon 11 in FIG. 4 and the cesium containing region 12 does not exist. FIG.

Since the diode shown in FIG. 10 is a Schottky barrier diode, the reverse bias current I _rn is expressed by the following formula (3).
Here, phi _b ^e is a Schottky barrier height for electrons, k _B is the Boltzmann constant, T is the absolute temperature. Incidentally, phi _b ^e is the energy difference between the nickel silicide 13, and the bottom of the conduction band in N-type silicon at the interface between the N-type silicon, the Fermi level of nickel silicide 13.

Referring to FIG. 9, since the ionization potential of cesium is 3.89 eV, whereas the electron affinity of silicon is 4.05 eV, cesium has an energy level higher than the lower end of the conduction band of silicon. It is thought to form a position. In this case, electrons are emitted from the energy level produced by cesium to the nickel silicide side, and cesium is positively ionized. In the region where cesium is ionized, the energy band of silicon is greatly pushed down according to the density of cesium. That is, when the density of the cesium is sufficiently large, to the lowest point of the bottom of the conduction band E _C ^Si of the silicon is substantially coincident with the Fermi level E _F ^M of the nickel silicide 13, the energy band of the silicon is bent.

  On the other hand, since cesium does not activate as a donor for silicon, cesium at a position sufficiently far from nickel silicide 13 in cesium-containing region 12 remains neutral. In addition, since emission of electrons from cesium at a position away from the interface with the N-type silicon in the cesium-containing region 12 to the nickel silicide 13 is mainly caused by a tunnel effect, the cesium is ionized by the nickel silicide 13 It is limited to a range of about 3 nm from the interface with the cesium-containing region 12.

As a result, the width of the Schottky barrier becomes very thin, and further, due to the reduction of the Schottky barrier height due to the mirror image effect, electrical conduction between the nickel silicide 13-P type silicon 11 is mainly caused by the tunnel current. . Accordingly, as shown in FIG. 9, the energy barrier height for electrons φ _b ^e (Cs) becomes a conduction band minimum E _C ^Si of the silicon, the energy difference between the Fermi level E _F ^M of the nickel silicide 13. In this case, the reverse bias current I _rn (Cs) is expressed by the following formula (4).

As can be seen from FIG. 9, since it is ^{_{φ b e (Cs) << φ}} b e, the _{I rn (Cs) >> I rn} . The φ _b ^e (Cs) is to become a conduction band minimum E _C ^Si of the silicon, a very small value of about energy difference between the Fermi level E _F ^Si of the silicon, as shown in FIG. 8, substantially ohmic properties The current-voltage characteristics can be obtained. In the structure of the semiconductor device shown in FIG. 2, since the electron carrier layer (fixed charge induced electron carrier layer) induced by the fixed charge can be regarded as a high electron density N-type region, by having the cesium containing region 7, It can be seen that the fixed charge-induced carrier layer-source / drain can be connected with low resistance, and therefore, the channel-source-drain can be connected with low resistance.

  Hereinafter, the channel-source / drain resistance in the semiconductor device shown in FIG. 2 will be considered with reference to FIGS.

  FIG. 11 is an energy band diagram in the BB ′ cross section in FIG. 2. FIG. 12 is an energy band diagram in a cross section corresponding to the BB ′ cross section in the form in which the cesium-containing region 5 and the cesium-containing region 7 do not exist (Schottky junction transistor) in FIG.

  As shown in FIG. 12, by applying a voltage to the gate electrode 3, the energy band of silicon is bent, and an inversion layer is formed in the channel region. As a result, the thickness of the Schottky barrier is reduced, and the height of the Schottky barrier for electrons is reduced due to the mirror image effect, so that a tunnel current can flow.

  In contrast, in FIG. 11 where the cesium-containing region 7 exists, the energy band of silicon is bent by applying a voltage to the gate electrode 3, and an inversion layer is formed in the channel region. In addition, since a fixed charge is included in the gate side wall, the energy band on the surface of the semiconductor layer is bent downward by a strong electric field generated from the fixed charge, and an electron carrier is interposed between the channel region and the nickel silicide 8. A layer (fixed charge induced electron carrier layer) is formed. At least on the source electrode side, cesium in the cesium-containing region 7 is positively ionized by releasing electrons to the nickel silicide 8. As a result, as can be seen from comparison with FIG. 12, in the region where cesium is ionized, the energy band of silicon is further bent, and the inclination becomes very steep. As a result, the thickness of the Schottky barrier becomes very thin. In addition, the height of the Schottky barrier with respect to electrons is greatly reduced by the mirror image effect, so that the tunneling current of the source-electron carrier layer becomes significantly large. Further, the energy band at the surface of the semiconductor layer near the nickel silicide 8 is bent by a strong electric field from the fixed charge in the gate side wall, so that the slope of the energy band near the interface between the nickel silicide 8 and the semiconductor layer becomes steeper. In addition, the effect of reducing the height of the Schottky barrier for electrons is further increased.

  As described above, in the semiconductor device shown in FIG. 2, by having the cesium-containing region 7 (and the cesium-containing region 5), the resistance between the channel, the source and the drain can be remarkably reduced, and a large on-current can be obtained. be able to.

  As described above, according to the semiconductor device of the present embodiment, an impurity that modulates the Schottky barrier is provided between the metal source / drain electrode (nickel silicide) 8 and the semiconductor layer (P-type silicon substrate 1). A cesium-containing region 7 containing cesium is formed. Accordingly, ionization of cesium in the vicinity of the metal source / drain electrode 8 increases the height of the energy barrier against holes, and the metal source / drain electrode 8 and the P-type silicon substrate 1 as compared with the Schottky junction. Leakage current between the two can be significantly reduced. At the same time, the height of the Schottky barrier against electrons between the semiconductor layer and the metal source / drain electrode 8 is effectively reduced. Further, due to the strong electric field from the fixed charge, the vicinity of the metal source / drain electrode 8 is increased. Since the energy band is bent at the surface of the semiconductor layer, the Schottky barrier against the electrons is further reduced. As a result, the parasitic resistance can be remarkably reduced as compared with a normal Schottky junction.

  The metal source / drain electrode (nickel silicide 8) may contain a part of cesium. In this case, since the work function (1.93 eV) of cesium is larger than the work function (4.9 eV) of nickel silicide (NiSi), the work function of the metal source / drain electrode is reduced, and the Schottky barrier against electrons is increased. The thickness can be further reduced.

  In addition, since cesium is not a silicon donor and acceptor and hardly generates carriers in the bulk of silicon, in the cesium-containing region 7, in a region sufficiently away from the metal source / drain electrode 8, cesium serves as a carrier. It does not ionize by emitting electrons. Therefore, it is not necessary to reduce the thickness of the cesium-containing region 7 extremely in consideration of the fact that the region functioning as the source / drain is expanded by cesium diffusion or the like. That is, there are no special restrictions on the conditions for ion implantation of cesium. Therefore, in order to reduce the thickness of the cesium-containing region 7, it is not necessary to use an impurity segregation technique as disclosed in Patent Document 1.

  Further, since the cesium-containing region 7 does not induce carriers, even if the cesium-containing region 7 is formed deeper than the metal source / drain electrode 8, the short channel effect characteristic is not deteriorated. That is, since the metal source / drain electrode 8 can be formed in a region shallower than the ion implantation depth of impurities (cesium), an extremely shallow source / drain can be formed. Therefore, good short channel effect characteristics can be obtained.

  The cesium has an ionization potential (3.89 eV) smaller than the electron affinity (4.05 eV) of silicon. Therefore, cesium forms an impurity level on the higher energy side than the lower end of the conduction band of silicon, and discharges electrons from this impurity level to the metal source / drain electrode 8 side, thereby positively ionizing and cesium. Bend the energy band. Thus, the energy band of silicon is bent to such an extent that the impurity level matches the Fermi level of the metal source / drain electrode. Therefore, the Schottky barrier can be greatly modulated, and as described above, the leakage current between the P-type silicon substrate 1 and the metal source / drain electrode 8 can be remarkably suppressed, and between the channel and the metal source / drain electrode 8. The resistance can be significantly reduced.

Further, since the cesium concentration in the cesium-containing region 12 at the position in contact with the nickel silicide 13 in FIG. 4 is 1 × 10 ¹⁹ cm ⁻³ , the interface between the metal source / drain electrode 8 and the P-type silicon substrate 1 is used. By setting the concentration of cesium to 1 × 10 ¹⁹ cm ⁻³ or more, the Schottky barrier can be modulated sufficiently large. Therefore, the leakage current between the P-type silicon substrate 1 and the metal source / drain electrode 8 can be remarkably suppressed, and the resistance between the channel-metal source / drain electrode 8 can be significantly reduced.

  The cesium is distributed so as to have a concentration peak at a position deeper than the interface between the metal source / drain electrode 8 and the P-type silicon substrate 1. Therefore, a wide range of the metal source / drain electrodes 8 can be covered with the high concentration cesium-containing region, and the leakage current can be effectively reduced.

  The metal source / drain electrode 8 is composed of nickel silicide which is a compound of silicon as the semiconductor and nickel as the metal. Therefore, the shallow metal source / drain electrodes 8 can be easily formed by reducing the thickness of the deposited nickel.

  The semiconductor layer includes at least one of silicon and germanium as a main component, and the metal includes one or more elements of Ni, Co, Ti, Er, Yb, and Pt. In this case, since the self-aligned silicide process or the self-aligned germanide process can be used, the shallow metal source / drain electrodes 8 can be easily formed at a position self-aligned with respect to the gate electrode 3. it can.

  As described above, according to the present embodiment, the height and width of the Schottky barrier can be easily controlled regardless of the type of metal material, the parasitic resistance is low, the short channel effect and the drain leakage current are effective. It is possible to provide a semiconductor device that can be suppressed and a manufacturing method thereof.

(Second embodiment)
13A to 13E are cross-sectional views during each manufacturing process of the semiconductor device of the second embodiment. In the second embodiment, the region adjacent to the gate electrode in the surface of the P-type silicon substrate as the semiconductor layer includes nitrogen in the plasma state, nitrogen radicals, and an oxidant composed of molecules containing the nitrogen element. An example of forming an insulating layer and forming a fixed charge by exposure to an atmosphere containing at least one of gases will be described.

  First, an element isolation region (not shown) is formed on one main surface of a P-type silicon substrate 21 as an example of a semiconductor layer by a known method such as the STI method, and an element formation region is formed by the element isolation region. Is divided.

  Next, as shown in FIG. 13A, a gate insulating film 22 made of silicon oxide is formed on the surface of the element formation region by using a thermal oxidation method, a CVD method, an ALD method, or the like, followed by a CVD method. Etc., an N-type polycrystalline silicon film is deposited on the gate insulating film 22. Next, the gate electrode 23 is formed by patterning the polycrystalline silicon film using a lithography method, an RIE method, or the like.

  As the material of the gate insulating film 22, silicon oxynitride, silicon nitride, hafnium oxide, lanthanum oxide, or a material containing nitrogen, silicon, aluminum, or the like may be used instead of silicon oxide. .

  Further, although polycrystalline silicon is used as the material of the gate electrode 23, amorphous silicon, germanium, silicon containing germanium, or the like may be used.

Next, as shown in FIG. 13B, the silicon surface is nitrided by exposing the silicon surface to radicals containing nitrogen element, plasma, or the like to form a thin silicon nitride layer 24. The refractive index of silicon nitride is preferably set to 2.1 or higher. In this case, the silicon nitride layer 24 as an insulating layer having a high-density positive fixed charge can be formed. For example, in PE-CVD (Plasma Enhanced CVD) method, the conditions are 300 mTorr to 600 mTorr, gas flow rate ratio SiH ₄ / NH ₃ = 0.04 to 1.5, substrate temperature 300 ° C. to 450 ° C., plasma power 40 W to 100 W. Thus, silicon nitride having a refractive index of 2.1 or more can be formed.

  In the case of a P-type element, by setting the refractive index of silicon nitride to 1.8 or less, the silicon nitride layer 24 as an insulating layer having a high density of negative fixed charges can be formed. Further, by forming an aluminum oxide film by an ALD method or the like instead of the silicon nitride layer 24, an insulating film having a negative fixed charge can be formed.

  Next, a silicon oxide film is deposited using the CVD method or the like, and then anisotropically etched by the RIE method, thereby forming the gate sidewall layer 24. A silicon nitride film or a silicon oxynitride film may be used instead of the silicon oxide film. Alternatively, the gate sidewall layer 24 may be formed by anisotropic etching of the silicon nitride layer 24 without forming the silicon oxide film. Hereinafter, the semiconductor device can be manufactured by performing the steps shown in FIGS. 13C to 13E in the same manner as in the first embodiment. In FIG. 13E, the gate sidewall layer 24 forms an insulating layer.

(Embodiment 3)
14A to 14E are cross-sectional views in each manufacturing process of the semiconductor device of the third embodiment. In the third embodiment, cesium-containing regions are formed by ion-implanting cesium as an impurity that modulates the Schottky barrier into a P-type silicon substrate as a semiconductor layer, and then the cesium-containing regions are formed on the cesium-containing regions. An example in which the fixed charge is formed by segregating the cesium at the interface between the insulating layer and the semiconductor layer by forming an insulating layer by reacting with an element (for example, oxygen or nitrogen) different from the elements constituting the containing region. To do.

  First, an element isolation region (not shown) is formed on one main surface of a P-type silicon substrate 31 as an example of a semiconductor layer by a known method such as the STI method, and the element formation region is formed by the element isolation region. Is divided.

  Next, as shown in FIG. 14A, a gate insulating film 32 made of silicon oxide is formed on the surface of the element formation region by using a thermal oxidation method, a CVD method, an ALD method, or the like, followed by a CVD method. Etc., an N-type polycrystalline silicon film is deposited on the gate insulating film 32. Next, the gate electrode 33 is formed by patterning the polycrystalline silicon film using a lithography method, an RIE method, or the like.

  As the material of the gate insulating film 32, silicon oxynitride, silicon nitride, hafnium oxide, lanthanum oxide, or a material containing nitrogen, silicon, aluminum, or the like may be used instead of silicon oxide. .

  Further, although polycrystalline silicon is used as the material of the gate electrode 33, amorphous silicon, germanium, silicon containing germanium, or the like may be used.

Next, cesium-containing region 37 is formed by ion implantation of cesium, for example, under conditions of an acceleration energy of 5 keV and a dose of 1 × 10 ¹⁴ cm ⁻² . The ion implantation conditions are not limited to the above conditions, but may be set so that the cesium-containing region 37 is formed to a position deeper than the nickel silicide 38 (see FIG. 14E) formed in a later step. Good.

  Cesium (mass number 133) has a larger mass number than P (mass number 31), As (mass number 75), etc., which are normal donor impurities. Can be ion-implanted. In ion implantation, the smaller the ion implantation energy and the smaller the number of implanted species, the smaller the amount of current during ion implantation. There is a problem that it becomes long. Cesium has a larger mass number than normal donor impurities such as P and As, so it can take a larger amount of current. Therefore, the ion implantation time can be greatly shortened or ion implantation can be performed at a lower energy. It becomes possible. As a result, since the metal source / drain electrodes can be formed at extremely shallow positions, the short channel effect characteristics can be improved. Thereafter, annealing may be performed to recover the implantation damage. In that case, for example, RTA method, FLA method, laser annealing method or the like is used.

  Next, as shown in FIG. 14B, a silicon oxide film 34 is formed by oxidation using a thermal oxidation method. At this time, the surface of the cesium-containing region 37 is oxidized, and a part of cesium in the cesium-containing region 37 is segregated at the interface between the silicon oxide 34 and the cesium-containing region 37 and becomes a positive fixed charge 35. Instead of forming the silicon oxide film 34, the surface of the cesium-containing region 37 may be nitrided to form a silicon nitride film. In this case, a part of cesium in the cesium-containing region 37 is segregated at the interface between the silicon nitride film and the cesium-containing region 37 and becomes a positive fixed charge, and a positive fixed charge is also formed in the silicon nitride film. Therefore, a high density fixed charge can be formed.

  Next, as shown in FIG. 14C, a silicon nitride 36 is deposited using a CVD method or the like. Any material can be used as a substitute for the silicon nitride 36 as long as it has an insulating property, and examples thereof include silicon oxide and silicon oxynitride. If the silicon oxide film 34 is sufficiently thick, the silicon nitride 36 may be omitted.

  Next, as shown in FIG. 14D, gate sidewalls are formed by anisotropically etching the silicon nitride 36 and the silicon oxide film 34 using RIE or the like. Hereinafter, the semiconductor device can be manufactured by performing the process shown in FIG. 14E in the same manner as in the first embodiment.

(Embodiment 4)
15A to 15E are cross-sectional views in each manufacturing process of the semiconductor device of the fourth embodiment. In the fourth embodiment, cesium as an impurity for modulating a Schottky barrier is ion-implanted into silicon as a semiconductor layer to form a cesium-containing region, and then nitrided as an insulating layer in a region adjacent to the gate electrode. An example will be described in which a fixed charge is formed by segregating the cesium at the insulating layer / semiconductor interface by forming a silicon film and annealing.

  First, an element isolation region (not shown) is formed on one main surface of a P-type silicon substrate 41 as an example of a semiconductor layer by a known method such as the STI method, and the element isolation region is formed by the element isolation region. Is divided.

  Next, as shown in FIG. 15A, a gate insulating film 42 made of silicon oxide is formed on the surface of the element formation region by using a thermal oxidation method, a CVD method, an ALD method, or the like, followed by a CVD method. Etc., an N-type polycrystalline silicon film is deposited on the gate insulating film. Next, the gate electrode 43 is formed by patterning the polycrystalline silicon film using a lithography method, an RIE method, or the like.

  As the material of the gate insulating film 42, silicon oxynitride, silicon nitride, hafnium oxide, lanthanum oxide, or a material containing nitrogen, silicon, aluminum, or the like may be used instead of silicon oxide. . Further, although polycrystalline silicon is used as the material of the gate electrode 43, amorphous silicon, germanium, silicon containing germanium, or the like may be used.

Next, cesium-containing region 47 is formed by ion-implanting cesium, for example, under conditions of an acceleration energy of 5 keV and a dose of 1 × 10 ¹⁴ cm ⁻² . The ion implantation conditions are not limited to the above conditions, but may be set so that the cesium-containing region 47 is formed to a position deeper than the nickel silicide 48 (see FIG. 15E) formed in a later step. Good.

  Cesium (mass number 133) has a larger mass number than P (mass number 31), As (mass number 75), etc., which are normal donor impurities. Can be ion-implanted. In ion implantation, the smaller the ion implantation energy and the smaller the number of implanted species, the smaller the amount of current during ion implantation. There is a problem that it becomes long. Cesium has a larger mass number than normal donor impurities such as P and As, so it can take a larger amount of current. Therefore, the ion implantation time can be greatly shortened or ion implantation can be performed at a lower energy. It becomes possible. As a result, since the metal source / drain electrodes can be formed at extremely shallow positions, the short channel effect characteristics can be improved.

  Next, an insulating layer 44 made of silicon nitride is deposited by CVD or the like. Any material may be used for the insulating layer 44 as long as it has insulating properties, but cesium is difficult to thermally diffuse. For example, a material containing nitrogen such as silicon nitride, silicon oxynitride, or hafnium oxynitride is preferable.

Next, as shown in FIG. 15B, annealing is performed, for example, at 700 to 1000 ° C. for 1 to 10 seconds using the RTA method. At this time, a part of cesium in the cesium-containing region 47 is segregated at the interface between the insulating layer 44 and the P-type silicon substrate 41 and becomes a positive fixed charge.
Instead of the RTA method, annealing at a higher temperature and shorter time may be performed by using a FLA method or a laser annealing method.

  Next, as shown in FIG. 15C, a second insulating layer 46 made of silicon oxide is formed by CVD or the like. Instead of silicon oxide, silicon oxynitride, silicon nitride, or the like may be used. Further, when the insulating layer 44 is sufficiently thick, the second insulating layer 46 can be omitted.

  Next, as shown in FIG. 15E, the gate sidewalls are formed by anisotropically etching the insulating layer 44 and the second insulating layer 46 using the RIE method or the like. Hereinafter, the semiconductor device can be manufactured by performing the same process as in the first embodiment.

(Embodiment 5)
16A to 16F are cross-sectional views in each manufacturing process of the semiconductor device of the fifth embodiment. In the fifth embodiment, cesium-containing regions and fixed charges are implanted by simultaneously implanting cesium into both sides of the gate electrode on the P-type silicon substrate as the semiconductor layer and in the insulating layers on both sides of the gate electrode. An example of simultaneous formation will be described.

  First, an element isolation region (not shown) is formed on a main surface of a P-type silicon substrate 51 as an example of a semiconductor layer by a known method such as the STI method, and the element formation region is formed by the element isolation region. Is divided.

  Next, as shown in FIG. 16A, a gate insulating film 52 made of silicon oxide is formed on the surface of the element formation region by using a thermal oxidation method, a CVD method, an ALD method, or the like, followed by a CVD method. Etc. is used to deposit an N-type polycrystalline silicon film on the gate insulating film 52. Next, the gate electrode 53 is formed by patterning the polycrystalline silicon film using a lithography method, an RIE method, or the like.

  As the material of the gate insulating film 52, silicon oxynitride, silicon nitride, hafnium oxide, lanthanum oxide, or a material containing nitrogen, silicon, aluminum, or the like may be used instead of silicon oxide. .

Further, although polycrystalline silicon is used as the material of the gate electrode 53, amorphous silicon, germanium, silicon containing germanium, or the like may be used.
Next, a silicon oxide film 54 (for example, 10 to 15 nm) is deposited by a CVD method or the like.

  Next, as shown in FIG. 16B, a silicon nitride film 56 is deposited by CVD or the like. Subsequently, as shown in FIG. 16C, gate sidewalls are formed by anisotropically etching the silicon oxide film 54 and the silicon nitride film 56 by the RIE method or the like. Thereafter, as shown in FIG. 16D, the silicon nitride film 56 is selectively removed using hot concentrated phosphoric acid or the like.

Next, cesium is ion-implanted, for example, under the conditions of an acceleration energy of 5 keV and a dose of 1 × 10 ¹⁴ cm ⁻² to form a cesium-containing region 57 in the P-type silicon substrate 51 and at the same time, the silicon oxide film 54 A cesium-containing region 55 is formed therein. The ion implantation conditions are not limited to the above conditions, but may be set so that the cesium-containing region 57 is formed to a position deeper than the nickel silicide 58 (see FIG. 16F) formed in a later step. Good. Thus, by simultaneously forming the cesium-containing region 57 and the fixed charge (cesium-containing region 55), the process can be simplified, and the fixed charge and the cesium-containing region are formed using the same material. Therefore, manufacturing cost can be reduced.

  Cesium (mass number 133) has a larger mass number than P (mass number 31), As (mass number 75), etc., which are normal donor impurities. Can be ion-implanted. In ion implantation, the smaller the ion implantation energy and the smaller the number of implanted species, the smaller the amount of current during ion implantation. There is a problem that it becomes long. Cesium has a larger mass number than normal donor impurities such as P and As, so it can take a larger amount of current. Therefore, the ion implantation time can be greatly shortened or ion implantation can be performed at a lower energy. It becomes possible. As a result, since the metal source / drain electrodes can be formed at extremely shallow positions, the short channel effect characteristics can be improved.

  Next, for example, annealing is performed at 750 to 950 ° C. for 1 to 10 seconds using the RTA method. As a result, the cesium in the silicon oxide film 54 is segregated at the interface between the silicon oxide film 54 and the semiconductor layer (P-type silicon substrate 51) and becomes positive fixed charges at the same time as the implantation damage is recovered. In addition, instead of the RTA method, annealing at a higher temperature and shorter time may be performed by using a FLA method or a laser annealing method.

  Next, as shown in FIG. 16F, nickel silicide 58 is formed by the same method as in the first embodiment. Hereinafter, the semiconductor device can be manufactured by performing the same process as in the first embodiment.

(Sixth embodiment)
In the sixth embodiment, the present invention is applied to a FET having a three-dimensional channel structure such as a Fin-FET (three-dimensional structure-FET (Field Effect Transistor)), a tri-gate-FET, and a nanowire-FET. Can.

  17A to 17E are cross-sectional views during each manufacturing process of the semiconductor device of the sixth embodiment. Hereinafter, a method for manufacturing the semiconductor device of the present embodiment will be described with reference to FIGS. 17A to 17E.

  First, as shown in FIG. 17A, for example, in an SOI substrate in which silicon 61, silicon oxide 62, and silicon as an SOI layer are stacked in this order, the SOI layer is patterned to form an alphabet “I” character. A semiconductor region 63 is formed. The thickness of the SOI layer (semiconductor region 33) is, for example, 20 nm, and the width (Fin width) of the channel region in the semiconductor region 33 is, for example, 10 nm.

  Next, as shown in FIG. 17B, a gate insulating film 64 made of silicon oxide is formed on the surface of the semiconductor region 63 by using a thermal oxidation method, a CVD method, an ALD method, or the like. Subsequently, an N-type polycrystalline silicon film is deposited on the gate insulating film 64 using a CVD method or the like. Next, the gate electrode 65 is formed by patterning the polycrystalline silicon film using a lithography method, an RIE method, or the like. Subsequently, the gate insulating film 64 in a region not covered with the gate electrode 65 is removed by wet etching or the like using a hydrofluoric acid aqueous solution.

  As the material of the gate insulating film 64, silicon oxynitride, silicon nitride, hafnium oxide, lanthanum oxide, or a material containing nitrogen, silicon, aluminum, or the like may be used instead of silicon oxide. .

  Further, although polycrystalline silicon is used as the material of the gate electrode 65, amorphous silicon, germanium, silicon containing germanium, or the like may be used.

Next, as shown in FIG. 17C, after depositing a silicon oxide film 66 (for example, 10 to 15 nm) using the CVD method or the like, cesium is introduced into the silicon oxide film 66 using, for example, an ion implantation method. , A cesium-containing region 67 (not shown in FIGS. 17C to 17E, see FIG. 18). The ion implantation conditions are, for example, acceleration energy: 5 keV, dose amount: 4 × 10 ¹⁴ cm ⁻² . The ion implantation conditions may be selected so that the peak position of the cesium concentration distribution after ion implantation is located near the center of the silicon oxide film 66. Cesium may enter the semiconductor region 63.

Next, after depositing the silicon nitride film 68, for example, annealing is performed at 750 to 950 ° C. for 1 to 10 seconds by the RTA method. As a result, the cesium in the silicon oxide film 66 is segregated at the interface between the silicon oxide film 66 and the semiconductor region 63 and becomes positive fixed charges at the same time as the implantation damage is recovered. In addition, instead of the RTA method, annealing at a higher temperature and shorter time may be performed by using a FLA method or a laser annealing method.
Subsequently, anisotropic etching of the silicon oxide film 66 and the silicon nitride film 68 is performed using the RIE method or the like to form gate sidewalls.

Next, as shown in FIG. 17D, cesium-containing region 69 is formed by ion implantation of cesium, for example, under the conditions of an acceleration energy of 5 keV and a dose of 1 × 10 ¹⁴ cm ⁻² . The ion implantation conditions are not limited to the above conditions, but may be set so that the cesium-containing region 69 extends at least to the boundary with the silicon oxide 62. However, when the semiconductor region 63 is amorphized over the entire thickness direction of the SOI layer by ion implantation, the amorphized region is polycrystallized by heat treatment in a later process, and leakage current and parasitic resistance increase. However, by selecting the acceleration energy so that the concentration peak of cesium is located in a region shallower than the center in the thickness direction of the SOI layer, the semiconductor region 63 becomes amorphous throughout the thickness direction of the SOI layer. Therefore, at least the crystallinity of the semiconductor region 63 in the region in contact with the silicon oxide 62 can be maintained. In this case, solid phase growth of single crystal silicon is promoted by heat treatment in a later step, and the amorphous region can be single crystallized (implantation damage can be recovered).

  Note that as the thickness of the SOI layer or the Fin width decreases, the semiconductor region 33 is likely to be amorphous throughout the thickness direction of the SOI layer by ion implantation, and the above-described polycrystallization is likely to occur. As the gate length is reduced, the fin width (and SOI layer thickness) needs to be reduced in order to suppress the short channel effect, and thus the problem of polycrystallization becomes more prominent with the progress of miniaturization in the future. . In this embodiment mode, cesium having a mass number 75 larger than that of arsenic, which is a normal donor impurity, is used. Therefore, ions can be implanted into a region shallower than the arsenic with the same ion implantation energy. Therefore, compared to the case where the source / drain is formed by a high concentration impurity region such as arsenic or the case where the impurity segregation technique as disclosed in the above-mentioned Patent Document 1 is used, the amorphousness over the entire thickness direction of the SOI layer is achieved. It is difficult to cause crystallization, and it is easy to prevent the polycrystallization.

  Thereafter, annealing may be performed to recover the implantation damage. In that case, for example, RTA method, FLA method, laser annealing method or the like is used.

  Next, as shown in FIG. 17E, after depositing nickel, for example, about 3 nm to 4 nm by sputtering or the like, and subsequently depositing TiN (titanium nitride), for example, about 10 nm, for example, 260 ° C.-350 ° C., 30 seconds-200. Annealed and silicided for 2 seconds. Thereafter, unreacted nickel and TiN are removed to form a nickel silicide 610 as an example of a metal source / drain electrode. Thereafter, the nickel silicide 610 is lowered in resistance by annealing under conditions of 350 ° C. to 500 ° C. and 30 seconds to 200 seconds. In the present embodiment, the nickel silicide 610 is formed so that all silicon is nickel silicided in the thickness direction of the SOI layer in the narrowest region (Fin region) of the semiconductor region 63. However, only the surface portion of the semiconductor region 63 may be nickel-silicided to form the nickel silicide 610 (in this case, the DD ′ arrow cross-sectional view of FIG. 17E is not FIG. 18 but FIG. 20). Becomes). Further, the entire semiconductor region 63 except the channel region may be nickel-silicided (in this case, the cross-sectional view taken along the line DD ′ in FIG. 15E is FIG. 21 instead of FIG. 18). In either case, the cesium ion implantation is performed so that the metal source / drain electrode (nickel silicide 610) (hereinafter sometimes referred to as the metal source / drain electrode 610) is in contact with the semiconductor region 63 via the cesium-containing region 69. The conditions and the formation conditions of the nickel silicide 610 may be determined. The thickness of the nickel silicide 610 is formed in a region about three times (for example, about 9 nm to 12 nm) of the thickness of the sputtered nickel from the silicon surface. In FIG. 18, the nickel silicide 610 layer constitutes a metal source / drain electrode, the silicon oxide layer 62 constitutes an insulating layer, and the semiconductor region 63 constitutes a semiconductor layer.

  When the nickel silicide 610 is formed, the gate electrode 65 is also silicided to form a nickel silicide 611.

  In this case, the gate electrode 65 may be entirely silicided to have a metal gate structure. In the case of a metal gate structure, the polycrystalline silicon film may be either i-type or P-type.

  As an example of the metal source / drain electrodes, when cobalt silicide is formed instead of nickel silicide 610, cobalt is deposited by sputtering to about 5 nm, and then the conditions are 400 ° C. to 600 ° C. and 30 seconds to 200 seconds. Silicidation occurs by annealing. Then, after removing unreacted cobalt, the resistance of cobalt silicide may be reduced by annealing under conditions of 700 ° C. to 900 ° C. and 30 seconds to 200 seconds. Also in this case, the metal source / drain electrodes (cobalt silicide) are formed so as to be in contact with the semiconductor layer (semiconductor region 63) through the cesium-containing region 69. Note that the thickness of the cobalt silicide is formed in a region about twice the thickness of the sputtered cobalt (for example, about 10 nm) from the silicon surface.

  As described above, the case of nickel silicide 610 and cobalt silicide has been described as an example of the metal source / drain electrode. However, the metal source / drain electrode is not limited thereto. For example, metal silicide using a metal composed of one or more elements of Ni, Co, Ti, Er, Yb, and Pt may be used.

  Finally, an interlayer insulating film (not shown), an upper wiring (not shown), and the like are formed by a known method, thereby completing the semiconductor device. 18 is a cross-sectional view taken along the line DD ′ of FIG. 17E. FIG. 19 is a cross-sectional view taken along the line EE ′ of FIG. 17E.

  According to the semiconductor device of the present embodiment, the cesium-containing region (cesium-containing region 67) is formed between the metal source / drain electrode (nickel silicide) 610 and the semiconductor layer (semiconductor region 63). As a result, the energy barrier height against holes between the source / drain electrode 610 and the semiconductor layer is increased. As a result, the leakage current between the metal source / drain electrode and the semiconductor layer is reduced as compared with the Schottky junction. It can be significantly reduced. Further, by providing the fixed charge and cesium-containing region (cesium-containing region 67), the Schottky barrier height against electrons between the electron carrier layer and the metal source / drain electrode induced on the surface of the semiconductor layer under the fixed charge can be increased. Since it can be significantly reduced, a low resistance connection can be established between the channel and the metal source / drain electrode. Furthermore, since the electron carrier layer functions as a very shallow source / drain extension, extremely good short channel effect characteristics can be obtained. Furthermore, GIDL can be significantly reduced by the electric field due to the fixed charge. Accordingly, it is possible to significantly reduce the parasitic resistance and the leakage current while suppressing the short channel effect.

  In addition, according to the semiconductor device in this embodiment, since the short channel effect characteristic is not deteriorated due to the diffusion of the donor impurity, a very good short channel effect characteristic can be obtained even in a three-channel FET. .

  Note that when a planar transistor is formed using an SOI substrate, the same cross-sectional structure as that in FIG. 20 is obtained.

  In each of the above embodiments, the cesium-containing region is formed in the entire region in contact with the metal source / drain electrode in the P-type silicon substrate and the semiconductor (silicon) region. However, the present invention is not limited to all of the “contact region”, and the same effect can be obtained even if it is formed on a part of the “contact region”.

  Note that a new semiconductor device of the present invention or a new semiconductor device of the present invention can be obtained by combining two or more configurations (invention specific items) of the contents described in the above-described embodiments and the above-described modifications. Of course, the manufacturing method can be derived.

DESCRIPTION OF SYMBOLS 1 P-type silicon substrate 2 Gate insulating film 3 Gate electrode 4 Silicon oxide 5 Cesium containing area | region 6 Silicon nitride film 7 Cesium containing area | region 8 Metal source / drain electrode

Claims (17)

A semiconductor layer;
A gate electrode formed on the semiconductor layer via a gate insulating film;
Metal source / drain electrodes formed on both sides of the gate electrode on the semiconductor layer;
Of the surface of the semiconductor layer, comprising an insulating layer provided on the portion sandwiched between the gate electrode and the metal source / drain electrode,
The semiconductor layer has a cesium-containing region containing cesium in part or all of a region in contact with the metal source / drain electrode,
A semiconductor device, wherein a positive fixed charge is present in the insulating layer. The semiconductor device according to claim 1,
The semiconductor device, wherein the semiconductor layer is made of a semiconductor having an electron affinity greater than 3.89 eV. The semiconductor device according to claim 1 or 2,
The semiconductor device is characterized in that the semiconductor layer is made of any one of silicon, germanium, silicon germanium, gallium arsenide, and gallium nitride. The semiconductor device according to any one of claims 1 to 3,
It is cesium that constitutes at least a part of the fixed charge. 5. The semiconductor device according to claim 1, wherein:
The semiconductor device, wherein the insulating layer contains a nitrogen element. The semiconductor device according to any one of claims 1 to 5,
A semiconductor device, wherein a concentration of the cesium at an interface between the cesium-containing region and the metal source / drain electrode is 1 × 10 ¹⁹ cm ⁻³ or more. The semiconductor device according to any one of claims 1 to 6,
A concentration of the cesium in the cesium-containing region has a peak at a position deeper than an interface between the cesium-containing region and the metal source / drain electrode. The semiconductor device according to any one of claims 1 to 7,
The metal source / drain electrode is composed of a compound of a semiconductor constituting the semiconductor layer and a metal. The semiconductor device according to claim 8,
The semiconductor constituting the semiconductor layer includes at least one of silicon and germanium,
The semiconductor device includes one or more of nickel, cobalt, titanium, platinum, erbium, and ytterbium. The semiconductor device according to any one of claims 1 to 9,
The semiconductor layer is provided on an insulator,
At least a part of the metal source / drain electrode is in contact with the insulator. In the manufacturing method of the semiconductor device which manufactures the semiconductor device according to claim 1,
Forming a gate electrode on the semiconductor layer via a gate insulating film;
Forming an insulating layer on both sides of the gate electrode on the semiconductor layer;
Introducing cesium into the insulating layer;
Forming a fixed charge by segregating the cesium at the interface between the insulating layer and the semiconductor layer by annealing;
Anisotropically etching the insulating layer such that a part of the surface of the semiconductor layer is exposed to form a gate sidewall made of the insulating layer;
Introducing cesium into a region where the surface of the semiconductor layer is exposed to form a cesium-containing region;
Forming a metal source / drain electrode so as to be in contact with the cesium-containing region. In the manufacturing method of the semiconductor device which manufactures the semiconductor device according to claim 1,
Forming a gate electrode on the semiconductor layer via a gate insulating film;
At least a region adjacent to the gate electrode in the surface of the semiconductor layer includes an atmosphere containing at least one of a plasma state of nitrogen, a nitrogen radical, and a gas containing an oxidant composed of a molecule containing a nitrogen element. Exposing to an insulating layer to form a positive fixed charge;
Anisotropically etching the insulating layer such that a part of the surface of the semiconductor layer is exposed to form a gate sidewall made of the insulating layer;
Introducing cesium into a region where the surface of the semiconductor layer is exposed to form a cesium-containing region;
Forming a metal source / drain electrode so as to be in contact with the cesium-containing region. In the manufacturing method of the semiconductor device which manufactures the semiconductor device according to claim 1,
Forming a gate electrode on the semiconductor layer via a gate insulating film;
Introducing cesium on both sides of the gate electrode in the upper part of the semiconductor layer to form a cesium-containing region;
The upper part of the cesium-containing region reacts with an element different from the element constituting the cesium-containing region to form an insulating layer, thereby segregating and fixing the cesium at the interface between the semiconductor layer and the insulating layer Forming a charge;
Etching part of the insulating layer to form an opening of the insulating layer so that at least part of the surface of the cesium-containing region in the semiconductor layer is exposed;
Forming a metal source / drain electrode so as to be in contact with the cesium-containing region. In the manufacturing method of the semiconductor device which manufactures the semiconductor device according to claim 1,
Forming a gate electrode on the semiconductor layer via a gate insulating film;
Introducing cesium on both sides of the gate electrode on the semiconductor layer to form a cesium-containing region;
Forming an insulating layer so as to cover at least a region adjacent to the gate electrode in the surface of the cesium-containing region;
Forming a positive fixed charge by segregating the cesium at the interface between the insulating layer and the semiconductor layer by annealing;
Etching part of the insulating layer to form an opening of the insulating layer so that at least part of the surface of the cesium-containing region in the semiconductor layer is exposed;
Forming a metal source / drain electrode so as to be in contact with the cesium-containing region. In the manufacturing method of the semiconductor device which manufactures the semiconductor device according to claim 1,
Forming a gate electrode on the semiconductor layer via a gate insulating film;
Forming an insulating layer on both sides of the gate electrode of the surface of the semiconductor layer;
Introducing cesium on both sides of the gate electrode on the semiconductor layer and in the insulating layer to form a cesium-containing region and forming a positive fixed charge in the insulating layer;
Etching part of the insulating layer to form an opening of the insulating layer so that at least part of the surface of the cesium-containing region in the semiconductor layer is exposed;
Forming a metal source / drain electrode so as to be in contact with the cesium-containing region. In the manufacturing method of the semiconductor device according to any one of claims 11 to 15,
The step of forming the metal source / drain electrode includes:
Depositing a metal on the cesium-containing region;
A step of reacting the semiconductor constituting the semiconductor layer by annealing and the metal;
And a step of removing an unreacted portion that has not reacted with the semiconductor constituting the semiconductor layer out of the metal. In the manufacturing method of the semiconductor device according to claim 16,
The semiconductor constituting the semiconductor layer includes at least one of silicon and germanium,
The method for manufacturing a semiconductor device, wherein the metal contains at least one of nickel, cobalt, titanium, platinum, erbium, and ytterbium.

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