JP2013051313A - Semiconductor device, and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which allows the easy control of the height and width of a Schottky barrier, involves a low parasitic resistance, and enables the effective suppression of the short-channel effect.SOLUTION: The semiconductor device comprises metal source and drain electrodes (nickel silicide) 6, a P-type silicon substrate 1, and a cesium-containing region 5 formed between the metal source and drain electrodes and the silicon substrate. Thus, the height of an energy barrier against holes is made larger by ionizing cesium in the vicinity of the metal source and drain electrodes 6, thereby significantly reducing a leak current between the metal source and drain electrodes 6 and the P-type silicon substrate 1. In addition, the height and width of a Schottky barrier between a channel and the metal source and drain electrodes 6 are reduced effectively, whereby the parasitic resistance is remarkably reduced. Thus, the thickness (depth) of the metal silicide can be determined without any restriction by ion implantation. Therefore, extremely shallow source and drain can be formed, and a good characteristic in connection with a short-channel effect can be obtained.

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof.

  High performance of semiconductor integrated circuits has been advanced by miniaturization of MOSFETs (MOS field effect transistors). In the future, in order to continue the miniaturization of MOSFETs, it is essential to suppress the deterioration of characteristics due to the short channel effect that becomes more prominent with the miniaturization. Here, in order to suppress the short channel effect, it is very effective to form the source / drain shallower. At the same time, in order to obtain a high on-current, the source / drain needs to have a low resistance.

  Usually, the source / drain is formed by ion-implanting a high concentration donor or acceptor into a semiconductor and then performing activation annealing. In order to reduce the source / drain junction depth formed in this way, it is necessary to reduce ion implantation energy (acceleration energy). However, if the ion implantation energy is extremely small (for example, 1 keV or less), it becomes difficult to secure a sufficient dose per unit time, which makes it very difficult to apply to a mass production process. Also, the junction depth becomes deep due to thermal diffusion of impurities by activation annealing. On the other hand, the source / drain resistance increases as the junction depth decreases. For these reasons, the shallow junction of the source / drain has become increasingly difficult in recent years.

  As a method for solving such a problem, a metal source / drain structure in which a source / drain is formed using a metal such as metal silicide has been proposed (for example, Non-Patent Document 1). The metal silicide is formed by depositing a metal on silicon as a semiconductor and then performing heat treatment such as RTA (Rapid Thermal Annealing). The film thickness of such a metal silicide can be controlled by the film thickness of the deposited metal, so that it can be easily controlled. Therefore, a very shallow source / drain can be easily formed. In addition, since the source and drain are made of metal, it is expected that the resistance can be made extremely low.

  However, since the Schottky junction is formed between the metal and the semiconductor in the metal source / drain structure, the leakage current between the source / drain and the semiconductor is large. There is a problem that the on-current is reduced due to the Schottky barrier formed between the two.

  In order to solve such a problem, Japanese Patent Application Laid-Open No. 2005-101588 (Patent Document 1) introduces impurities such as As and B into a silicon substrate as a semiconductor, and then from the region where the impurities are implanted. Impurities are segregated near the interface between the metal silicide and silicon by forming metal silicide (metal source / drain) to a deeper region, and the region that is in contact with the metal silicide has a conductivity type opposite to that of the silicon substrate and is depleted. A technique for forming a region is disclosed.

  In the field effect transistor disclosed in Patent Document 1, the junction characteristics between the metal source / drain and the semiconductor are in an intermediate state between the pn junction and the Schottky junction. Also, leakage current can be suppressed. Further, compared to the case of Non-Patent Document 1, the height of the Schottky barrier formed between the channel and the source / drain is effectively reduced, so that the on-current can be improved.

  However, in the technique disclosed in Patent Document 1, it is necessary to form the metal silicide up to a position deeper than the region into which the impurity is implanted. Therefore, the depth of the source / drain is made shallower than the impurity implantation depth. I can't. That is, there is a problem that it is impossible in principle to form a source / drain shallower than the conventional method of forming a source / drain using a pn junction.

  In addition, since the impurities used are semiconductor donor impurities or acceptor impurities, the impurities are thermally diffused when heat treatment is performed to recover crystal defects caused by impurity activation or ion implantation after the impurities are implanted. Resulting in. Therefore, there is a problem that it becomes more difficult to form a shallow source / drain.

JP 2005-101588 A

See Wang, John P. Snyder, J. P. Snyder, JRTucker, "Applied Physics Letters", American Institute of the United States・ Physics (American Institute of Physics), Volume 74 (VOL.74), 1999, P.1174-1176

  Accordingly, an object of the present invention is to provide a semiconductor device capable of easily controlling the height and width of the Schottky barrier regardless of the type of metal material, having low parasitic resistance, and effectively suppressing the short channel effect, and It is in providing the manufacturing method.

In order to solve the above problems, a semiconductor device of the present invention is
Semiconductors,
A gate electrode formed on the semiconductor via a gate insulating film;
Metal source / drain electrodes formed on both sides of the gate electrode on the semiconductor,
In part or all of the region in contact with the metal source / drain electrode in the semiconductor has an impurity-containing region containing an impurity that modulates a Schottky barrier,
The impurity is an impurity that hardly generates carriers in the bulk of the semiconductor.

  According to the above configuration, an impurity region containing an impurity that modulates the Schottky barrier is provided in part or all of the region in contact with the metal source / drain electrode in the semiconductor. Therefore, the leakage current between the semiconductor and the metal source / drain electrode can be remarkably suppressed, and the resistance between the channel and the metal source / drain electrode can be significantly reduced.

  Further, since the impurities hardly generate carriers in the bulk of the semiconductor, even if the impurity-containing region is formed deeper than the metal source / drain electrodes, the short channel effect characteristics are not deteriorated. . That is, the source / drain can be formed in a region shallower than the impurity implantation depth, and an extremely shallow source / drain can be formed. Therefore, good short channel effect characteristics can be obtained.

In the semiconductor device of one embodiment,
In addition to part or all of the region in contact with the metal source / drain electrode in the semiconductor, the impurity is in a region including part or all of the region in contact with the semiconductor in the metal source / drain electrode. Is also included,
The work function of the impurities is smaller than the work function of the metal source / drain electrodes.

  According to this embodiment, in the region including part or all of the region in contact with the semiconductor in the metal source / drain electrode, the impurity having a work function smaller than that of the metal source / drain electrode is present. include. Therefore, the work function of the metal source / drain electrodes can be reduced, and the Schottky barrier height for electrons can be further reduced. That is, the parasitic resistance of the N-type MOSFET can be reduced.

In the semiconductor device of one embodiment,
In addition to part or all of the region in contact with the metal source / drain electrode in the semiconductor, the impurity is in a region including part or all of the region in contact with the semiconductor in the metal source / drain electrode. Is also included,
The work function of the impurity is larger than the work function of the metal source / drain electrode.

  According to this embodiment, the impurity whose work function is larger than the work function of the metal source / drain electrode is present in a region including part or all of the region in contact with the semiconductor in the metal source / drain electrode. include. Therefore, the work function of the metal source / drain electrodes can be reduced, and the Schottky barrier height for holes can be further reduced. That is, the parasitic resistance of the P-type MOSFET can be reduced.

In the semiconductor device of one embodiment,
The mass number of the impurities is greater than 75.

  According to this embodiment, when the impurity contained in the semiconductor is introduced by ion implantation, the mass number of the impurity is larger than the mass number 75 of arsenic, which is a normal donor impurity, and therefore the same ion implantation energy. Can be implanted into a region shallower than the arsenic. Conversely, when ion implantation is performed at the same depth, the ion implantation energy of the impurity can be made larger than the ion implantation energy of the arsenic, so that the amount of ion current can be increased and the process time can be shortened. Can do. In particular, according to the above impurities, it is possible to avoid the problem that a sufficient dose cannot be secured when ion implantation is performed with very small ion implantation energy.

In the semiconductor device of one embodiment,
The impurity has an ionization potential smaller than the electron affinity of the semiconductor.

  According to this embodiment, since the ionization potential of the impurity is smaller than the electron affinity of the semiconductor, the impurity forms an energy level (impurity level) on the higher energy side than the lower end of the conduction band of the semiconductor. To do. Then, electrons are emitted from the impurity level to the metal source / drain electrode side, the impurity is positively ionized, and in the region where the impurity is ionized, the energy band of the semiconductor has the impurity level and the metal It is bent to the extent that the Fermi level of the source / drain electrodes coincides. Therefore, the Schottky barrier is greatly modulated.

  Therefore, in the N-type MOSFET, the leakage current between the semiconductor and the metal source / drain electrode can be remarkably suppressed, and the resistance between the channel and the metal source / drain electrode can be significantly reduced.

In the semiconductor device of one embodiment,
The impurity is cesium.

  According to this embodiment, since the ionization potential 3.89 eV of cesium is smaller than, for example, the electron affinity 4.05 eV of silicon, the cesium has an energy level (impurity level) higher than the lower end of the conduction band of silicon. Level). Therefore, the Schottky barrier can be easily modulated greatly. Note that cesium hardly generates carriers in the bulk of silicon.

In the semiconductor device of one embodiment,
The concentration of the impurity at the interface between the impurity-containing region and the metal source / drain electrode is 1 × 10 ¹⁹ cm ⁻³ or more.

  According to this embodiment, the concentration of the impurity at the interface with the metal source / drain electrode is sufficiently high. Therefore, the Schottky barrier is greatly modulated, the leakage current between the semiconductor and the metal source / drain electrode is remarkably suppressed, and the resistance between the channel and the metal source / drain electrode is remarkably reduced.

In the semiconductor device of one embodiment,
The concentration of the impurity in the impurity-containing region has a peak at a position deeper than the interface between the impurity-containing region and the metal source / drain electrode.

  According to this embodiment, since a wide range of the metal source / drain electrodes can be covered with a high concentration impurity region, the leakage current between the semiconductor and the metal source / drain electrodes can be effectively reduced. Can do.

In the semiconductor device of one embodiment,
The metal source / drain electrodes are composed of a compound of the semiconductor and metal.

  According to this embodiment, the depth of the metal source / drain electrode can be controlled by the thickness of the metal deposited on the semiconductor. Therefore, shallow metal source / drain electrodes can be easily formed by thinly depositing the metal on the semiconductor by sputtering or the like.

In the semiconductor device of one embodiment,
The semiconductor contains at least one of silicon and germanium as a main component,
The metal includes one or more of nickel, cobalt, titanium, erbium, ytterbium and platinum elements.

  According to this embodiment, since the self-aligned silicide process or the self-aligned germanide process can be used, the shallow metal source / drain electrodes are easily formed in a self-aligned position with respect to the gate electrode. can do.

In the semiconductor device of one embodiment,
The semiconductor is provided on an insulator,
At least a part of the metal source / drain electrode is in contact with the insulator.

  According to this embodiment, in a semiconductor device having an SOI (Semiconductor On Insulator) structure, the leakage current between the semiconductor and the metal source / drain electrode can be remarkably suppressed, and the resistance between the channel and the metal source / drain electrode can be reduced. Can be significantly reduced. Furthermore, it is possible to form a very shallow source / drain and to obtain good short channel effect characteristics.

In addition, a method for manufacturing a semiconductor device according to the present invention includes:
Forming a gate electrode on a semiconductor via a gate insulating film;
Introducing the impurity on both sides of the gate electrode in the upper part of the semiconductor to form the impurity-containing region;
Depositing a metal on the impurity-containing region in the semiconductor;
Forming a metal source / drain electrode on both sides of the gate electrode in the upper part of the semiconductor by reacting the semiconductor with the metal by annealing; and
The impurity-containing region is formed in part or all of a region in contact with the metal source / drain electrode in the semiconductor.

  According to the above configuration, the impurity region containing the impurity that modulates the Schottky barrier is formed in part or all of the region in contact with the metal source / drain electrode in the semiconductor. Therefore, it is possible to form a semiconductor device in which the leakage current between the semiconductor and the metal source / drain electrode can be remarkably suppressed and the resistance between the channel and the metal source / drain electrode can be significantly reduced.

  Furthermore, since the impurities do not generate carriers in the bulk of the semiconductor, even if the impurity-containing region is formed deeper than the metal source / drain electrodes, the short channel effect characteristics are not deteriorated. That is, the source / drain can be formed in a region shallower than the impurity implantation depth, and an extremely shallow source / drain can be formed. Accordingly, a semiconductor device having good short channel effect characteristics can be formed.

In the manufacturing method of the semiconductor device of one embodiment,
The impurity is cesium.

  According to this embodiment, since the ionization potential 3.89 eV of cesium is smaller than, for example, the electron affinity 4.05 eV of silicon, the cesium has an energy level (impurity level) higher than the lower end of the conduction band of silicon. Level). Therefore, the Schottky barrier can be easily modulated greatly. Note that cesium hardly generates carriers in the bulk of silicon.

In the manufacturing method of the semiconductor device of one embodiment,
The semiconductor contains at least one of silicon and germanium as a main component,
The metal includes one or more of nickel, cobalt, titanium, erbium, ytterbium and platinum elements.

  According to this embodiment, since the self-aligned silicide process or the self-aligned germanide process can be used, the shallow metal source / drain electrodes are easily formed in a self-aligned position with respect to the gate electrode. can do.

  As is clear from the above, according to the present invention, the semiconductor region has an impurity region containing an impurity that modulates the Schottky barrier in part or all of the region in contact with the metal source / drain electrode. The leakage current between the semiconductor and the metal source / drain electrode can be remarkably suppressed, and the resistance between the channel and the metal source / drain electrode can be significantly reduced.

  Further, since the impurities hardly generate carriers in the bulk of the semiconductor, even if the impurity-containing region is formed deeper than the metal source / drain electrodes, the short channel effect characteristics are not deteriorated. . That is, the source / drain can be formed in a region shallower than the impurity implantation depth, and an extremely shallow source / drain can be formed. Therefore, good short channel effect characteristics can be obtained.

It is sectional drawing in each manufacturing process in 1st Embodiment in the semiconductor device of this invention. It is sectional drawing of the semiconductor device manufactured by the manufacturing method shown in FIG. It is sectional drawing of the diode produced by the method similar to the metal source / drain electrode in FIG. It is a figure which shows the current-voltage characteristic in FIG. FIG. 4 is a band diagram in FIG. 3. FIG. 4 is a band diagram when there is no cesium-containing region in FIG. 3. FIG. 4 is a diagram showing current-voltage characteristics when N-type silicon is used in FIG. 3. It is a band figure at the time of using N type silicon in FIG. FIG. 4 is a band diagram when N-type silicon is used in FIG. 3 and no cesium-containing region exists. It is a band figure in the BB 'cross section in FIG. FIG. 3 is a band diagram at the BB ′ cross section when no cesium-containing region exists in FIG. 2. It is sectional drawing in each manufacturing process in 2nd Embodiment. It is sectional drawing in each manufacturing process in 3rd Embodiment. It is sectional drawing in each manufacturing process following FIG. It is sectional drawing in the manufacturing process following FIG. It is DD 'arrow sectional drawing of FIG.15 (e). It is EE 'arrow sectional drawing of FIG.15 (e). It is DD 'arrow sectional drawing of FIG.15 (e) different from FIG. FIG. 19 is a cross-sectional view taken along the line DD ′ in FIG. 15 (e) different from FIGS.

  Hereinafter, the present invention will be described in detail with reference to the illustrated embodiments.

  The semiconductor that can be used in the present invention is not particularly limited, but silicon, germanium, SiGe, GaAs, carbon nanotubes, and the like can be used. Further, it may be an SOI (Semiconductor On Insulator) substrate or a strained semiconductor substrate in which carrier mobility is improved by applying strain to the crystal. In addition, a polycrystalline semiconductor or an amorphous semiconductor formed on a glass substrate or the like may be used.

  In each of the following embodiments, the description will focus on an N-type channel element using cesium as an impurity, but a P-type channel element is obtained by reversing the conductivity type of the impurity and the polarity of the fixed charge. be able to. Of course, both types of elements may be formed on the same substrate.

(First embodiment)
FIG. 1 is a cross-sectional view in each manufacturing process of the semiconductor device of the first embodiment. FIG. 2 is a cross-sectional view of the semiconductor device manufactured by the manufacturing method shown in FIG. A method for manufacturing the semiconductor device of the present embodiment will be described below with reference to FIGS.

  First, an element isolation region (not shown) is formed on one main surface of a P-type silicon substrate 1 as an example of a semiconductor by a known method such as an STI (Shallow Trench Isolation) method. The element formation region is divided by the element isolation region.

  Next, as shown in FIG. 1A, by using a thermal oxidation method, a CVD (Chemical Vapor Deposition) method, an ALD (Atomic Layer Deposition) method, or the like, A gate insulating film 2 made of silicon oxide is formed on the surface of the formation region, and then an N-type polycrystalline silicon film is deposited on the gate insulating film 2 using a CVD method or the like. Next, the gate electrode 3 is formed by patterning the polycrystalline silicon film using a lithography method, a reactive ion etching (RIE) method, or the like.

  As the material of the gate insulating film 2, silicon oxynitride, silicon nitride, hafnium oxide, lanthanum oxide, or a material containing these materials containing nitrogen, silicon, aluminum, or the like may be used instead of silicon oxide. Good.

  Further, although polycrystalline silicon is used as the material of the gate electrode 3, amorphous silicon, germanium, silicon containing germanium, or the like may be used.

  Next, as shown in FIG. 1B, a silicon oxide film is deposited using a CVD method or the like, and then etched back by an RIE method, thereby forming a gate sidewall film 4.

  As a material for the gate sidewall film 4, silicon nitride, silicon oxynitride, or the like may be used instead of silicon oxide.

The gate sidewall film 4 may contain positive fixed charges. For example, the gate sidewall film 4 containing positive fixed charges can be formed by introducing an impurity that becomes positive fixed charges such as cesium into the silicon oxide by an ion implantation method or the like. Further, instead of the silicon oxide, a radical containing silicon element or plasma is exposed to the silicon surface to nitride the silicon surface to form a thin silicon nitride, or a refractive index of 2.1 or more by the CVD method or the like. The gate sidewall film 4 containing positive fixed charges can also be formed by forming this silicon nitride. By setting the refractive index of silicon nitride to 2.1 or more, a high-density fixed charge can be formed. For example, in PE-CVD (Plasma Enhanced CVD) method, the conditions are 300 mTorr to 600 mTorr, gas flow rate ratio SiH ₄ / NH ₃ = 0.04 to 1.5, substrate temperature 300 ° C. to 450 ° C., plasma power 40 W to 100 W. Thus, silicon nitride having a refractive index of 2.1 or more can be formed. In addition, the gate sidewall film 4 including the fixed charge is formed by etching back the laminated film on which the insulating film such as silicon oxide is deposited on the insulating film including the fixed charge formed by the method described above. May be.

  As described above, when the gate sidewall film 4 includes a positive fixed charge, at least one of the metal source / drain electrodes formed in a later process is offset with respect to the gate electrode 3 due to process variation or the like. However, since the electron carrier layer is formed on the silicon surface as the semiconductor under the gate side wall film 4 containing the fixed charge, the channel region and the metal source / drain electrodes may be ohmically connected via the electron carrier layer. And increase in parasitic resistance can be prevented. Thereby, the yield can be dramatically improved. Since the electron carrier layer is extremely thin, the short channel effect characteristic is not deteriorated.

但し、

ここで、κ：シリコン(半導体)の比誘電率、ε：真空の誘電率(Ｆ/cm)、ｑ：電荷素量(Ｃ)、Ｎ_i：シリコン(半導体)の真性キャリア密度(cm^-3)、ｋ_B：ボルツマン定数(eＶ/Ｋ)、Ｔ：絶対温度(Ｋ)である。例えば、Ｎ_A＝１×１０¹⁸cm^-3のとき、
σ_FC≧３.５×１０¹²cm^-2
とすることにより、上記電子キャリア層を形成することができる。 The fixed charge density σ _FC (cm ⁻² ) in the gate sidewall film 4 satisfies the following condition when the P-type impurity concentration N _A (cm ⁻³ ) in the silicon near the end of the gate electrode 3 is satisfied. By satisfy | filling, said electron carrier layer can be formed.

However,

Where κ: relative dielectric constant of silicon (semiconductor), ε: dielectric constant of vacuum (F / cm), q: elementary charge (C), _Ni : intrinsic carrier density of silicon (semiconductor) (cm ⁻³⁾ ), K _B : Boltzmann constant (eV / K), T: absolute temperature (K). For example, when N _A = 1 × 10 ¹⁸ cm ⁻³ ,
σ _FC ≧ 3.5 × 10 ¹² cm ^-2
Thus, the electron carrier layer can be formed.

More preferably, σ _FC = 1 × 10 ¹³ cm ^{−2 to} 3 × 10 ¹³ cm ⁻² . At this time, the resistance of the electron carrier layer becomes the lowest, and the resistance increase due to the offset can be prevented most effectively. As σ _FC increases, the electron carrier density increases, but the mobility decreases. ^Therefore , the resistance of the electron carrier layer is lowest at σ _FC = 1 × 10 ¹³ cm ^{−2 to} 3 × 10 ¹³ cm ^−2. Become.

  In the case of a P-type element, the same effect as described above can be obtained by making the polarity of the fixed charge negative. For example, the gate sidewall film 4 having a negative fixed charge is formed by forming silicon nitride having a dielectric constant of less than 1.9 or aluminum oxide formed by using an ALD method or the like and then etching back. Can do.

Next, as shown in FIG. 1C, cesium as an impurity that modulates the Schottky barrier between the semiconductor and the metal source / drain electrodes is, for example, accelerated energy of 5 keV and dose of 1 × 10 ¹⁴ cm ⁻² . The cesium-containing region 5 is formed by ion implantation under conditions. The ion implantation conditions are not limited to the above conditions, but the cesium-containing region 5 is formed so as to be deeper than the nickel silicide 6 (see FIG. 1D) formed in a later step. do it.

  Cesium (mass number 133) has a larger mass number than P (mass number 31), As (mass number 75), etc., which are normal donor impurities. Can be ion-implanted. In ion implantation, the smaller the ion implantation energy and the smaller the number of implanted species, the smaller the amount of current during ion implantation. There is a problem that it becomes long. Cesium has a larger mass number than normal donor impurities such as P and As, so it can take a larger amount of current. Therefore, the ion implantation time can be greatly shortened or ion implantation can be performed at a lower energy. It becomes possible. As a result, since the metal source / drain electrodes can be formed at extremely shallow positions, the short channel effect characteristics can be improved.

  The cesium ion implantation may be performed so that cesium is introduced into the gate sidewall film 4 simultaneously with the formation of the cesium-containing region 5 by adjusting the tilt angle. In that case, since cesium is ionized in the gate side wall film 4 and becomes a positive fixed charge, at least one of the metal source / drain electrodes formed in the subsequent process is offset with respect to the gate electrode 3 due to process variations or the like. Even in this case, since the electron carrier layer is formed immediately below the gate sidewall film 4 containing a fixed charge, the channel region and the metal source / drain electrodes can be connected ohmic via the electron carrier layer, An increase in parasitic resistance can be prevented. Thereby, the yield can be dramatically improved. Since the electron carrier layer is extremely thin, the short channel effect characteristic is not deteriorated.

  Thus, the process can be simplified by simultaneously forming fixed charges in the cesium-containing region 5 and the gate sidewall film 4 using the same impurity.

  Thereafter, annealing may be performed to recover the implantation damage. In that case, for example, RTA method, FLA (Flash Lamp Annealing) method, laser annealing method or the like is used.

  Next, as shown in FIG. 1 (d), nickel is deposited by, for example, about 2 nm by sputtering or the like, and then annealed at 260 ° C. to 350 ° C. for 30 seconds to 200 seconds to be silicided. In that case, TiN may be deposited on nickel by sputtering or the like before the annealing. Thereafter, unreacted nickel (and TiN) is removed to form the nickel silicide 6 as an example of a metal source / drain electrode. After that, the resistance of the nickel silicide 6 is reduced by annealing under conditions of 350 ° C. to 500 ° C. and 30 seconds to 200 seconds. In this case, the nickel is used so that the metal source / drain electrode (nickel silicide 6) (hereinafter sometimes referred to as the metal source / drain electrode 6) is in contact with the semiconductor (P-type silicon substrate 1) through the cesium-containing region 5. The silicide 6 is formed so that at least its thickness (depth) is thinner (shallow) than the cesium-containing region 5. The thickness of the nickel silicide 6 is about three times the thickness of the sputtered nickel (for example, about 6 nm).

  As a result of the above process, the metal source / drain electrode (nickel silicide 6) may contain a part of cesium as an impurity that modulates the Schottky barrier between the semiconductor and the metal source / drain electrode. In this case, since the work function of cesium (1.93 eV) is smaller than that of nickel silicide (NiSi) (4.9 eV), the work function of the metal source / drain electrodes is reduced, and the Schottky barrier height against electrons is increased. Can be further reduced. In the case of a P-type MOSFET, the work function of the metal source / drain electrode can be increased by using a material having a work function larger than that of the metal source / drain electrode instead of cesium, and Schottky for holes. The barrier height can be further reduced.

  The nickel silicide 6 functions as a source / drain.

  When the nickel silicide 6 is formed, the gate electrode 3 is also silicided to form nickel silicide 7. Thus, a semiconductor device as shown in FIG. 2 is formed.

  In this case, the gate electrode 3 may be entirely silicided to have a metal gate structure. In the case of a metal gate structure, the polycrystalline silicon film may be either i-type or P-type.

  As an example of the metal source / drain electrodes, in the case where cobalt silicide is formed instead of nickel silicide 6, after depositing about 3 nm of cobalt by sputtering or the like, conditions of 400 ° C. to 600 ° C., 30 seconds to 200 seconds are used. It is silicidized by annealing. In that case, TiN may be deposited on cobalt by sputtering or the like before the annealing. Then, after removing unreacted cobalt (and TiN), the resistance of cobalt silicide may be reduced by annealing under conditions of 700 ° C. to 900 ° C. and 30 seconds to 200 seconds. Also in this case, the cobalt silicide is at least thinner than the cesium-containing region so that the metal source / drain electrodes (cobalt silicide) are in contact with the semiconductor (P-type silicon substrate 1) via the cesium-containing region 5. To form. The thickness of the cobalt silicide is about twice the thickness of the sputtered cobalt (for example, about 6 nm).

  As described above, the case of nickel silicide 6 and cobalt silicide has been described as an example of the metal source / drain electrode. However, the metal source / drain electrode is not limited thereto. For example, metal silicide using a metal composed of one or more elements of Ni, Co, Ti, Er, Yb, and Pt may be used.

  Finally, an interlayer insulating film (not shown), an upper wiring (not shown), and the like are formed by a known method, thereby completing the semiconductor device.

  According to the semiconductor device of the present embodiment, the cesium-containing region 5 is formed between the metal source / drain electrode 6 (nickel silicide 6) and the semiconductor (P-type silicon substrate 1). The ionization of cesium in the vicinity of the electrode increases the energy barrier height against holes. As a result, the leakage current between the source / drain and the semiconductor can be significantly reduced as compared with the Schottky junction. At the same time, since the Schottky barrier height for electrons between the channel and the source / drain is effectively reduced, the parasitic resistance can be significantly reduced as compared with the Schottky junction.

In that case, if the concentration of cesium at the interface with the metal source / drain electrode 6 in the cesium-containing region 5 is set to 1 × 10 ¹⁹ cm ⁻³ or more, the concentration of cesium at the interface with the metal source / drain electrode 6 is increased. Can be big enough. Therefore, the Schottky barrier can be modulated more greatly to reduce the leakage current between the source / drain and the semiconductor and the parasitic resistance between the channel / source / drain more effectively. .

  Further, if the cesium concentration in the cesium-containing region 5 is set to have a peak at a position deeper than the interface with the metal source / drain electrode 6 in the cesium-containing region 5, a wide range of the metal source / drain electrode 6 can be obtained. Can be covered with a high concentration cesium region. Therefore, the leakage current between the source / drain and the semiconductor can be further effectively reduced.

  Further, since cesium is not a silicon donor and acceptor, cesium is not ionized in a region sufficiently separated from the metal source / drain electrode 6 in the cesium-containing region 5. Therefore, it is not necessary to extremely reduce the thickness of the cesium-containing region 5 between the metal source / drain electrode 6 and the semiconductor (P-type silicon substrate 1) (that is, there is no restriction when cesium is ion-implanted). Therefore, it is not necessary to use an impurity segregation technique as disclosed in Patent Document 1.

  As described above, in the semiconductor device of the present embodiment, since the thickness (depth) of the metal silicide can be determined without restriction by ion implantation, it is possible to form extremely shallow metal sources / drains. The channel effect can be suppressed very well.

  In order to confirm the effect of having the cesium-containing region 5 in the semiconductor device of the present embodiment, the following experiment was performed.

FIG. 3 is a cross-sectional view of a diode manufactured by the same method as that for the metal source / drain electrode 6 in FIG. That is, this diode is obtained by forming a cesium-containing region 12 on the surface of P-type silicon 11 and then forming nickel silicide 13. Nickel silicide 13 is in contact with P-type silicon 11 through cesium-containing region 12. As a result of analysis by SIMS (secondary ion mass spectrometry), the cesium concentration in the cesium-containing region 12 was 1 × 10 ¹⁹ cm ⁻³ at the interface with the nickel silicide 13. Further, the distribution of cesium has a peak in the P-type silicon 11 outside the nickel silicide 13.

  FIG. 4 shows current-voltage characteristics measured between the nickel silicide 13 and the back surface of the P-type silicon 11 in FIG. FIG. 4 also shows the current-voltage characteristics of a diode having no cesium-containing region for comparison. The bias voltage on the horizontal axis is a voltage applied to the nickel silicide 13 with respect to the P-type silicon 11.

  As can be seen from FIG. 4, when the cesium-containing region 12 is provided, the reverse bias current is remarkably smaller than when the cesium-containing region is not provided. This indicates that the leak current between the metal source / drain electrode 6 and the P-type silicon substrate 1 can be remarkably reduced in the source / drain structure shown in FIG.

  Hereinafter, the reason for this will be described with reference to FIGS.

5 and 6 are band diagrams in the CC ′ section in FIG. However, FIG. 6 is a band diagram in the case where the cesium-containing region 12 does not exist. 5 and FIG. 6, “E _C ^Si ” is the lower conduction band of silicon, “E _F ^Si ” is the Fermi level of silicon, and “E _V ^Si ” is the valence band of silicon. On the top, “E _F ^M ” indicates the Fermi level of the nickel silicide 13, and “φ _b ^h ” indicates the barrier height against holes.

ここで、φ_ｂ ^ｈ：正孔に対するショットキー障壁高さ、ｋ_Ｂ：ボルツマン定数、Ｔ：絶対温度である。尚、φ_ｂ ^ｈはニッケルシリサイド１３のフェルミ準位Ｅ_Ｆ ^ＭとＰ型シリコン１１の価電子帯上端Ｅ_Ｖ ^Ｓiとのエネルギー差である。 Since the diode shown in FIG. 6 is a Schottky barrier diode, the reverse bias current I _rp is expressed by the following formula (1).

Here, φ _b ^h : Schottky barrier height with respect to holes, k _B : Boltzmann constant, and T: absolute temperature. Incidentally, phi _b ^h is the energy difference between the valence band maximum _E ^{V Si} of the Fermi level _E ^{F M} and P-type silicon 11 of nickel silicide 13.

In FIG. 5, the ionization potential of cesium is 3.89 eV, whereas the electron affinity of silicon is 4.05 eV. Therefore, cesium has an energy level higher than the lower conduction band E _C ^Si of silicon. Is thought to form. In this case, electrons are emitted from the energy level produced by cesium to the nickel silicide 13 side, and cesium is positively ionized. In the region where cesium is ionized, the silicon band is greatly depressed in accordance with the density of cesium. That is, when the density of the cesium is sufficiently large, to the lowest point of the bottom of the conduction band E _C ^Si of the silicon is substantially coincident with the Fermi level E _F ^M nickel silicide 13, silicon band is bent.

  On the other hand, since cesium does not activate as a donor for silicon, cesium at a position away from the nickel silicide 13 in the cesium-containing region 12 remains neutral. In addition, since the emission of electrons from cesium at a position away from the interface with the P-type silicon 11 in the cesium-containing region 12 to the nickel silicide 13 mainly occurs due to the tunnel effect, the cesium ionizes the nickel silicide 13. And from the interface between the cesium-containing region 12 and the range of about 3 nm.

In order to measure the activation rate of cesium as a donor in silicon, hole measurement was performed. The sample was prepared as follows. Cesium was ion-implanted at an acceleration energy of 100 keV into a 12 mm square sample in which 10 nm of SiO ₂ was formed on silicon. In that case, most of the cesium is distributed in the silicon. Next, P ions were implanted using a resist having openings at the four corners of the sample as a mask. Subsequently, after removing the resist, annealing was performed at 900 ° C. for 10 seconds to form an n ⁺ region, and damage caused by cesium ion implantation was recovered. Next, SiO ₂ on the four n ⁺ regions was opened using the lithography method and the RIE method, and subsequently, a Ti electrode was formed on each n ⁺ region using the lift-off method. Using this sample, hole measurement was performed by the Van der Pauw method. As a result, an electron surface density of 3.0 × 10 ¹² cm ⁻² was obtained. As a result of SIMS analysis, the amount of cesium contained in silicon was 1.7 × 10 ¹⁵ cm ⁻² . Therefore, the activation rate of cesium in silicon was a sufficiently low 0.18%. However, since cesium injected into SiO ₂ becomes a positive fixed charge and induces electron carriers in silicon, the activation rate of cesium in actual silicon as a donor is lower than 0.18%. It is thought that. Thus, it has been found that cesium hardly generates carriers in the bulk of silicon as a semiconductor.

Here, normally, the P-type impurity concentration in the vicinity of the channel is 1 × 10 ¹⁸ cm ⁻³ or more. Therefore, if the activation rate is 0.2% or less, if the concentration of cesium in the cesium-containing region 12 is 5 × 10 ²⁰ cm ⁻³ or less, the concentration of cesium as a donor is 1 × 10 ¹⁸ cm ^{−. 3} (= 5 × 10 ²⁰ cm ⁻³ × 0.002) or less, which is lower than the P-type impurity concentration of 1 × 10 ¹⁸ cm ⁻³ or more. Therefore, since the cesium-containing region 12 becomes an N-type region and the source / drain junction depth does not increase, the short channel effect characteristic does not deteriorate. In addition, if the cesium concentration at the interface between the metal source / drain electrode and the semiconductor is 1 × 10 ¹⁹ cm ⁻³ or more, a sufficient Schottky barrier modulation effect can be obtained. Therefore, the above cesium concentration is 5 × 10 ²⁰ cm ^−3. The value is sufficiently large. That is, by setting the impurity activation rate to 0.2% or less, a very wide process margin can be obtained.

As a result, the energy barrier height against holes in the diode shown in FIG. 5 is represented by φ _b ^h (Cs) in FIG. 5, and the reverse bias current I _rp (Cs) is represented by the following formula (2). .

As can be seen from FIG. 5, since φ _b ^h (Cs)> φ _b ^h , I _rp (Cs) << I _rp . In the case of many metal silicides, φ _b ^h is about 0.4 eV to 0.5 eV, whereas φ _b ^h (Cs) can be increased up to about 1.1 eV of silicon band gap. The reverse bias current is significantly reduced.

  Thus, the reverse bias current can be remarkably reduced by having the cesium-containing region in the semiconductor at the interface between the metal and the semiconductor.

  2 is the same as the band diagram of FIG. 5 in the semiconductor device shown in FIG.

  Next, a diode manufactured by using N-type silicon instead of P-type silicon 11 with the same structure as the diode shown in FIG. 3 will be described.

  FIG. 7 shows current-voltage characteristics of the diode using the N-type silicon. FIG. 7 also shows current-voltage characteristics when there is no cesium-containing region. As can be seen from FIG. 7, when the cesium-containing region is included, the reverse bias current is remarkably increased as compared with the case where the cesium-containing region is not provided. This indicates that the resistance between nickel silicide and N-type silicon is reduced by forming the cesium-containing region. This indicates that the resistance between the metal source / drain electrode 6 and the channel can be reduced in the source / drain structure shown in FIG.

  Hereinafter, this reason will be described with reference to FIGS.

  FIG. 8 and FIG. 9 are band diagrams in the CC ′ section of a diode using N-type silicon instead of P-type silicon 11 in FIG. However, FIG. 9 is a band diagram in the case where the cesium-containing region 12 does not exist.

ここで、φ_ｂ ^ｅ：電子に対するショットキー障壁高さ、ｋ_Ｂ：ボルツマン定数、Ｔ：絶対温度である。尚、φ_ｂ ^ｅはＮ型シリコンの伝導帯下端とニッケルシリサイド１３のフェルミ準位とのエネルギー差である。 Since the diode shown in FIG. 9 is a Schottky barrier diode, the reverse bias current I _rn is expressed by the following formula (3).

Here, φ _b ^e : Schottky barrier height for electrons, k _B : Boltzmann constant, and T: absolute temperature. Incidentally, phi _b ^e is the energy difference between the Fermi level of the conduction band and the nickel silicide 13 of N-type silicon.

In FIG. 8, the ionization potential of cesium is 3.89 eV, whereas the electron affinity of silicon is 4.05 eV. Therefore, cesium forms an energy level on the higher energy side than the lower end of the conduction band of silicon. It is considered a thing. In this case, electrons are emitted from the energy level produced by cesium to the nickel silicide side, and cesium is positively ionized. In the region where cesium is ionized, the silicon band is greatly depressed in accordance with the density of cesium. That is, when the density of the cesium is sufficiently large, to the lowest point of the bottom of the conduction band E _C ^Si of the silicon is substantially coincident with the Fermi level E _F ^M nickel silicide 13, silicon band is bent.

  On the other hand, since cesium does not activate as a donor for silicon, cesium at a position away from the nickel silicide 13 in the cesium-containing region 12 remains neutral. In addition, since emission of electrons from cesium at a position away from the interface with the N-type silicon in the cesium-containing region 12 to the nickel silicide 13 is mainly caused by a tunnel effect, the cesium is ionized by the nickel silicide 13 It is limited to a range of about 3 nm from the interface with the cesium-containing region 12.

As a result, the width of the Schottky barrier becomes very thin, and further, due to the reduction of the Schottky barrier height due to the mirror image effect, electrical conduction between the nickel silicide 13-P type silicon 11 is mainly caused by the tunnel current. . Accordingly, as shown in FIG. 8, the energy barrier height for electrons φ _b ^e (Cs) is a energy difference between the Fermi level E _F ^M of the conduction band of the silicon bottom E _C ^Si and nickel silicide 13. In this case, the reverse bias current I _rn (Cs) is expressed by the following formula (4).

As can be seen from FIG. 8, since it is ^{_{φ b e (Cs) << φ}} b e, the _{I rn (Cs) >> I rn} . Since φ _b ^e (Cs) is a very small value of the energy difference between the bottom conduction band E _C ^Si of silicon and the Fermi level E _F ^{Si of silicon} , as shown in FIG. Current-voltage characteristics can be obtained. In the structure of the semiconductor device shown in FIG. 2, since the channel in the on state can be regarded as an N-type region having a high electron density, the channel-source / drain can be connected with a low resistance by having the cesium-containing region 12. I understand that.

  Hereinafter, the channel-source-drain resistance in the semiconductor device shown in FIG. 2 will be considered with reference to FIGS.

  10 and 11 are band diagrams at the BB ′ section in FIG. However, FIG. 11 is a band diagram in the case where the cesium-containing region 5 does not exist (Schottky junction transistor).

  As shown in FIG. 11, by applying a voltage to the gate electrode 3, the silicon band is bent and an inversion layer is formed in the channel region. As a result, the thickness of the Schottky barrier is reduced, and the height of the Schottky barrier for electrons is reduced due to the mirror image effect, so that a tunnel current can flow.

  On the other hand, in FIG. 10 where the cesium-containing region 5 exists, the silicon band is bent by applying a voltage to the gate electrode 3, and an inversion layer is formed in the channel region. In at least a region close to the source in the cesium-containing region 5, cesium is positively ionized by emitting electrons to the source side. As a result, as can be seen from comparison with FIG. 11, in the region where cesium is ionized, the band of silicon is further bent, and the inclination becomes very steep. As a result, the Schottky barrier thickness becomes very thin, and in addition, the Schottky barrier height for electrons is greatly reduced by the mirror image effect, so that the tunnel current between the source and the channel becomes remarkably large.

  As described above, in the semiconductor device shown in FIG. 2, by having the cesium-containing region 5, the resistance between the channel, the source, and the drain can be significantly reduced, and a large on-current can be obtained.

  As described above, according to the semiconductor device of the present embodiment, cesium as an impurity that modulates the Schottky barrier is interposed between the metal source / drain electrode (nickel silicide) 6 and the semiconductor (P-type silicon substrate 1). The cesium containing area | region 5 to contain is formed. Accordingly, ionization of cesium in the vicinity of the metal source / drain electrode 6 increases the height of the energy barrier against holes, and the metal source / drain electrode 6 and the P-type silicon substrate 1 as compared with the Schottky junction. Leakage current between the two can be significantly reduced. In addition, since the Schottky barrier height between the channel and the metal source / drain electrode 6 is effectively reduced and the Schottky barrier thickness is reduced, the parasitic resistance is significantly reduced compared to the Schottky junction. It can be done.

  The metal source / drain electrode (nickel silicide 6) may contain a part of cesium as an impurity that modulates the Schottky barrier between the semiconductor and the metal source / drain electrode. In this case, since the work function of cesium (1.93 eV) is larger than that of nickel silicide (NiSi) (4.9 eV), the work function of the metal source / drain electrodes is reduced, and the Schottky barrier height against electrons is increased. Can be further reduced.

  In addition, since cesium is not a silicon donor and acceptor (that is, almost no carriers are generated in the bulk of silicon), in the cesium-containing region 5, the cesium is sufficiently separated from the metal source / drain electrode 6. It does not ionize by emitting electrons as carriers. Therefore, it is not necessary to extremely reduce the thickness of the cesium-containing region 5 in advance considering that the region functioning as the source / drain expands due to impurity diffusion or the like. That is, there are no special restrictions on the conditions for ion implantation of cesium. Therefore, in order to reduce the thickness of the cesium-containing region 5, it is not necessary to use an impurity segregation technique as disclosed in Patent Document 1.

  Further, since the cesium-containing region 5 does not induce carriers, the short channel effect characteristic is not deteriorated even if the cesium-containing region 5 is formed deeper than the metal source / drain electrode 6. That is, since the metal source / drain electrode 6 can be formed in a region shallower than the ion implantation depth of impurities (cesium), an extremely shallow source / drain can be formed. Therefore, good short channel effect characteristics can be obtained.

  The cesium has an ionization potential (3.89 eV) smaller than the electron affinity (4.05 eV) of silicon. Therefore, cesium forms an impurity level on the higher energy side than the lower end of the conduction band of silicon, and emits electrons from the impurity level to the metal source / drain electrode 6 side, thereby positively ionizing and cesium. Bend the energy band. Thus, the energy band of silicon is bent to such an extent that the impurity level matches the Fermi level of the metal source / drain electrode. Therefore, the Schottky barrier can be greatly modulated, and as described above, the leakage current between the P-type silicon substrate 1 and the metal source / drain electrode 6 can be remarkably suppressed, and between the channel and the metal source / drain electrode 6. The resistance can be significantly reduced.

Further, since the cesium concentration in the cesium-containing region 12 at the position in contact with the nickel silicide 13 in FIG. 3 was 1 × 10 ¹⁹ cm ⁻³ , the interface between the metal source / drain electrode 6 and the P-type silicon substrate 1 was used. By setting the cesium concentration to 1 × 10 ¹⁹ cm ⁻³ or more, the Schottky barrier can be greatly modulated. Therefore, the leakage current between the P-type silicon substrate 1 and the metal source / drain electrode 6 can be remarkably suppressed, and the resistance between the channel-metal source / drain electrode 6 can be remarkably reduced.

  The cesium is distributed so as to have a concentration peak at a position deeper than the interface between the metal source / drain electrode 6 and the P-type silicon substrate 1. Therefore, a wide range of the metal source / drain electrode 6 can be covered with the high-concentration impurity region, and the leakage current can be effectively reduced.

  The metal source / drain electrodes 6 are made of nickel silicide, which is a compound of silicon as the semiconductor and nickel as the metal. Therefore, the shallow metal source / drain electrodes 6 can be easily formed by reducing the thickness of the deposited nickel.

  The semiconductor contains at least one of silicon and germanium as a main component, and the metal contains one or more elements of Ni, Co, Ti, Er, Yb, and Pt. Therefore, the gate electrode 3 can be made of polycrystalline silicon, amorphous silicon, germanium, silicon containing germanium, or the like, and the shallow metal source / drain electrode 6 can be easily positioned in a self-aligned position with respect to the gate electrode 3. Can be formed.

  As described above, according to the present embodiment, the height and width of the Schottky barrier can be easily controlled regardless of the type of the metal material, the parasitic resistance is low, and the short channel effect can be effectively suppressed. It is possible to provide a semiconductor device and a manufacturing method thereof.

(Second embodiment)
FIG. 12 is a cross-sectional view during each manufacturing process of the semiconductor device of the second embodiment.

  First, an element isolation region (not shown) is formed on one main surface of a P-type silicon substrate 21 as an example of a semiconductor by a known method such as the STI method, and the element formation region is formed by the element isolation region. Break down.

  Next, as shown in FIG. 12A, a gate insulating film 22 made of silicon oxide is formed on the surface of the element formation region by using a thermal oxidation method, a CVD method, an ALD method, or the like, and then Then, an N-type polycrystalline silicon film is deposited on the gate insulating film 22 using a CVD method or the like. Next, the gate electrode 23 is formed by patterning the polycrystalline silicon film using a lithography method, an RIE method, or the like.

  As the material of the gate insulating film 22, silicon oxynitride, silicon nitride, hafnium oxide, lanthanum oxide, or a material containing nitrogen, silicon, aluminum, or the like may be used instead of silicon oxide. .

  Further, although polycrystalline silicon is used as the material of the gate electrode 23, amorphous silicon, germanium, silicon containing germanium, or the like may be used.

  Next, a silicon oxide film is deposited using the CVD method or the like, and then etched back by the RIE method to form the gate sidewall film 24. As a material for the gate sidewall film 24, silicon nitride, silicon oxynitride, or the like may be used instead of silicon oxide.

Next, as shown in FIG. 12B, donor impurities such as As are ion-implanted and annealed to form an N-type impurity region 25. The impurity concentration of the N-type impurity region 25 may be set to such a low concentration that it is not completely depleted even when a drain voltage is applied after the semiconductor device of the present embodiment is completed. By doing so, the leakage current can be further reduced without causing a large increase in parasitic capacitance. Alternatively, the impurity concentration of the N-type impurity region 25 may be a high concentration of 1 × 10 ²⁰ cm ⁻³ or more. In that case, the gate electrode 23 can be doped simultaneously with the doping of the N-type impurity region 25.

  Next, as shown in FIG. 12C, after the gate sidewall film 24 is removed by wet etching or the like using a hydrofluoric acid aqueous solution, silicon oxide is deposited by CVD or the like, and then etched back by RIE or the like. Thereby, the gate side wall 26 is formed. As the material of the gate sidewall 26, silicon oxynitride, silicon nitride, or the like may be used instead of silicon oxide.

Next, cesium-containing region 27 is formed by ion-implanting cesium, for example, under the conditions of an acceleration energy of 5 keV and a dose of 1 × 10 ¹⁴ cm ⁻² . The ion implantation conditions are not limited to the above conditions, but the cesium-containing region 27 is formed to a position deeper than the nickel silicide 28 (see FIG. 12D) formed in a later step. You only have to set it.

  Thereafter, annealing may be performed to recover the implantation damage. In that case, for example, RTA method, FLA method, laser annealing method or the like is used.

  Next, as shown in FIG. 12 (d), nickel is deposited by, for example, about 2 nm by sputtering or the like, and then annealed at 260 ° C. to 350 ° C. for 30 seconds to 200 seconds to be silicided. In that case, TiN may be deposited on nickel by sputtering or the like before the annealing. Thereafter, unreacted nickel (and TiN) is removed to form the nickel silicide 28 as an example of a metal source / drain electrode. Then, the resistance of the nickel silicide 28 is reduced by annealing under conditions of 350 ° C. to 500 ° C. and 30 seconds to 200 seconds. In this case, the nickel source / drain electrode (nickel silicide 28) (hereinafter also referred to as the metal source / drain electrode 28) may be in contact with the semiconductor (P-type silicon substrate 21) through the cesium-containing region 27. The silicide 28 is formed so that at least its thickness (depth) is thinner (shallow) than the cesium-containing region 27. The thickness of the nickel silicide 28 is about three times the thickness of the sputtered nickel film (for example, about 6 nm).

  The nickel silicide 28 functions as a source / drain.

  When the nickel silicide 28 is formed, the gate electrode 23 is also silicided to form a nickel silicide 29.

  In this case, the gate electrode 23 may be entirely silicided to have a metal gate structure. In the case of a metal gate structure, the polycrystalline silicon film may be either i-type or P-type.

  As an example of the metal source / drain electrodes, when cobalt silicide is formed instead of nickel silicide 28, cobalt is deposited by sputtering to about 3 nm, and then at 400 ° C. to 600 ° C. for 30 seconds to 200 seconds. Silicidation occurs by annealing. In that case, TiN may be deposited on cobalt by sputtering or the like before the annealing. Then, after removing unreacted cobalt (and TiN), the resistance of cobalt silicide may be reduced by annealing under conditions of 700 ° C. to 900 ° C. and 30 seconds to 200 seconds. Also in this case, the cobalt silicide is at least thinner than the cesium-containing region so that the metal source / drain electrodes (cobalt silicide) are in contact with the semiconductor (P-type silicon substrate 21) through the cesium-containing region 27. To form. The thickness of cobalt silicide is about twice the thickness of the sputtered cobalt (for example, about 6 nm).

  As described above, the case of nickel silicide 28 and cobalt silicide has been described as an example of the metal source / drain electrode. However, the metal source / drain electrode is not limited thereto. For example, metal silicide using a metal composed of one or more elements of Ni, Co, Ti, Er, Yb, and Pt may be used.

  Finally, an interlayer insulating film (not shown), an upper wiring (not shown), and the like are formed by a known method, thereby completing the semiconductor device.

  According to the semiconductor device of the present embodiment, since the cesium-containing region 27 is formed between the metal source / drain electrode (nickel silicide) 28 and the semiconductor (P-type silicon substrate 21), the metal source / drain electrode The ionization of cesium in the vicinity of 28 increases the height of the energy barrier against holes. As a result, the leakage current between the source / drain and the semiconductor can be significantly reduced as compared with the Schottky junction. it can. At the same time, the Schottky barrier height for the electrons between the channel and the source / drain is effectively reduced and the Schottky barrier thickness is reduced, which significantly reduces the parasitic resistance compared to a Schottky junction. It can be done.

  Further, since cesium is not a silicon donor and acceptor, cesium is not ionized in a region of the cesium-containing region 27 that is sufficiently away from the metal source / drain electrode 28. Therefore, there is no need to extremely reduce the thickness of the cesium-containing region 27 between the metal source / drain electrode 28 and the semiconductor (P-type silicon substrate 21) (that is, there is no restriction when cesium is ion-implanted). Therefore, it is not necessary to use an impurity segregation technique as disclosed in Patent Document 1.

  As described above, in the semiconductor device of the present embodiment, the thickness of the metal silicide (metal source / drain electrodes) can be determined without restriction by ion implantation, so that extremely shallow source / drains can be formed. The short channel effect can be suppressed very well.

  Further, since the N-type impurity region 25 having an impurity concentration that does not completely deplete is formed in contact with the source / drain located away from the channel region, the leakage current can be further increased without causing a large increase in parasitic capacitance. Can be reduced. Further, by forming a contact hole in the upper part of the N-type impurity region 25, excessive etching is performed due to etching variation at the time of forming the contact hole, and the upper electrode is directly connected to the P-type silicon substrate 21 through the nickel silicide 28. As a result, an increase in leakage current can be prevented. Therefore, since the nickel silicide 28 can be formed thinly, the short channel effect can be suppressed extremely well.

(Third embodiment)
In the third embodiment, the present invention is applied to a FET having a three-dimensional channel structure such as a Fin-FET (three-dimensional structure-FET (Field Effect Transistor)), a tri-gate-FET, and a nanowire-FET. It is an example.

  FIG. 13A to FIG. 15E are cross-sectional views during each manufacturing process of the semiconductor device of the third embodiment. A method for manufacturing the semiconductor device of the present embodiment will be described below with reference to FIGS. 13 (a) to 15 (e).

  First, as shown in FIG. 13A, for example, in an SOI substrate in which silicon 31, silicon oxide 32, and silicon as an SOI layer are stacked in this order, the SOI layer is patterned to form the alphabet “ An I-shaped semiconductor region 33 is formed. The thickness of the SOI layer (semiconductor region 33) is, for example, 20 nm. In addition, the width (Fin width) of a region that becomes a channel in the semiconductor region 33 is, for example, 10 nm.

  Next, as shown in FIG. 13B, a gate insulating film 34 made of silicon oxide is formed on the surface of the semiconductor region 33 by using a thermal oxidation method, a CVD method, an ALD method, or the like. Subsequently, an N-type polycrystalline silicon film is deposited on the gate insulating film 34 using a CVD method or the like. Next, the gate electrode 35 is formed by patterning the polycrystalline silicon film using a lithography method, an RIE method, or the like. Subsequently, the gate insulating film 34 in a region not covered with the gate electrode 35 is removed by wet etching or the like using a hydrofluoric acid aqueous solution.

  As the material of the gate insulating film 34, silicon oxynitride, silicon nitride, hafnium oxide, lanthanum oxide, or a material containing nitrogen, silicon, aluminum, or the like may be used instead of silicon oxide. .

  Further, although polycrystalline silicon is used as the material of the gate electrode 35, amorphous silicon, germanium, silicon containing germanium, or the like may be used.

  Next, as shown in FIG. 14C, a silicon oxide film is deposited using the CVD method or the like, and then etched back by the RIE method, thereby forming a gate sidewall film 36. As a material for the gate sidewall film 36, silicon nitride, silicon oxynitride, or the like may be used instead of silicon oxide.

Next, as shown in FIG. 14D, cesium-containing region 37 is formed by ion-implanting cesium, for example, under conditions of an acceleration energy of 5 keV and a dose of 1 × 10 ¹⁴ cm ⁻² . The ion implantation conditions are not limited to the above conditions, but may be set so that the cesium-containing region 37 extends at least to the boundary with the silicon oxide 32. However, when the semiconductor region 33 is amorphized over the entire thickness direction of the SOI layer by ion implantation, the amorphized region is polycrystallized by heat treatment in a later process, and leakage current and parasitic resistance are increased. Will increase. However, by selecting the acceleration energy so that the concentration peak of cesium (impurity that modulates the Schottky barrier) is located in a region shallower than the center in the thickness direction of the SOI layer, the semiconductor region 33 is in the thickness direction of the SOI layer. It is possible to prevent the entire region from being amorphous and to maintain the crystallinity of at least the semiconductor region 33 in the region in contact with the silicon oxide 32. In this case, solid phase growth of single crystal silicon is promoted by heat treatment in a later step, and the amorphous region can be single crystallized (implantation damage can be recovered).

  Thereafter, annealing may be performed to recover the implantation damage. In that case, for example, RTA method, FLA method laser annealing method or the like is used.

  Next, as shown in FIG. 15 (e), after depositing nickel, for example, about 3 nm to 4 nm by sputtering or the like, it is annealed and silicided at 260 ° C. to 350 ° C. for 30 seconds to 200 seconds. In that case, TiN may be deposited on nickel by sputtering or the like before the annealing. Thereafter, unreacted nickel (and TiN) is removed to form nickel silicide 38 as an example of a metal source / drain electrode. Thereafter, the nickel silicide 38 is lowered in resistance by annealing under conditions of 350 ° C. to 500 ° C. and 30 seconds to 200 seconds. In the present embodiment, the nickel silicide 38 is formed such that all silicon is nickel-silicided in the narrowest region (Fin region) of the semiconductor region 33. Nickel silicide 38 may be formed by nickel silicidation only on the surface portion 33 (in this case, the cross-sectional view taken along the line DD ′ in FIG. 15E is FIG. 18 instead of FIG. 16). Further, the entire semiconductor region 33 excluding the channel region may be nickel-silicided (in this case, the sectional view taken along the line DD ′ in FIG. 15E is FIG. 19 instead of FIG. 16). In any case, cesium ion implantation is performed so that the metal source / drain electrode (nickel silicide 38) (hereinafter also referred to as the metal source / drain electrode 38) is in contact with the semiconductor region 33 through the cesium-containing region 37. The conditions and the formation conditions of the nickel silicide 38 may be determined. The thickness of the nickel silicide 38 is about three times the thickness of the sputtered nickel film (for example, about 9 nm to 12 nm).

  The nickel silicide 38 functions as a source / drain.

  When the nickel silicide 38 is formed, the gate electrode 35 is also silicided to form a nickel silicide 39.

  In this case, the gate electrode 35 may be entirely silicided to have a metal gate structure. In the case of a metal gate structure, the polycrystalline silicon film may be either i-type or P-type.

  As an example of the metal source / drain electrodes, in the case where cobalt silicide is formed instead of nickel silicide 38, cobalt is deposited to a thickness of about 5 nm by sputtering or the like, and then at 400 ° C. to 600 ° C. for 30 seconds to 200 seconds. Silicidation occurs by annealing. In that case, TiN may be deposited on cobalt by sputtering or the like before the annealing. Then, after removing unreacted cobalt (and TiN), the resistance of cobalt silicide may be reduced by annealing at 700 ° C. to 900 ° C. for 30 seconds to 200 seconds. Also in this case, the metal source / drain electrodes (cobalt silicide) are formed so as to be in contact with the semiconductor (semiconductor region 33) through the cesium-containing region 37. The thickness of the cobalt silicide is about twice the thickness of the sputtered cobalt (for example, about 10 nm).

  As described above, the case of nickel silicide 38 and cobalt silicide has been described as an example of the metal source / drain electrode. However, the metal source / drain electrode is not limited thereto. For example, metal silicide using a metal composed of one or more elements of Ni, Co, Ti, Er, Yb, and Pt may be used.

  Finally, an interlayer insulating film (not shown), an upper wiring (not shown), and the like are formed by a known method, thereby completing the semiconductor device. FIG. 16 is a cross-sectional view taken along the line DD ′ of FIG. FIG. 17 is a cross-sectional view taken along the line EE ′ of FIG.

  According to the semiconductor device of the present embodiment, the cesium-containing region 37 is formed between the metal source / drain electrode (nickel silicide) 38 and the semiconductor (semiconductor region 33). As a result of the ionization of cesium, the energy barrier height against holes is increased, and as a result, the leakage current between the source / drain and the semiconductor can be significantly reduced as compared with the Schottky junction. At the same time, the Schottky barrier height for the electrons between the channel and the source / drain is effectively reduced, and the Schottky barrier thickness is reduced. It can be reduced.

  In addition, since cesium is not a silicon donor and acceptor, cesium is not ionized in a region sufficiently separated from the metal source / drain electrode 38 in the cesium-containing region 37. Therefore, there is no need to extremely reduce the thickness of the cesium-containing region 37 between the metal source / drain electrode 38 and the semiconductor (semiconductor region 33) (that is, there is no restriction when ion-implanting cesium). It is not necessary to use an impurity segregation technique as disclosed in Patent Document 1.

  As described above, according to the semiconductor device in this embodiment, since the short channel effect characteristic is not deteriorated due to the diffusion of the donor impurity, an extremely good short channel effect characteristic can be obtained even in the three-dimensional channel structure FET. It is.

  Note that when a planar transistor is formed using an SOI substrate, the same cross-sectional structure as that in FIG. 19 is obtained.

  In each of the above embodiments, the cesium-containing regions 5, 27, 37 are in contact with the metal source / drain electrodes 6, 28, 38 in the P-type silicon substrates 1, 21 and the semiconductor (silicon) region 33. It is formed in the whole area. However, the present invention is not limited to all of the “contact region”, and the same effect can be obtained even if it is formed on a part of the “contact region”.

1,21 ... P-type silicon substrate,
2, 22, 34 ... gate insulating film,
3, 23, 35 ... gate electrode,
4, 24, 36 ... gate sidewall film,
5, 12, 27, 37 ... cesium-containing region,
6, 13, 28, 38 ... nickel silicide (metal source / drain electrodes),
7, 29, 39 ... Nickel silicide of the gate electrode,
11 ... P-type silicon,
25 ... N-type impurity region,
26 ... Gate side wall,
31 ... Silicon,
32 ... silicon oxide,
33: Semiconductor region.

Claims (14)

Semiconductors,
A gate electrode formed on the semiconductor via a gate insulating film;
Metal source / drain electrodes formed on both sides of the gate electrode on the semiconductor,
In part or all of the region in contact with the metal source / drain electrode in the semiconductor has an impurity-containing region containing an impurity that modulates a Schottky barrier,
The semiconductor device, wherein the impurity is an impurity that hardly generates carriers in the bulk of the semiconductor. The semiconductor device according to claim 1,
In addition to part or all of the region in contact with the metal source / drain electrode in the semiconductor, the impurity is in a region including part or all of the region in contact with the semiconductor in the metal source / drain electrode. Is also included,
A semiconductor device, wherein a work function of the impurity is smaller than a work function of the metal source / drain electrode. The semiconductor device according to claim 1,
In addition to part or all of the region in contact with the metal source / drain electrode in the semiconductor, the impurity is in a region including part or all of the region in contact with the semiconductor in the metal source / drain electrode. Is also included,
A semiconductor device, wherein a work function of the impurity is larger than a work function of the metal source / drain electrode. In the semiconductor device according to any one of claims 1 to 3,
A semiconductor device, wherein the mass number of the impurity is greater than 75. The semiconductor device according to any one of claims 1, 2, and 4,
The semiconductor device, wherein the impurity has an ionization potential smaller than an electron affinity of the semiconductor. In the semiconductor device according to any one of claims 1, 2, 4, and 5,
The semiconductor device is characterized in that the impurity is cesium. In the semiconductor device according to any one of claims 1 to 6,
A semiconductor device, wherein the impurity concentration at the interface between the impurity-containing region and the metal source / drain electrode is 1 × 10 ¹⁹ cm ⁻³ or more. The semiconductor device according to any one of claims 1 to 7,
A concentration of the impurity in the impurity-containing region has a peak at a position deeper than an interface between the impurity-containing region and the metal source / drain electrode. The semiconductor device according to any one of claims 1 to 8,
The metal source / drain electrode is composed of a compound of the semiconductor and metal. The semiconductor device according to claim 9.
The semiconductor contains at least one of silicon and germanium as a main component,
A semiconductor device characterized in that the metal contains one or more elements selected from the group consisting of nickel, cobalt, titanium, erbium, ytterbium and platinum. In the semiconductor device according to any one of claims 1 to 10,
The semiconductor is provided on an insulator,
At least a part of the metal source / drain electrode is in contact with the insulator. A method of manufacturing a semiconductor device according to claim 1,
Forming a gate electrode on a semiconductor via a gate insulating film;
Introducing the impurity on both sides of the gate electrode in the upper part of the semiconductor to form the impurity-containing region;
Depositing a metal on the impurity-containing region in the semiconductor;
Forming a metal source / drain electrode on both sides of the gate electrode in the upper part of the semiconductor by reacting the semiconductor with the metal by annealing; and
A method of manufacturing a semiconductor device, wherein the impurity-containing region is formed in a part or all of a region in contact with the metal source / drain electrode in the semiconductor. In the manufacturing method of the semiconductor device according to claim 12,
The method for manufacturing a semiconductor device, wherein the impurity is cesium. In the manufacturing method of the semiconductor device according to claim 12 or 13,
The semiconductor contains at least one of silicon and germanium as a main component,
The method for manufacturing a semiconductor device, wherein the metal includes one or more elements selected from the group consisting of nickel, cobalt, titanium, erbium, ytterbium, and platinum.

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