JP2014036215A - Semiconductor device and method for manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device capable of easily controlling a height and a width of a schottky barrier regardless of the kind of metal material and having low parasitic resistance, and a method for manufacturing the same.SOLUTION: A gate electrode 3 is formed on a p-type silicon substrate 1 via a gate insulating film 2, a first metal source drain electrode 6a is formed at one side of the gate electrode 3 on the p-type silicon substrate 1, and a second metal source drain electrode 6b is formed at other side of the gate electrode 3 on the p-type silicon. Insulating gate side wall films 4a and 4b are provided on side surfaces of the gate electrode 3, and cesium-containing regions 5a and 5b containing cesium are formed on a part or whole of a region contacting with the first and the second metal source drain electrodes 6a and 6b, on the p-type silicon substrate 1. Fixed charges exist in the gate side wall films 4a and 4b.

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof.

  Semiconductor integrated circuits have been improved in performance by miniaturization of MOSFETs (MOS field effect transistors). Here, in order to continue miniaturization of MOSFETs in the future, it is indispensable to suppress characteristic deterioration due to the short channel effect that becomes more prominent with miniaturization. Here, in order to suppress the short channel effect, it is very effective to form the source / drain shallower. At the same time, in order to obtain a high on-current, the source and drain need to have a low resistance.

  Usually, the source / drain is formed by ion-implanting a high-concentration donor or acceptor into the semiconductor layer, followed by activation annealing. In order to reduce the junction depth of the source / drain formed in this way, it is necessary to reduce ion implantation energy (acceleration energy). However, if the ion implantation energy is extremely small (for example, 1 keV or less), it becomes difficult to secure a sufficient dose per unit time, and mass production becomes very difficult. In addition, there is a problem that the junction depth becomes deep due to thermal diffusion of impurities by activation annealing. On the other hand, as the junction depth is reduced, the source / drain resistance increases. For these reasons, shallow source / drain junctions have become increasingly difficult in recent years.

  As a method for solving such a problem, a metal source / drain structure in which a source / drain is formed using a metal such as metal silicide has been proposed (for example, Non-Patent Document 1). The metal silicide is formed by depositing a metal on silicon as a semiconductor and then performing heat treatment such as RTA (Rapid Thermal Annealing). The film thickness of such a metal silicide can be controlled by the film thickness of the deposited metal, and therefore can be easily controlled. Therefore, a very shallow source / drain can be easily formed. In addition, since the source and drain are made of metal, it is expected that the resistance can be very low.

  However, in the metal source / drain structure, a Schottky junction is formed between the metal and the semiconductor, so that a leakage current between the source / drain and the semiconductor is large, and between the channel and the source / drain. Due to the formed Schottky barrier, there is a problem that the on-current is reduced.

  In order to solve such a problem, Japanese Patent Application Laid-Open No. 2005-101588 (Patent Document 1) discloses a technique in which impurities such as As and B are implanted into a silicon substrate as a semiconductor layer, and then the region where the impurities are implanted. By forming a metal silicide (metal source / drain) to a deeper region, impurities are segregated near the interface between the metal silicide and silicon, and the region in contact with the metal silicide has a conductivity type opposite to that of the silicon substrate and is depleted. A technique for forming a doped impurity-containing region is disclosed.

  In the field effect transistor disclosed in Patent Document 1, the junction characteristics between the metal source / drain and the semiconductor are in an intermediate state between the pn junction and the Schottky junction. Leakage current can be suppressed. In addition, compared to the case of Non-Patent Document 1, the height of the Schottky barrier formed between the channel and the source / drain is effectively reduced, so that the on-current can be increased.

  However, in the technique disclosed in Patent Document 1, it is necessary to form the metal silicide up to a position deeper than the region into which the impurity is implanted. Therefore, the depth of the source and drain may be made shallower than the impurity implantation depth. Can not. That is, there is a problem that it is impossible in principle to form a source / drain shallower than the conventional method of forming a source / drain using a pn junction.

  In addition, since the impurities used are semiconductor donor impurities or acceptor impurities, the impurities are thermally diffused when heat treatment is performed to recover crystal defects caused by impurity activation or ion implantation after the impurities are implanted. Resulting in. Therefore, there is a problem that it becomes more difficult to form a shallow source / drain.

  In recent LSI manufacturing, a large-diameter semiconductor wafer is used. In this case, for example, a sputtering method is used to form a metal silicide (metal source / drain) by a SALICIDE (Self-Aligned Silicide) process. When the metal film is deposited by the above method, the incident angle of the metal particles flying from the sputter target is increased particularly in the peripheral part of the wafer, so that the gate electrode becomes a shadow, and the film thickness of the deposited metal is reduced in the region near the gate electrode. It tends to be thinner than the target value. When silicidation is performed in such a state, in the region where the metal film thickness is thin, the metal silicide film thickness becomes thinner than the target value, so that the lateral growth is shortened and the metal silicide (one of the metal source / drain electrodes) Is offset with respect to the gate electrode.

JP 2005-101588 A

See Wang, John P. Snyder, J. P. Snyder, JRTucker, "Applied Physics Letters", American Institute of the United States・ Physics (American Institute of Physics), Volume 74 (VOL.74), 1999, P.1174-1176

  Accordingly, an object of the present invention is to provide a semiconductor device capable of easily controlling the height and width of a Schottky barrier regardless of the type of metal material, having a low parasitic resistance, and effectively suppressing the short channel effect, and its semiconductor device It is to provide a manufacturing method.

In order to solve the above problems, a semiconductor device of the present invention is
A semiconductor layer;
A gate electrode formed on the semiconductor layer via a gate insulating film;
A first metal source / drain electrode formed on the semiconductor layer and on one side of the gate electrode;
A second metal source / drain electrode formed on the semiconductor layer and on the other side of the gate electrode;
An insulating gate sidewall film provided on the side surface of the gate electrode,
A part or all of the region in contact with the first and second metal source / drain electrodes in the semiconductor layer is a cesium-containing region containing cesium,
A positive fixed charge is present in the gate sidewall film.

  According to the present invention, the semiconductor layer has a cesium-containing region containing cesium in part or all of the region in contact with the metal source / drain electrode. Here, since the ionization potential of cesium is the lowest among all elements, the energy level (impurity level) formed by cesium in the cesium-containing region is higher than the Fermi level of the metal source / drain electrode. Will be located. As a result, electrons are emitted from the cesium to the metal source / drain electrode side, and the cesium is positively ionized. In the cesium ionized region, the Schottky barrier at the interface between the metal source / drain electrode and the cesium-containing region is greatly modulated (Schottky barrier modulation effect). That is, the Schottky barrier height with respect to holes increases effectively and the Schottky barrier height with respect to electrons decreases effectively. Therefore, in the N-type MOSFET, the leakage current between the semiconductor layer and the metal source / drain electrode can be remarkably suppressed, and the resistance between the channel and the metal source / drain electrode can be remarkably reduced.

  Band bending occurs to the extent that the impurity level at a position sufficiently far from the metal source / drain electrode matches the Fermi level of the metal source / drain electrode. Therefore, as the energy difference from the Fermi level to the impurity level of the metal source / drain electrode increases, the band bending increases and the Schottky barrier modulation effect increases. Since cesium has the smallest ionization potential (3.89 eV) among all elements, the use of cesium can most effectively exhibit the Schottky barrier modulation effect.

  Further, since the gate sidewall film contains a positive fixed charge, even if at least one of the metal source / drain electrodes is offset with respect to the gate electrode due to process variation or the like, the gate sidewall film includes the fixed charge below the gate sidewall film. Since the electron carrier layer is induced on the surface of the semiconductor layer, the channel region under the gate electrode and the metal source / drain electrode are ohmically connected through the electron carrier layer, and an increase in parasitic resistance can be prevented. Thereby, the yield can be dramatically improved. Since the electron carrier layer is extremely thin, the short channel effect characteristic is not deteriorated.

In one embodiment,
The semiconductor layer is made of a semiconductor having an electron affinity greater than 3.89 eV.

  According to the embodiment, since the electron affinity of the semiconductor layer is larger than the ionization energy (3.89 eV) of cesium, the impurity level produced by cesium in the cesium-containing region is lower than the lower end of the conduction band of the semiconductor layer. It can be located on the high energy side. Therefore, the energy band of the semiconductor layer in the vicinity of the metal source / drain electrode is bent to the extent that the lower end of the conduction band of the semiconductor layer matches the Fermi level of the metal source / drain electrode, so that almost maximum band bending can be obtained. it can. In addition, since the band bending in the region where cesium is ionized becomes very steep, the thickness of the Schottky barrier against electrons between the first and second metal source / drain electrodes and the semiconductor layer becomes very thin, Furthermore, since the effect of reducing the Schottky barrier height due to the mirror image effect becomes significant, the Schottky barrier height for electrons is effectively very small. Therefore, it is possible to connect the channel and the metal source / drain electrode with a very low resistance. At the same time, since the energy barrier height against holes becomes very large, the leakage current between the metal source and drain semiconductor layers can be remarkably suppressed.

In one embodiment,
The semiconductor layer is made of any one of silicon, germanium, silicon germanium, gallium arsenide, and gallium nitride.

  The electron affinity of silicon, germanium, silicon germanium, gallium arsenide, and gallium nitride is 4.05 eV, 4.0 eV, 4.0 eV, 4.07 eV, and 4.1 eV, respectively. Therefore, according to the embodiment, the electron affinity of the semiconductor layer can be made larger than 3.89 eV.

  Further, since cesium is not a silicon donor or acceptor, carriers are hardly generated in the bulk of the semiconductor layer. Therefore, even when the cesium-containing region is formed deeper than the first and second metal source / drain electrodes, the short channel effect characteristic is not deteriorated and the source is formed in a region shallower than the cesium implantation depth. A drain can be formed, and a very shallow source / drain can be formed. Therefore, good short channel effect characteristics can be obtained.

  In addition, when ion implantation is used to form the cesium-containing region, the mass number of cesium (133) is very large and is larger than the mass number of normal donor impurities (for example, the arsenic room rainfall number is 75). Thus, ions can be implanted into a region shallower than arsenic at the same ion implantation energy. In other words, when ion implantation is performed at the same depth, the ion implantation energy of cesium can be made larger than that of arsenic, so that the amount of ion current can be increased and the process time can be shortened. . In particular, when ion implantation is performed with very small ion implantation energy, a problem that a sufficient dose cannot be secured can be avoided.

In one embodiment,
At least a part of the fixed charge is cesium.

  Since cesium has the lowest ionization potential (3.89 eV) among all elements, it can form a high-density fixed charge most easily.

  In addition, a semiconductor having an electron affinity of less than 3.89 eV (eg, silicon, germanium, GaAs, GaN, etc .; the electron affinity is 4.05 eV, 4.0 eV, 4.07 eV, 4.1 eV, respectively) is used as the semiconductor layer. When used, cesium forms an energy level (impurity level) on the higher energy side than the lower end of the conduction band of the semiconductor layer, so that a higher-density fixed charge can be formed. For this reason, even when the metal source / drain electrode is offset from the gate electrode, a high-concentration electron carrier layer can be induced on the surface of the semiconductor layer, so that an increase in parasitic resistance can be remarkably suppressed. . As a result of charge transfer between the impurity level and the semiconductor layer, band bending occurs to the extent that the impurity level and the Fermi level coincide with each other on the surface of the semiconductor layer. If the electron carrier concentration increases and the impurity level is on the higher energy side than the lower end of the conduction band of the semiconductor layer, the surface of the semiconductor layer can be strongly inverted, and an extremely high concentration electron carrier layer can be formed. Can be formed.

In one embodiment,
The gate insulating film contains a nitrogen element.

  According to the embodiment, it is possible to easily form a fixed charge in the gate sidewall film. For example, in silicon nitride, a higher density positive fixed charge can be formed as the refractive index is higher than 1.9, and a higher density negative fixed charge can be formed as the refractive index is lower than 1.9.

In one embodiment,
The concentration of the cesium at the interface between the first metal source / drain electrode and the second metal source / drain electrode in the cesium-containing region is 1 × 10 ¹⁹ cm ⁻³ or more.

  According to the embodiment, the concentration of cesium at the interface between the first metal source / drain electrode and the second metal source / drain electrode in the cesium-containing region is sufficiently high. Therefore, the Schottky barrier is greatly modulated, the leakage current between the semiconductor layer and the first and second metal source / drain electrodes is remarkably suppressed, and the resistance between the channel and the first and second metal source / drain electrodes is significantly reduced. Is done.

In one embodiment,
The concentration of the cesium in the cesium-containing region has a peak at a position deeper than the interface between the first metal source / drain electrode and the second metal source / drain electrode in the cesium-containing region.

  According to the above embodiment, since the wide range of the first and second metal source / drain electrodes can be covered with the high concentration cesium-containing region, the leakage current between the semiconductor layer and the first and second metal source / drain electrodes can be reduced. Furthermore, it can reduce effectively.

In one embodiment,
Each of the first metal source / drain electrode and the second metal source / drain electrode is composed of a compound of the semiconductor layer and a metal.

  The depth of the first and second metal source / drain electrodes can be controlled by the thickness of the metal deposited on the semiconductor layer. According to the embodiment, a shallow metal source / drain electrode can be easily formed by thinly depositing the metal on the semiconductor layer by sputtering or the like.

In one embodiment,
The semiconductor layer includes at least one of silicon and germanium,
The metal includes one or more of nickel, cobalt, titanium, erbium and ytterbium.

  According to the above embodiment, since a self-aligned silicide process or a self-aligned germanide process can be used, a shallow metal source / drain electrode can be easily formed in a self-aligned position with respect to the gate electrode. .

In one embodiment,
The semiconductor layer is provided on an insulator,
At least a part of the first metal source / drain electrode and the second metal source / drain electrode is in contact with the insulator.

  According to the embodiment, in the semiconductor device having an SOI (Semiconductor On Insulator) structure, the leakage current between the semiconductor layer and the first and second metal source / drain electrodes can be remarkably suppressed, and the channel and the first and second metal sources. The resistance between the drain electrodes can be significantly reduced. Furthermore, it is possible to form a very shallow source / drain and obtain good short channel effect characteristics.

In addition, a method for manufacturing a semiconductor device of the present invention includes:
A manufacturing method of a semiconductor device for manufacturing a semiconductor device of the present invention,
Forming a gate electrode on the semiconductor layer via a gate insulating film;
Forming an insulating layer on the surface of the semiconductor layer and on both sides of the gate electrode;
Introducing cesium into the insulating layer;
Anisotropically etching the insulating layer so that part of the surface of the semiconductor layer is exposed to form a gate sidewall film made of the insulating layer;
Introducing cesium into a region where the surface of the semiconductor layer is exposed to form a cesium-containing region;
Forming the first and second metal source / drain electrodes so as to be in contact with the cesium-containing region.

  According to the present invention, a cesium-containing region containing cesium that modulates the Schottky barrier can be formed in part or all of the region in contact with the first and second metal source / drain electrodes in the semiconductor layer. Therefore, it is possible to form a semiconductor device that can significantly suppress the leakage current between the semiconductor layer and the first and second metal source / drain electrodes and can significantly reduce the resistance between the channel and the first and second metal source / drain electrodes.

  Further, according to the present invention, positive fixed charges can be formed in the vicinity of the interface between the insulating layer and the semiconductor layer by segregating cesium to the interface between the insulating layer and the semiconductor layer by annealing or the like. Therefore, on the surface of the semiconductor layer under a fixed charge, a carrier layer having a polarity opposite to the polarity of the fixed charge (in the case of an N-type MOSFET, the polarity of the fixed charge is positive, in the case of a carrier, in the case of a P-type MOSFET, the polarity of the fixed charge) Can induce holes), and can function as a very shallow source / drain extension. Therefore, very good short channel effect characteristics can be obtained.

  Moreover, due to the strong electric field effect due to the fixed charge, the Schottky barrier thickness with respect to carriers between the semiconductor layer and the first and second metal source / drain electrodes is remarkably reduced, and further, the reduction of the Schottky barrier height is promoted by the mirror image effect. Therefore, the effective Schottky barrier height is significantly reduced, and a low resistance connection between the carrier layer and the first and second metal source / drain electrodes is realized. Therefore, good short channel effect characteristics and low parasitic resistance can be realized at the same time.

In addition, a method for manufacturing a semiconductor device of the present invention includes:
A manufacturing method of a semiconductor device for manufacturing a semiconductor device of the present invention,
Forming a gate electrode on the semiconductor layer via a gate insulating film;
At least a region adjacent to the gate electrode on the surface of the semiconductor layer is exposed to an atmosphere containing at least one of a gas containing an oxidant composed of molecules containing nitrogen, nitrogen radicals, and nitrogen elements in a plasma state. Forming an insulating layer and forming a positive fixed charge;
Anisotropically etching the insulating layer such that a part of the surface of the semiconductor layer is exposed to form a gate sidewall made of the insulating layer;
Introducing cesium into a region where the surface of the semiconductor layer is exposed to form a cesium-containing region;
Forming the first and second metal source / drain electrodes so as to be in contact with the cesium-containing region.

  According to the present invention, at least one of the surfaces of the cesium-containing region adjacent to the gate electrode is subjected to at least one of a gas containing an oxidant composed of molecules containing nitrogen, nitrogen radicals, and nitrogen elements in a plasma state. By exposing to an atmosphere including the insulating layer, an insulating layer including a positive fixed charge can be formed.

In addition, a method for manufacturing a semiconductor device of the present invention includes:
A manufacturing method of a semiconductor device for manufacturing a semiconductor device of the present invention,
Forming a gate electrode on the semiconductor layer via a gate insulating film;
Introducing cesium into the upper part of the semiconductor layer and both sides of the gate electrode to form a cesium-containing region;
Forming a positive fixed charge by causing the cesium-containing region to react with other elements to form an insulating layer, thereby segregating the cesium to the interface between the semiconductor layer and the insulating layer;
Etching a part of the insulating layer to form an opening in the insulating layer so that at least a part of the surface of the cesium-containing region in the semiconductor layer is exposed;
Forming the first and second metal source / drain electrodes so as to be in contact with the cesium-containing region.

  According to the present invention, the cesium-containing region is reacted with other elements by oxidation, oxynitridation, nitridation, or the like, thereby forming an insulating layer on the cesium-containing region, and at the same time, part of the cesium and A fixed charge can be formed by segregating at the interface with the cesium-containing region. Therefore, since it is not necessary to introduce cesium into the insulating layer separately from the step of forming the cesium-containing region in order to form a fixed charge, the process can be simplified. Further, since the fixed charge and the cesium-containing region are formed using the same material, the manufacturing cost can be reduced.

In addition, a method for manufacturing a semiconductor device of the present invention includes:
A manufacturing method of a semiconductor device for manufacturing a semiconductor device of the present invention,
Forming a gate electrode on the semiconductor layer via a gate insulating film;
Introducing cesium into the upper part of the semiconductor layer and both sides of the gate electrode to form a cesium-containing region;
Forming an insulating layer so as to cover at least a region adjacent to the gate electrode in the surface of the cesium-containing region;
Forming a positive fixed charge by segregating the cesium by annealing at the interface between the insulating layer and the semiconductor layer;
Etching a part of the insulating layer to form an opening in the insulating layer so that at least a part of the surface of the cesium-containing region in the semiconductor layer is exposed;
Forming the first and second metal source / drain electrodes so as to be in contact with the cesium-containing region.

  According to the present invention, after forming the insulating layer on the cesium-containing region, annealing is performed, whereby a part of cesium is segregated at the interface between the insulating layer and the cesium-containing region, so that a fixed charge can be formed. Therefore, since it is not necessary to introduce cesium into the insulating layer separately from the step of forming the cesium-containing region in order to form a fixed charge, the process can be simplified. Further, since the fixed charge and the cesium-containing region are formed using the same cesium, the manufacturing cost can be reduced.

In addition, a method for manufacturing a semiconductor device of the present invention includes:
A manufacturing method of a semiconductor device for manufacturing a semiconductor device of the present invention,
Forming a gate electrode on the semiconductor layer via a gate insulating film;
Forming an insulating layer on the surface of the semiconductor layer and on both sides of the gate electrode;
Introducing cesium into both sides of the gate electrode and the insulating layer above the semiconductor layer to form a cesium-containing region and forming a positive fixed charge in the insulating layer;
Etching part of the insulating layer to form an opening in the insulating layer so that at least part of the surface of the cesium-containing region in the semiconductor layer is exposed;
Forming the first and second metal source / drain electrodes so as to be in contact with the cesium-containing region.

  According to the present invention, it is not necessary to introduce a step of forming a fixed charge in the insulating layer separately from the step of forming the cesium-containing region in order to form a fixed charge, and therefore the process can be simplified. . In addition, since the fixed charge and the impurity-containing region are formed using the same material, the manufacturing cost can be reduced.

In one embodiment,
The step of forming the first and second metal source / drain electrodes includes:
Depositing a metal on the cesium-containing region;
Performing annealing to react the semiconductor layer with the metal;
Removing the unreacted portion of the metal.

  According to the above embodiment, since the metal source / drain electrode is formed by reacting the metal and the semiconductor layer, the adhesion and adhesion at the interface between the metal source / drain electrode and the semiconductor layer can be improved, The interface state density can be reduced. Therefore, good rectification characteristics can be obtained. Further, the metal source / drain electrode can be formed at a position self-aligned with the gate electrode.

In one embodiment,
The semiconductor layer includes at least one of silicon and germanium,
The metal includes one or more of nickel, cobalt, titanium, erbium and ytterbium.

  Note that at least one of the silicon and germanium is preferably a main component of the semiconductor layer.

  According to the embodiment, since the self-aligned silicide process and the self-aligned germanide process can be applied, the shallow metal source / drain electrode can be easily formed at a position self-aligned with respect to the gate electrode.

  According to the present invention, the cesium-containing region containing cesium that modulates the Schottky barrier is provided in a part or all of the region in contact with the metal source / drain electrode in the semiconductor layer. In addition, the leakage current between the second metal source / drain electrodes can be significantly suppressed, and the resistance between the channel and the first and second metal source / drain electrodes can be significantly reduced.

  Further, since cesium hardly generates carriers in the bulk of the semiconductor layer, even if the cesium-containing region is formed deeper than the first and second metal source / drain electrodes, the short channel effect characteristic can be deteriorated. Absent. That is, the source / drain can be formed in a region shallower than the cesium implantation depth, and an extremely shallow source / drain can be formed. Therefore, good short channel effect characteristics can be obtained.

  Furthermore, since the gate sidewall film includes a fixed charge, even if at least one of the first and second metal source / drain electrodes is offset from the gate electrode due to process variations or the like, the gate sidewall including the fixed charge is included. Since a carrier layer having a polarity opposite to the polarity of the fixed charge is induced on the surface of the semiconductor layer below the film, an increase in parasitic resistance can be prevented. Therefore, the yield can be dramatically improved.

It is sectional drawing in one manufacturing process in 1st Embodiment in the semiconductor device of this invention. It is sectional drawing in one manufacturing process in 1st Embodiment in the semiconductor device of this invention. It is sectional drawing in one manufacturing process in 1st Embodiment in the semiconductor device of this invention. It is sectional drawing in one manufacturing process in 1st Embodiment in the semiconductor device of this invention. It is sectional drawing of the semiconductor device manufactured by the manufacturing method shown in FIG. It is sectional drawing of the diode produced by the method similar to the metal source drain electrode in FIG. It is a figure which shows the current-voltage characteristic in FIG. FIG. 4 is an energy band diagram in FIG. 3. FIG. 4 is an energy band diagram when there is no cesium-containing region in FIG. 3. FIG. 4 is a diagram showing current-voltage characteristics when N-type silicon is used in FIG. 3. FIG. 4 is an energy band diagram when N-type silicon is used in FIG. 3. FIG. 4 is an energy band diagram in the case where N-type silicon is used in FIG. 3 and no cesium-containing region exists. It is an energy band figure in the BB 'cross section in FIG. FIG. 3 is an energy band diagram at the BB ′ cross section when there is no cesium-containing region in FIG. 2. It is sectional drawing in one manufacturing process in 2nd Embodiment. It is sectional drawing in one manufacturing process in 2nd Embodiment. It is sectional drawing in one manufacturing process in 2nd Embodiment. It is sectional drawing in one manufacturing process in 2nd Embodiment. It is sectional drawing in one manufacturing process in 3rd Embodiment. It is sectional drawing in one manufacturing process in 3rd Embodiment. It is sectional drawing in one manufacturing process in 3rd Embodiment. It is sectional drawing in one manufacturing process in 3rd Embodiment. It is sectional drawing in one manufacturing process in 3rd Embodiment. It is DD 'arrow sectional drawing of FIG. 13E. It is EE 'arrow sectional drawing of FIG. 13E. It is DD 'arrow sectional drawing of FIG. 13E different from FIG. It is DD 'arrow sectional drawing of FIG. 13E different from FIG. 14 and FIG. It is a figure which shows the case where at least one of the metal source drain electrode is offset with respect to the gate electrode due to process variations or the like.

  Hereinafter, the present invention will be described in detail with reference to the drawings.

  The semiconductor that can be used in the present invention is not particularly limited, and silicon, germanium, SiGe, GaAs, GaN, SiC, carbon nanotubes, and the like can be used. Further, it may be an SOI (Semiconductor On Insulator) substrate or a strained semiconductor substrate in which carrier mobility is improved by applying strain to the crystal. In addition, a polycrystalline semiconductor or an amorphous semiconductor formed on a glass substrate or the like may be used.

(First embodiment)
1A to 1D are cross-sectional views in each manufacturing process of the semiconductor device of the first embodiment. FIG. 2 is a cross-sectional view of the semiconductor device manufactured by the manufacturing method shown in FIG. A method for manufacturing the semiconductor device of this embodiment will be described below with reference to FIGS.

  First, an element isolation region (not shown) is formed on one main surface of a P-type silicon substrate 1 as an example of a semiconductor layer by a known method such as an STI (Shallow Trench Isolation) method. Each element formation region is defined by the element isolation region.

  Next, as shown in FIG. 1A, by using a thermal oxidation method, a CVD (Chemical Vapor Deposition) method, an ALD (Atomic Layer Deposition) method, or the like, the element formation region is formed. A gate insulating film 2 made of silicon oxide is formed on the surface, and then an N-type polycrystalline silicon film is deposited on the gate insulating film 2 using a CVD method or the like. Next, the gate electrode 3 is formed by patterning the polycrystalline silicon film using a lithography method, a reactive ion etching (RIE) method, or the like.

  As the material of the gate insulating film 2, silicon oxynitride, silicon nitride, hafnium oxide, lanthanum oxide, or a material containing these materials containing nitrogen, silicon, aluminum, or the like may be used instead of silicon oxide. Good. Further, although polycrystalline silicon is used as the material of the gate electrode 3, amorphous silicon, germanium, silicon containing germanium, or the like may be used.

Next, as shown in FIG. 1B, for example, in PE-CVD (Plasma Enhanced CVD) method, 300 mTorr to 600 mTorr, gas flow rate ratio SiH ₄ / NH ₃ = 0.04 to 1.5, substrate temperature 300 ° C. to 450 A silicon nitride film is formed under the conditions of ° C. and plasma power of 40 W to 100 W. At this time, positive fixed charges are formed in the silicon nitride film. Thin silicon nitride may be formed by nitriding the silicon surface by exposing radicals containing nitrogen element or plasma to the silicon surface. The refractive index of silicon nitride is preferably 2.1 or higher. In this case, the density of positive fixed charges is very high. Subsequently, the gate sidewall films 4a and 4b containing positive fixed charges are formed by etching back by the RIE method. As shown in FIG. 1B, the gate sidewall film 4 a is formed on one side surface of the gate electrode 3, while the gate sidewall film 4 b is formed on the other side surface of the gate electrode 3.

  As the material of the gate sidewall films 4a and 4b, any material can be used as long as it is an insulator containing positive fixed charges. Further, the positive fixed charges in the gate side wall films 4a and 4b can be formed as follows. For example, instead of the silicon nitride film, after forming a silicon oxide film by a CVD method or the like, an impurity that becomes a positive fixed charge such as cesium or the like is introduced into the silicon oxide by an ion implantation method or the like, Etching back by the RIE method or the like can form the gate sidewall films 4a and 4b including positive fixed charges. In addition, a fixed film is formed by etching back a laminated film in which an insulating film such as silicon oxide, silicon nitride, or silicon oxynitride is deposited on the insulating film including the fixed charge formed by the above-described method. Including gate sidewall films 4a and 4b may be formed.

  As described above, when the gate sidewall films 4a and 4b contain positive fixed charges, for example, as shown in FIG. 18, at least one of the metal source / drain electrodes 6a and 6b formed in the subsequent process is caused by process variation or the like. Even when offset with respect to the gate electrode 3, since the electron carrier layer 58 is formed on the silicon surface as the semiconductor under the gate sidewall films 4a and 4b including the fixed charge 59, the channel region and the metal source / drain electrode 6a and 6b can be connected ohmic via the electron carrier layer 58, and an increase in parasitic resistance can be remarkably suppressed. Thereby, the yield can be dramatically improved. In FIG. 18, 2 indicates a gate insulating film, 3 indicates a gate electrode, 5a and 5b indicate cesium-containing regions, and 7 indicates nickel silicide. Further, since the electron carrier layer 58 is extremely thin, the short channel effect characteristic is not deteriorated.

  Note that even if the first and second metal source / drain electrodes are formed in a self-aligned position with respect to the gate electrode by using a self-aligned process such as a SALICIDE (Self-Aligned Silicide) process. Such misalignment occurs for the following reason.

  That is, in recent LSI manufacturing, a large-diameter semiconductor wafer is used. In this case, for example, when a metal film is deposited by a sputtering method to form a metal silicide, the wafer flies from a sputter target, particularly in the periphery of the wafer. Since the incident angle of the incoming metal particles becomes large, the gate electrode becomes a shadow, and in the region close to the gate electrode, a difference in the film thickness of the metal deposited on both sides of the gate electrode is likely to occur (for example, one side is thin and the other side is thin) Becomes thicker). When silicidation is performed in such a state, since the film thickness of the metal silicide is thinner than the target value when the metal film thickness is thin, the lateral growth is also shortened. Therefore, the metal silicide (first and second) One of the metal source / drain electrodes 6 a and 6 b is offset with respect to the gate electrode 3.

但し、

When the P-type impurity concentration in the silicon near the end of the gate electrode 3 is N _A (cm ⁻³ ), the fixed charge density σ _FC (cm ⁻² ) in the gate sidewall films 4a and 4b is By satisfying the above condition, the above-described electron carrier layer can be formed.

However,

Here, kappa is the dielectric constant of the silicon (semiconductor), epsilon is the dielectric constant of vacuum (F / cm), q is the elementary electric charge (C), N _i is silicon ( The intrinsic carrier density (cm ⁻³ ) of the semiconductor), k _B is the Boltzmann constant (eV / K), and T is the absolute temperature (K). Thus, for example, when N _A = 1 × 10 ¹⁸ cm ⁻³ ,
σ _FC ≧ 3.5 × 10 ¹² cm ^-2
Thus, the electron carrier layer can be formed.

More preferably, σ _FC = 1 × 10 ¹³ cm ^{−2 to} 3 × 10 ¹³ cm ⁻² . At this time, the resistance of the electron carrier layer becomes the lowest, and the increase in resistance due to the offset can be most effectively prevented. As σ _FC increases, the electron carrier density increases, but the mobility decreases. ^Therefore , the resistance of the electron carrier layer is lowest at σ _FC = 1 × 10 ¹³ cm ^{−2 to} 3 × 10 ¹³ cm ^−2. Become.

  In the case of a P-type element, the same effect as described above can be obtained by making the polarity of the fixed charge negative. For example, silicon nitride having a dielectric constant of less than 1.9 or aluminum oxide formed using an ALD method or the like is formed, and then etched back to form a gate sidewall film having a negative fixed charge.

Next, as shown in FIG. 1C, cesium as an impurity that modulates the Schottky barrier between the semiconductor layer and the metal source / drain electrode is ionized under the conditions of, for example, an acceleration energy of 5 keV and a dose of 1 × 10 ¹⁴ cm ^−2. By injecting, the cesium-containing regions 5a and 5b are formed. The ion implantation conditions are not limited to the above conditions, but the cesium-containing regions 5a and 5b are formed to a position deeper than nickel silicides 6a and 6b (see FIG. 1D) formed in a later step. You can do it.

  Cesium (mass number 133) has a larger mass number than P (mass number 31), As (mass number 75), etc., which are normal donor impurities. Can be ion implanted. In ion implantation, the smaller the ion implantation energy and the smaller the number of implanted species, the smaller the amount of current during ion implantation. There is a problem that it becomes long. Cesium has a larger mass number than normal donor impurities such as P and As, so it can take a larger amount of current. Therefore, the ion implantation time can be greatly shortened or ion implantation can be performed at a lower energy. It becomes possible. As a result, the metal source / drain electrode can be formed at an extremely shallow position, so that the short channel effect characteristic can be improved.

  Further, the cesium ion implantation may be performed so that cesium is introduced into the gate sidewall films 4a and 4b at the same time as the formation of the cesium-containing regions 5a and 5b by adjusting the tilt angle. Good. In that case, since cesium is ionized in the gate sidewall films 4a and 4b and becomes a positive fixed charge, it is not necessary to previously include the fixed charges in the gate sidewall films 4a and 4b. The material of the gate sidewall films 4a and 4b is preferably silicon oxide. In this case, annealing causes diffusion of cesium in the gate sidewall film and segregation at the interface between the gate sidewall films 4a and 4b and the P-type silicon substrate 1, thereby generating a high-density fixed charge. Because it can.

  In addition, since the gate sidewall films 4a and 4b contain positive fixed charges, at least one of the metal source / drain electrodes formed in the subsequent process is offset with respect to the gate electrode 3 due to process variations or the like. Even in such a case, since the electron carrier layer is formed immediately below the gate sidewall films 4a and 4b containing fixed charges, the channel region and the metal source / drain electrode can be connected ohmic via the electron carrier layer, and parasitic An increase in resistance can be prevented. Thereby, the yield can be dramatically improved. Since the electron carrier layer is extremely thin, the short channel effect characteristic is not deteriorated. Thus, the process can be simplified by simultaneously forming the cesium-containing regions 5a and 5b and the fixed charges in the gate sidewall films 4a and 4b using the same material.

  Thereafter, annealing may be performed to recover the implantation damage. In that case, for example, RTA method, FLA (Flash Lamp Annealing) method, laser annealing method or the like is used. In this embodiment, the cesium-containing regions 5a and 5b are formed after forming the gate sidewall films 4a and 4b containing fixed charges. However, after the cesium-containing regions 5a and 5b are formed, the gate sidewall films 4a and 4b are formed. Can also be formed. For example, after forming the cesium-containing regions 5a and 5b, the insulating layer is formed by oxidation, oxynitridation, or nitridation. At this time, cesium segregates at the interface between the insulating layer and the P-type silicon substrate 1 and becomes a positive fixed charge. Thereafter, by etching back the insulating layer, the gate sidewall films 4a and 4b containing fixed charges can be formed. Alternatively, after forming the cesium-containing regions 5a and 5b, an insulating layer (eg, silicon oxide, silicon oxynitride, silicon nitride) is formed by CVD or the like, and then annealing is performed. At this time, cesium segregates at the interface between the insulating layer and the P-type silicon substrate 1 and becomes a positive fixed charge. Thereafter, by etching back the insulating layer, the gate sidewall films 4a and 4b containing fixed charges can be formed.

  Next, as shown in FIG. 1D, after depositing nickel, for example, about 2 nm by sputtering or the like, annealing is performed under conditions of 260 ° C. to 350 ° C. and 30 seconds to 200 seconds. In this way, the deposited nickel is silicided. Prior to annealing, TiN may be deposited on nickel by sputtering or the like. Thereafter, unreacted nickel (and TiN) is removed to form the nickel silicides 6a and 6b as an example of the metal source / drain electrodes. Thereafter, the resistance of the nickel silicide 6 is lowered by annealing under conditions of 350 ° C. to 500 ° C. and 30 seconds to 200 seconds.

  In that case, at least the thickness (depth) of the nickel silicides 6a and 6b (hereinafter sometimes referred to as the first and second metal source / drain electrodes 6a and 6b) is thinner (shallow) than the cesium-containing regions 5a and 5b. The nickel silicides 6a and 6b are in contact with the semiconductor layer (P-type silicon substrate 1) through the cesium-containing regions 5a and 5b. As shown in FIG. 1D, the first metal source / drain electrode 6a is in contact with the cesium-containing region 5a, while the second metal source / drain electrode 6b is in contact with the cesium-containing region 5b. Here, the thickness of the nickel silicides 6a and 6b is about three times the thickness of the sputtered nickel film (for example, about 6 nm).

  After the above process, the first and second metal source / drain electrodes (nickel silicide) 6a and 6b have impurities that modulate the Schottky barrier between the semiconductor layer and the first and second metal source / drain electrodes. A part of cesium may be included. In this case, since the work function of cesium (1.93 eV) is smaller than that of nickel silicide (NiSi) (4.9 eV), the work functions of the first and second metal source / drain electrodes are reduced, and the shot for electrons is reduced. The key barrier height can be further reduced. In the case of a P-type MOSFET, the work function of the first and second metal source / drain electrodes is increased by using a material having a work function larger than that of the first and second metal source / drain electrodes instead of cesium. And the height of the Schottky barrier for holes can be further reduced.

  The nickel silicide 6a, 6b functions as a source / drain. When the nickel silicides 6a and 6b are formed, the upper portion of the gate electrode 3 is also silicided to form the nickel silicide 7. Thus, the structure shown in FIG. 2 is formed. The gate electrode 3 may be entirely silicided to form a metal gate structure. In the case of a metal gate structure, the polycrystalline silicon film may be either i-type or P-type. Thereafter, finally, an interlayer insulating film (not shown), an upper wiring (not shown), and the like are formed by a known method, thereby completing the semiconductor device.

  In the case where cobalt silicide is formed as the first and second metal source / drain electrodes instead of nickel silicide 6a, 6b, after depositing about 3 nm of cobalt by sputtering or the like, 400 ° C. to 600 ° C., 30 ° C. Annealing is performed under conditions of seconds to 200 seconds. In this way, cobalt is silicided. Note that TiN may be deposited on cobalt by sputtering or the like before annealing. Then, after removing unreacted cobalt (and TiN), the resistance of cobalt silicide may be reduced by annealing at 700 ° C. to 900 ° C. for 30 seconds to 200 seconds. Also in this case, at least the thickness of the cobalt silicide contains cesium so that the first and second metal source / drain electrodes (cobalt silicide) are in contact with the semiconductor layer (for example, a P-type silicon substrate) via the cesium-containing region. It is formed so as to be thinner than the region. The thickness of the cobalt silicide is preferably about twice the thickness of the sputtered cobalt film (for example, about 6 nm).

  As described above, the case of nickel silicide 6a, 6b and cobalt silicide has been described as the first and second metal source / drain electrodes. However, the first and second metal source / drain electrodes are not limited to these. . For example, metal silicide using a metal composed of one or more elements of Ni, Co, Ti, Er, Yb, and Pt may be used.

  According to the semiconductor device of the present embodiment, the cesium-containing regions 5a and 5b are formed between the first and second metal source / drain electrodes (nickel silicide) 6a and 6b and the semiconductor layer (P-type silicon substrate 1). Therefore, the cesium in the vicinity of the first and second metal source / drain electrodes 6a and 6b is ionized to increase the energy barrier height against holes. As a result, the leakage current between the first and second source / drains 6a and 6b and the P-type silicon substrate 1 can be significantly reduced as compared with a Schottky junction in which no cesium-containing region is formed. At the same time, the height of the Schottky barrier for electrons between the channel and the first and second source / drains 6a and 6b can be effectively reduced, and the parasitic resistance can be significantly reduced as compared with the Schottky junction. .

In that case, cesium at the interface with the first and second metal source / drain electrodes 6a, 6b (where the first metal source / drain electrode is 6a and the second metal source / drain electrode is 6b) of the cesium-containing regions 5a, 5b. if the concentrations 1 × 10 ¹⁹ cm ^-3 or more, cesium-containing region 5a, the first and second metal source drain electrode 6a of 5b, cesium concentration at the interface between 6b sufficiently large. Therefore, the Schottky barrier can be modulated more greatly to reduce the leakage current between the source / drain and the semiconductor layer and to reduce the parasitic resistance between the channel and the source / drain more effectively. .

  Furthermore, if the cesium concentration in the cesium-containing regions 5a and 5b is set to have a peak at a position deeper than the interface between the cesium-containing regions 5a and 5b and the first and second metal source / drain electrodes 6a and 6b. A wide range of the first and second metal source / drain electrodes 6a and 6b can be covered with a high concentration cesium region. Therefore, the leakage current between the first and second source / drain electrodes 6a and 6b and the P-type silicon substrate 1 as the semiconductor layer can be further effectively reduced.

  Further, since cesium is not a silicon donor and acceptor, cesium is not ionized in a region sufficiently distant from the first and second metal source / drain electrodes 6a and 6b in the cesium-containing regions 5a and 5b. Therefore, it is not necessary to extremely reduce the thickness of the cesium-containing regions 5a and 5b between the first and second metal source / drain electrodes 6a and 6b and the semiconductor layer (P-type silicon substrate 1) (that is, cesium Therefore, it is not necessary to use an impurity segregation technique as disclosed in Patent Document 1 above.

  As described above, in the semiconductor device of this embodiment, the thickness (depth) of the metal silicide can be determined without restriction by ion implantation, so that a very shallow metal source / drain can be formed, and as a result, the short channel effect Can be suppressed very well.

  In order to confirm the effect of having the cesium-containing regions 5a and 5b in the semiconductor device of this embodiment, the following experiment was performed.

FIG. 3 is a cross-sectional view of a diode manufactured by the same method as the first and second metal source / drain electrodes 6a and 6b in FIG. 1D. That is, in this diode, a cesium-containing region 12 is formed on the surface of the P-type silicon 11, and then a nickel silicide 13 is formed. Nickel silicide 13 is in contact with P-type silicon 11 through cesium-containing region 12. As a result of analysis by SIMS (secondary ion mass spectrometry), the cesium concentration in the cesium-containing region 12 was 1 × 10 ¹⁹ cm ⁻³ at the interface with the nickel silicide 13. Further, the concentration distribution of cesium had a peak in the P-type silicon 11 outside the nickel silicide 13.

  FIG. 4 shows current-voltage characteristics measured between the nickel silicide 13 and the back surface of the P-type silicon 11 in FIG. For comparison, FIG. 4 also shows the current-voltage characteristics of a diode that does not have a cesium-containing region. In FIG. 4, the horizontal axis bias voltage is a voltage applied to the nickel silicide 13 with reference to the P-type silicon 11.

  As can be seen from FIG. 4, when the cesium-containing region 12 is provided, the reverse bias current is remarkably small as compared with the case where the cesium-containing region is not provided. From this, it can be seen that the leakage current between the first and second metal source / drain electrodes 6a and 6b and the P-type silicon substrate 1 is remarkably reduced in the source / drain structure shown in FIG.

  Hereinafter, the reason for this will be described with reference to FIGS.

FIG. 5 is an energy band diagram in the CC ′ section in FIG. 3, and FIG. 6 is an energy band diagram corresponding to FIG. 5 when the cesium-containing region 12 does not exist. 5 and FIG. 6, “E _C ^Si ” is the lower conduction band of silicon, “E _F ^Si ” is the Fermi level of silicon, and “E _V ^Si ” is the valence band of silicon. On the upper end, “E _F ^M ” indicates the Fermi level of the nickel silicide 13, and “φ _b ^h ” indicates the Schottky barrier height for holes.

Since the diode shown in FIG. 6 is a Schottky barrier diode, the reverse bias current I _rp is expressed by the following formula (1).

Where φ _b ^h is the Schottky barrier height for holes, k _B is the Boltzmann constant, and T is the absolute temperature. Incidentally, phi _b ^h is the energy difference between the valence band maximum _E ^{V Si} of the Fermi level _E ^{F M} and P-type silicon 11 of nickel silicide 13 at the interface between the nickel silicide 13 and the P-type silicon 11.

In FIG. 5, the ionization potential of cesium is 3.89 eV, whereas the electron affinity of silicon is 4.05 eV. Therefore, cesium has an energy level higher than the lower conduction band E _C ^Si of silicon. Is thought to form. In this case, electrons are emitted from the energy level produced by cesium to the nickel silicide 13 side, and cesium is positively ionized. In the region where cesium is ionized, the energy band of silicon is greatly pushed down according to the density of cesium. That is, when the density of the cesium is sufficiently large, to the lowest point of the bottom of the conduction band E _C ^Si of the silicon is substantially coincident with the Fermi level E _F ^M of the nickel silicide 13 is bent silicon energy band.

  On the other hand, since cesium does not activate as a donor for silicon, cesium at a position sufficiently far from nickel silicide 13 in cesium-containing region 12 remains neutral. In addition, since the emission of electrons from cesium at a position away from the interface with the P-type silicon 11 in the cesium-containing region 12 to the nickel silicide 13 mainly occurs due to the tunnel effect, the cesium ionizes the nickel silicide 13. And from the interface between the cesium-containing region 12 and the range of about 3 nm.

In order to measure the activation rate of cesium as a donor in silicon, hole measurement was performed. The sample was prepared as follows. That is, cesium was ion-implanted at an acceleration energy of 100 keV into a 12 mm square sample in which 10 nm of SiO ₂ was formed on silicon. In that case, most of the cesium is distributed in the silicon. Next, P ions were implanted using a resist having openings at the four corners of the sample as a mask. Subsequently, after removing the resist, annealing was performed at 900 ° C. for 10 seconds to form an n ⁺ region, and damage caused by cesium ion implantation was recovered.

Next, SiO ₂ on the four n ⁺ regions was opened using the lithography method and the RIE method, and subsequently, a Ti electrode was formed on each n ⁺ region using the lift-off method. Using this sample, hole measurement was performed by the Van der Pauw method. As a result, an electron surface density of 3.0 × 10 ¹² cm ⁻² was obtained. As a result of SIMS analysis, the amount of cesium contained in silicon was 1.7 × 10 ¹⁵ cm ⁻² . Therefore, the activation rate of cesium in silicon was a sufficiently low 0.18%. However, since cesium injected into SiO ₂ becomes a positive fixed charge and induces electron carriers in silicon, the activation rate of cesium in actual silicon as a donor is lower than 0.18%. It is thought that. Thus, it was found that cesium hardly generates carriers in the bulk of the silicon layer as the semiconductor layer.

As a result, the energy barrier height against holes in the diode shown in FIG. 5 is represented by φ _b ^h (Cs) in FIG. 5, and the reverse bias current I _rp (Cs) is represented by the following formula (2). .

As can be seen from FIG. 5, since φ _b ^h (Cs)> φ _b ^h , I _rp (Cs) << I _rp . In the case of many metal silicides, φ _b ^h is about 0.4 eV to 0.5 eV, whereas φ _b ^h (Cs) can be increased up to about 1.1 eV of silicon band gap. Is significantly reduced.

  Thus, the reverse bias current can be remarkably reduced by having the cesium-containing region in the semiconductor layer at the interface between the metal and the semiconductor layer. Therefore, since the structure of the semiconductor device shown in FIG. 2 has the cesium-containing regions 5a and 5b, the leakage current between the first and second metal source / drain electrodes 6a and 6b and the P-type silicon substrate 1 is reduced. It can be significantly reduced. 2 is the same as the energy band diagram of FIG. 5 in the semiconductor device shown in FIG.

  Next, a diode manufactured by using N-type silicon instead of P-type silicon 11 with the same structure as the diode shown in FIG. 3 will be described.

  FIG. 7 is a diagram showing current-voltage characteristics of the diode using the N-type silicon. FIG. 7 also shows current-voltage characteristics when there is no cesium-containing region. As shown in FIG. 7, when the cesium-containing region is included, the reverse bias current is remarkably increased as compared with the case where the cesium-containing region is not included. This indicates that the resistance between nickel silicide and N-type silicon is reduced by forming the cesium-containing region. From this, it can be seen that in the source / drain structure shown in FIG. 2, the resistance between the first and second metal source / drain electrodes 6a and 6b and the channel is small.

  Hereinafter, this reason will be described with reference to FIGS.

  8 is an energy band diagram in a CC ′ section of a diode using N-type silicon instead of P-type silicon 11 in FIG. 3, and FIG. 9 is a diagram in which no cesium-containing region 12 exists in FIG. FIG. 9 is an energy band diagram corresponding to FIG.

Since the diode shown in FIG. 9 is a Schottky barrier diode, the reverse bias current I _rn is expressed by the following formula (3).

Here, phi _b ^e is a Schottky barrier height for electrons, k _B is the Boltzmann constant, T is the absolute temperature. Incidentally, phi _b ^e is the energy difference between the Fermi level of the conduction band and the nickel silicide 13 of N-type silicon at the interface between the N-type silicon and nickel silicide 13.

In FIG. 8, the ionization potential of cesium is 3.89 eV, whereas the electron affinity of silicon is 4.05 eV. Therefore, cesium forms an energy level on the higher energy side than the lower end of the conduction band of silicon. It is considered a thing. In this case, electrons are emitted from the energy level produced by cesium to the nickel silicide side, and cesium is positively ionized. In the region where cesium is ionized, the energy band of silicon is greatly pushed down according to the density of cesium. That is, when the density of the cesium is sufficiently large, to the lowest point of the bottom of the conduction band E _C ^Si of the silicon is substantially coincident with the Fermi level E _F ^M of the nickel silicide 13, the energy band of the silicon is bent.

  On the other hand, since cesium does not activate as a donor for silicon, cesium at a position sufficiently far from nickel silicide 13 in cesium-containing region 12 remains neutral. In addition, since emission of electrons from cesium at a position away from the interface with the N-type silicon in the cesium-containing region 12 to the nickel silicide 13 is mainly caused by a tunnel effect, the cesium is ionized by the nickel silicide 13 It is limited to a range of about 3 nm from the interface with the cesium-containing region 12.

As a result, the width of the Schottky barrier becomes very thin, and further, due to the reduction of the Schottky barrier height due to the mirror image effect, electrical conduction between the nickel silicide 13-P type silicon 11 is mainly caused by the tunnel current. . Accordingly, as shown in FIG. 8, the energy barrier height for electrons φ _b ^e (Cs) is a energy difference between the Fermi level E _F ^M of the conduction band of the silicon bottom E _C ^Si and nickel silicide 13. In this case, the reverse bias current I _rn (Cs) is expressed by the following formula (4).

As can be seen from FIG. 8, since it is ^{_{φ b e (Cs) << φ}} b e, the _{I rn (Cs) >> I rn} . Since φ _b ^e (Cs) is a very small value of the energy difference between the bottom conduction band E _C ^Si of silicon and the Fermi level E _F ^{Si of silicon} , as shown in FIG. Current-voltage characteristics can be obtained. Therefore, in the structure of the semiconductor device shown in FIG. 2, since the channel in the on state can be regarded as an N-type region having a high electron density, the channel-source drain can be connected with a low resistance by having the cesium-containing region 12. I understand that there is.

  Hereinafter, the resistance between the channel and the first and second source / drain electrodes in the semiconductor device shown in FIG. 2 will be considered with reference to FIGS.

  FIG. 10 is an energy band diagram in the BB ′ cross section in FIG. 2, and FIG. 11 corresponds to FIG. 10 in the case where the cesium containing regions 5a and 5b do not exist (Schottky junction transistor) in FIG. It is an energy band figure.

  As shown in FIG. 11, by applying a voltage to the gate electrode 3, the energy band of silicon is bent, and an inversion layer is formed in the channel region. As a result, the thickness of the Schottky barrier is reduced and the height of the Schottky barrier with respect to electrons is reduced due to the mirror image effect, so that a tunnel current can flow.

  On the other hand, in FIG. 10 where the cesium-containing regions 5a and 5b exist, the energy band of silicon is bent by voltage application to the gate electrode 3, and an inversion layer is formed in the channel region. . In at least a region close to the source in the cesium-containing regions 5a and 5b, cesium is positively ionized by emitting electrons to the source side. As a result, as can be seen from a comparison with FIG. 11, in the region where cesium is ionized, the energy band of silicon is further bent and the inclination becomes very steep. As a result, the thickness of the Schottky barrier becomes very thin and the height of the Schottky barrier with respect to electrons is greatly reduced by the mirror image effect, so that the tunnel current between the source and the channel is remarkably increased.

  Therefore, since the semiconductor device shown in FIG. 2 has the cesium-containing regions 5a and 5b, the resistance between the channel and the source / drain can be remarkably reduced, and a large on-current can be obtained.

  As described above, according to the semiconductor device of this embodiment, the Schottky barrier is modulated between the first and second metal source / drain electrodes (nickel silicide) 6a and 6b and the semiconductor layer (P-type silicon substrate 1). Cesium-containing regions 5a and 5b containing cesium as an impurity to be formed are formed. Therefore, ionization of cesium in the vicinity of the first and second metal source / drain electrodes 6a and 6b increases the energy barrier height against holes, and the first and second metals compared to the Schottky junction. Leakage current between the source / drain electrodes 6a and 6b and the P-type silicon substrate 1 can be significantly reduced. Further, since the Schottky barrier height between the channel and the first and second metal source / drain electrodes 6a and 6b is effectively reduced and the Schottky barrier thickness is reduced, the Schottky junction is compared with the case of the Schottky junction. Parasitic resistance can be significantly reduced.

  In the first and second metal source / drain electrodes (nickel silicide) 6a and 6b, cesium as an impurity that modulates the Schottky barrier between the semiconductor layer and the first and second metal source / drain electrodes 6a and 6b is formed. Some may be included. In this case, since the work function of cesium (1.93 eV) is larger than that of nickel silicide (NiSi) (4.9 eV), the work function of the metal source / drain electrode is reduced, and the Schottky barrier height against electrons is increased. It can be further reduced.

  Further, since cesium is not a silicon donor and acceptor (that is, almost no carriers are generated in the bulk of silicon), it is sufficient from the first and second metal source / drain electrodes 6a and 6b in the cesium-containing regions 5a and 5b. In a remote region, cesium does not ionize by emitting electrons as carriers. For this reason, it is not necessary to extremely reduce the thickness of the cesium-containing regions 5a and 5b, considering in advance that the region functioning as the source / drain is enlarged by diffusion of cesium or the like. That is, there are no special restrictions on the conditions for ion implantation of cesium. Therefore, in order to reduce the thickness of the cesium-containing regions 5a and 5b, it is not necessary to use an impurity segregation technique as disclosed in Patent Document 1.

  Further, since the cesium-containing regions 5a and 5b do not induce carriers, even if the cesium-containing regions 5a and 5b are formed deeper than the first and second metal source / drain electrodes 6a and 6b, the short channel effect characteristics are deteriorated. There is no. That is, since the first and second metal source / drain electrodes 6a and 6b can be formed in a region shallower than the ion implantation depth of the impurity (cesium), an extremely shallow source / drain can be formed. Therefore, good short channel effect characteristics can be obtained.

  The cesium has an ionization potential (3.89 eV) smaller than the electron affinity (4.05 eV) of silicon. Therefore, cesium forms an impurity level on the higher energy side than the lower end of the conduction band of silicon, and emits electrons from the impurity level to the first and second metal source / drain electrodes 6a and 6b side, Positively ionizes and bends the energy band of silicon. Thus, the energy band of silicon is bent to such an extent that the impurity level matches the Fermi level of the metal source / drain electrode. Therefore, the Schottky barrier can be greatly modulated, and as described above, the leakage current between the P-type silicon substrate 1-first and second metal source / drain electrodes 6a, 6b can be remarkably suppressed, and the channel-first In addition, the resistance between the second metal source / drain electrodes 6a and 6b can be significantly reduced.

Further, since the cesium concentration in the cesium-containing region 12 at the position in contact with the nickel silicide 13 in FIG. 3 was 1 × 10 ¹⁹ cm ⁻³ , the first and second metal source / drain electrodes 6a and 6b and the P-type silicon By setting the cesium concentration at the interface with the substrate 1 to 1 × 10 ¹⁹ cm ⁻³ or more, the Schottky barrier can be greatly modulated. Therefore, the leakage current between the P-type silicon substrate 1 and the first and second metal source / drain electrodes 6a and 6b can be remarkably suppressed, and the resistance between the channel and the first and second metal source / drain electrodes 6a and 6b is remarkably reduced. Can be made.

  The cesium is distributed so as to have a concentration peak at a position deeper than the interface between the first and second metal source / drain electrodes 6 a and 6 b and the P-type silicon substrate 1. Therefore, the wide range of the first metal source / drain electrodes 6a and 6b can be covered with the high concentration cesium-containing region, and the leakage current can be effectively reduced.

  The first and second metal source / drain electrodes 6a and 6b are made of nickel silicide which is a compound of silicon as a semiconductor and nickel as a metal. Therefore, the shallow first and second metal source / drain electrodes 6a and 6b can be easily formed by reducing the thickness of the deposited nickel.

  The semiconductor contains at least one of silicon and germanium as a main component, and the metal contains one or more elements of Ni, Co, Ti, Er, Yb, and Pt. Therefore, since the self-aligned silicide process or the self-aligned germanide process can be used, the shallow metal source / drain electrode can be easily formed at a position self-aligned with respect to the gate electrode.

  As described above, according to the present embodiment, the height and width of the Schottky barrier can be easily controlled regardless of the type of the metal material, the parasitic resistance is low, and the short channel effect can be effectively suppressed. An apparatus and a manufacturing method thereof can be provided.

(Second embodiment)
12A to 12D are cross-sectional views during each manufacturing process of the semiconductor device of the second embodiment. In all the following embodiments including the second embodiment, the first and second metal source / drain electrodes are simply referred to as metal source / drain electrodes without being divided, and the reference number is also the same as the first metal source / drain electrode. The same material is used for the second metal source / drain electrode.

  First, an element isolation region (not shown) is formed on one main surface of a P-type silicon substrate 21 as an example of a semiconductor layer by a known method such as the STI method, and each element is formed by the element isolation region. Define the region.

  Next, as shown in FIG. 12A, a gate insulating film 22 made of silicon oxide is formed on the surface of the element formation region by using a thermal oxidation method, a CVD method, an ALD method, or the like, followed by a CVD method. Etc., an N-type polycrystalline silicon film is deposited on the gate insulating film 22. Next, the gate electrode 23 is formed by patterning the polycrystalline silicon film using a lithography method, an RIE method, or the like.

  As the material of the gate insulating film 22, silicon oxynitride, silicon nitride, hafnium oxide, lanthanum oxide, or a material containing nitrogen, silicon, aluminum or the like in these materials is used instead of silicon oxide. Can do. Further, as the material of the gate electrode 23, amorphous silicon, germanium, silicon containing germanium, or the like can be used instead of polycrystalline silicon.

  Next, a silicon oxide film is deposited using the CVD method or the like, and then etched back by the RIE method to form the gate sidewall film 24. As a material for the gate sidewall film 24, silicon nitride, silicon oxynitride, or the like may be used instead of silicon oxide.

Next, as shown in FIG. 12B, an N-type impurity-containing region 25 is formed by ion implantation of a donor impurity such as As and then annealing. The impurity concentration of the N-type impurity-containing region 25 is so thin that it is not completely depleted even when a drain voltage is applied after the semiconductor device of this embodiment is completed. In this way, the leakage current can be further reduced without causing a large increase in parasitic capacitance. The impurity concentration of the N-type impurity-containing region 25 can be set to a high concentration of 1 × 10 ²⁰ cm ⁻³ or more. In this case, simultaneously with the doping of the N-type impurity-containing region 25, Doping can be performed.

Next, as shown in FIG. 12C, after the gate sidewall film 24 is removed by wet etching or the like using a hydrofluoric acid aqueous solution, for example, in PE-CVD (Plasma Enhanced CVD) method, 300 mTorr to 600 mTorr, gas flow rate ratio SiH ₄ / A silicon nitride film is formed under the conditions of NH ₃ = 0.04 to 1.5, substrate temperature of 300 ° C. to 450 ° C., and plasma power of 40 W to 100 W. At this time, positive fixed charges are formed in the silicon nitride film. Thin silicon nitride may be formed by nitriding the silicon surface by exposing radicals containing nitrogen element or plasma to the silicon surface. The refractive index of silicon nitride is preferably 2.1 or higher. In this case, the density of positive fixed charges is very high. Subsequently, the gate side wall film 26 containing positive fixed charges is formed by etching back by the RIE method.

  The material of the gate sidewall film 26 may be anything as long as it is an insulator containing a fixed charge. The positive fixed charge in the gate sidewall film 26 can also be formed as follows. For example, instead of the silicon nitride film, after forming a silicon oxide film by a CVD method or the like, impurities that become positive fixed charges such as cesium are introduced into the silicon oxide by an ion implantation method or the like, Etching back by the RIE method or the like can form the gate sidewall film 26 containing positive fixed charges.

  In addition, a fixed film is formed by etching back a laminated film in which an insulating film such as silicon oxide, silicon nitride, or silicon oxynitride is deposited on the insulating film including the fixed charge formed by the above-described method. The gate side wall film 26 may be formed.

  As described above, when the gate sidewall film 26 includes a positive fixed charge, even when at least one of the metal source / drain electrodes formed in a later process is offset with respect to the gate electrode 23 due to process variations or the like. Since the electron carrier layer is formed on the silicon surface as the semiconductor under the gate sidewall film 26 containing the fixed charge, the channel region and the metal source / drain electrode can be ohmically connected via the electron carrier layer, An increase in parasitic resistance can be prevented. Thereby, the yield can be dramatically improved. Since the electron carrier layer is extremely thin, the short channel effect characteristic is not deteriorated.

Next, cesium-containing region 27 is formed by ion-implanting cesium, for example, under the conditions of an acceleration energy of 5 keV and a dose of 1 × 10 ¹⁴ cm ⁻² . The ion implantation conditions are not limited to the above conditions, but may be set so that the cesium-containing region 27 is formed to a position deeper than the nickel silicide 28 (see FIG. 12D) formed in a later step. Good.

  Thereafter, annealing may be performed to recover the implantation damage. In that case, for example, RTA method, FLA method, laser annealing method or the like is used.

  Next, as shown in FIG. 12D, after nickel is deposited by, for example, about 2 nm by sputtering or the like, the nickel is silicided by annealing at 260 ° C. to 350 ° C. for 30 seconds to 200 seconds. Prior to annealing, TiN may be deposited on nickel by sputtering or the like. Thereafter, unreacted nickel (and TiN) is removed to form nickel silicide 28 as an example of a metal source / drain electrode. Then, the resistance of the nickel silicide 28 is reduced by annealing under conditions of 350 ° C. to 500 ° C. and 30 seconds to 200 seconds. In that case, the nickel silicide (hereinafter sometimes referred to as a metal source / drain electrode) 28 is formed so that at least its thickness (depth) is thinner (shallow) than the cesium-containing region 27, and the nickel silicide 28 is formed of cesium. The semiconductor layer (P-type silicon substrate 21) is in contact with the inclusion region 27. Here, the thickness of the nickel silicide 28 is about three times the thickness of the sputtered nickel film (for example, about 6 nm). Thereafter, finally, an interlayer insulating film (not shown), an upper wiring (not shown), and the like are formed by a known method, thereby completing the semiconductor device.

  The nickel silicide 28 functions as a source / drain. Further, when the nickel silicide 28 is formed, the gate electrode 23 is also silicided to form a nickel silicide 29. In this case, the gate electrode 23 may be entirely silicided to have a metal gate structure. In the case of a metal gate structure, the polycrystalline silicon film may be either i-type or P-type. Further, when cobalt silicide is formed as the metal source / drain electrode instead of nickel silicide 28, cobalt is deposited by about 3 nm by sputtering or the like, and then annealed under conditions of 400 ° C. to 600 ° C. for 30 seconds to 200 seconds. As a result, silicidation occurs. Prior to annealing, TiN may be deposited on cobalt by sputtering or the like. Then, after removing unreacted cobalt (and TiN), the resistance of cobalt silicide may be reduced by annealing at 700 ° C. to 900 ° C. for 30 seconds to 200 seconds. Also in this case, the cobalt silicide is at least thinner than the cesium-containing region so that the metal source / drain electrode (cobalt silicide) is in contact with the semiconductor layer (P-type silicon substrate 21) via the cesium-containing region 27. To form. The thickness of the cobalt silicide is preferably about twice the thickness of the sputtered cobalt film (for example, about 6 nm).

  The case where the metal source / drain electrode is nickel silicide 28 and cobalt silicide has been described above, but the metal source / drain electrode is not limited to these. For example, the metal source / drain electrode may be made of a metal silicide using a metal composed of one or more elements of Ni, Co, Ti, Er, Yb, and Pt.

  According to the semiconductor device of this embodiment, since the cesium-containing region 27 is formed between the metal source / drain electrode (nickel silicide) 28 and the semiconductor layer (P-type silicon substrate 21), the vicinity of the metal source / drain electrode 28 is obtained. As a result of the ionization of cesium, the height of the energy barrier against holes is increased. As a result, the leakage current between the source / drain and the semiconductor layer can be significantly reduced as compared with the Schottky junction. At the same time, the Schottky barrier height for the electrons between the channel and the source / drain is effectively reduced and the Schottky barrier thickness is reduced, so that the parasitic resistance can be significantly reduced compared to a Schottky junction. .

  In addition, since cesium is not a silicon donor and acceptor, cesium is not ionized in a region sufficiently separated from the metal source / drain electrode 28 in the cesium-containing region 27. Therefore, it is not necessary to extremely reduce the thickness of the cesium-containing region 27 between the metal source / drain electrode 28 and the semiconductor layer (P-type silicon substrate 21) (that is, there is no restriction when cesium is ion-implanted). Therefore, it is not necessary to use an impurity segregation technique as disclosed in Patent Document 1.

  As described above, in the semiconductor device of this embodiment, the thickness of the metal silicide (metal source / drain electrode) can be determined without restriction by ion implantation, so that a very shallow source / drain can be formed. The effect can be suppressed very well.

  Further, since the N-type impurity-containing region 25 having an impurity concentration that does not completely deplete is formed in contact with the source and drain at a position away from the channel region, the leakage current is further increased without causing a large increase in parasitic capacitance. Can be reduced. Further, by forming a contact hole in the upper part of the N-type impurity containing region 25, it is possible to prevent excessive etching due to etching variation at the time of forming the contact hole, and the etching penetrates the nickel silicide 28, so that the upper electrode is formed. Directly connected to the P-type silicon substrate 21 can prevent an increase in leakage current. Therefore, since the nickel silicide 28 can be formed thin, the short channel effect can be suppressed extremely well.

(Third embodiment)
In the third embodiment, the present invention is applied to an FET having a three-dimensional channel structure such as a Fin-FET (three-dimensional structure-FET (Field Effect Transistor)), a tri-gate-FET, and a nanowire-FET. It is.

  13A to 13E are cross-sectional views during each manufacturing process of the semiconductor device of the third embodiment. Hereinafter, the method for manufacturing the semiconductor device of this embodiment will be described with reference to FIGS. 13A to 13E.

  First, as shown in FIG. 13A, in an SOI substrate in which silicon 31, silicon oxide 32 as an example of an insulator, and silicon as an SOI layer are stacked in this order, the SOI layer is patterned to form alphabetical characters. A semiconductor region 33 as an example of the “I” -shaped semiconductor layer is formed. The thickness of the SOI layer (semiconductor region 33) is, for example, 20 nm. Further, the width (Fin width) of the region to be a channel in the semiconductor region 33 is, for example, 10 nm.

  Next, as shown in FIG. 13B, a gate insulating film 34 made of silicon oxide is formed on the surface of the semiconductor region 33 by using a thermal oxidation method, a CVD method, an ALD method, or the like. Subsequently, an N-type polycrystalline silicon film is deposited on the gate insulating film 34 using a CVD method or the like. Next, the gate electrode 35 is formed by patterning the polycrystalline silicon film using a lithography method, an RIE method, or the like. Subsequently, the gate insulating film 34 in a region not covered with the gate electrode 35 is removed by wet etching or the like using a hydrofluoric acid aqueous solution.

  As the material of the gate insulating film 34, silicon oxynitride, silicon nitride, hafnium oxide, lanthanum oxide, or a material containing nitrogen, silicon, aluminum, or the like may be used instead of silicon oxide. . Further, although polycrystalline silicon is used as the material of the gate electrode 35, amorphous silicon, germanium, silicon containing germanium, or the like may be used.

Next, as shown in FIG. 13C, for example, in PE-CVD (Plasma Enhanced CVD) method, 300 mTorr to 600 mTorr, gas flow rate ratio SiH ₄ / NH ₃ = 0.04 to 1.5, substrate temperature 300 ° C. to 450 A silicon nitride film is formed under the conditions of ° C. and plasma power of 40 W to 100 W. At this time, positive fixed charges are formed in the silicon nitride film. Thin silicon nitride may be formed by nitriding the silicon surface by exposing radicals containing nitrogen element or plasma to the silicon surface. The refractive index of silicon nitride is preferably 2.1 or higher. In this case, the density of positive fixed charges is very high. Subsequently, the gate sidewall film 36 containing positive fixed charges is formed by etching back by the RIE method. The material of the gate sidewall film 36 may be anything as long as it is an insulator containing a fixed charge.

  The positive fixed charge in the gate sidewall film 36 can also be formed as follows. For example, instead of the silicon nitride film, after forming a silicon oxide film by a CVD method or the like, an impurity that becomes a positive fixed charge such as cesium or the like is introduced into the silicon oxide by an ion implantation method or the like, Etching back by the RIE method or the like can form the gate sidewall film 36 containing positive fixed charges.

  In addition, a fixed film is formed by etching back a laminated film in which an insulating film such as silicon oxide, silicon nitride, or silicon oxynitride is deposited on the insulating film including the fixed charge formed by the above-described method. The gate sidewall film 36 including the gate sidewall film 36 may be formed.

  As described above, when the gate sidewall film 36 includes a positive fixed charge, even when at least one of the metal source / drain electrodes formed in a later process is offset with respect to the gate electrode 35 due to process variations or the like. Since the electron carrier layer is formed on the silicon surface as the semiconductor under the gate side wall film 36 including the fixed charge, the channel region and the metal source / drain electrode can be ohmically connected via the electron carrier layer, An increase in parasitic resistance can be prevented. Thereby, the yield can be dramatically improved. Since the electron carrier layer is extremely thin, the short channel effect characteristic is not deteriorated.

Next, as shown in FIG. 13D, cesium-containing region 37 is formed by ion-implanting cesium, for example, under the conditions of an acceleration energy of 5 keV and a dose of 1 × 10 ¹⁴ cm ⁻² . The ion implantation conditions are not limited to the above conditions, but are set so that the cesium-containing region 37 extends at least to the boundary with the silicon oxide 32. When the semiconductor region 33 is amorphized over the entire thickness direction of the SOI layer by ion implantation, the amorphized region is polycrystallized by heat treatment in a later process, and leakage current and parasitic resistance are increased. Will increase. However, by selecting the acceleration energy so that the concentration peak of cesium (impurity that modulates the Schottky barrier) is located in a region shallower than the center in the thickness direction of the SOI layer, the semiconductor region 33 is in the thickness direction of the SOI layer. It is possible to prevent the entire region from being amorphous and to maintain the crystallinity of at least the semiconductor region 33 in the region in contact with the silicon oxide 32. In this case, solid phase growth of single crystal silicon is promoted by heat treatment in a later step, and the amorphous region can be single crystallized (implantation damage can be recovered).

  Note that as the thickness of the SOI layer or the Fin width decreases, the semiconductor region 33 is likely to be amorphous throughout the thickness direction of the SOI layer by ion implantation, and the above-described polycrystallization is likely to occur. As the gate length is reduced, the fin width (and SOI layer thickness) needs to be reduced in order to suppress the short channel effect, and thus the problem of polycrystallization becomes more prominent with the progress of miniaturization in the future. . In this embodiment, since cesium (mass number 133) larger than the mass number 75 of arsenic which is a normal donor impurity is used, ions can be implanted into a region shallower than the arsenic with the same ion implantation energy. Therefore, compared with the case where the source / drain is formed by a high-concentration impurity region such as arsenic or the case where the impurity segregation technique as disclosed in Patent Document 1 is used, the SOI layer is made amorphous throughout the thickness direction. Is difficult to occur, and it is easy to prevent the polycrystallization. After that, annealing may be performed to recover the implantation damage. In that case, for example, RTA method, FLA method, laser annealing method or the like is used.

  Next, as shown in FIG. 13E, after depositing nickel, for example, about 3 nm to 4 nm by sputtering or the like, it is annealed and silicided at 260 ° C. to 350 ° C. for 30 seconds to 200 seconds. Prior to annealing, TiN may be deposited on nickel by sputtering or the like. Thereafter, unreacted nickel (and TiN) is removed to form nickel silicide 38 as an example of a metal source / drain electrode. Thereafter, the nickel silicide 38 is lowered in resistance by annealing under conditions of 350 ° C. to 500 ° C. and 30 seconds to 200 seconds. In this embodiment, the nickel silicide 38 is formed so that all silicon is nickel-silicided in the thickness direction of the SOI layer in the narrowest region (Fin region) of the semiconductor region 33. Only the surface portion of the region 33 may be nickel-silicided (in this case, the sectional view taken along the line DD ′ in FIG. 13E is FIG. 16 instead of FIG. 14). Further, the entire semiconductor region 33 excluding the channel region may be nickel-silicided (in this case, the sectional view taken along the line DD ′ in FIG. 13E is FIG. 17 instead of FIG. 14). In either case, the cesium ion implantation conditions and the formation conditions of the nickel silicide 38 are set so that the nickel silicide (hereinafter also referred to as a metal source / drain electrode) 38 contacts the semiconductor region 33 via the cesium-containing region 37. Just decide. The nickel silicide 38 is formed in a region about 3 times the thickness of the sputtered nickel (for example, about 9 nm to 12 nm) from the silicon surface. Thereafter, finally, an interlayer insulating film (not shown), an upper wiring (not shown), and the like are formed by a known method, thereby completing the semiconductor device. In this semiconductor device, FIG. 14 shows a cross-sectional view taken along the line DD ′ of FIG. 13E, and FIG. 15 shows a cross-sectional view taken along the line EE ′ of FIG.

  The nickel silicide 38 functions as a source / drain. When the nickel silicide 38 is formed, the gate electrode 35 is also silicided to form a nickel silicide 39. In this case, the gate electrode 35 may be entirely silicided to have a metal gate structure. In the case of a metal gate structure, the polycrystalline silicon film may be either i-type or P-type.

  When cobalt silicide is formed instead of nickel silicide 38 as the metal source / drain electrode, after depositing about 5 nm of cobalt by sputtering or the like, annealing is performed under conditions of 400 ° C. to 600 ° C. and 30 seconds to 200 seconds. To silicide the cobalt. Prior to annealing, TiN may be deposited on cobalt by sputtering or the like. Then, after removing unreacted cobalt (and TiN), the resistance of cobalt silicide may be reduced by annealing at 700 ° C. to 900 ° C. for 30 seconds to 200 seconds. Also in this case, the metal source / drain electrode (cobalt silicide) is formed so as to be in contact with the semiconductor layer (semiconductor region 33) through the cesium-containing region 37. The cobalt silicide is preferably formed from the silicon surface in a region about twice the thickness of the sputtered cobalt film (for example, about 10 nm).

  The case where the metal source / drain electrodes are nickel silicide 38 and cobalt silicide has been described above, but the metal source / drain electrodes are not limited to these. For example, the metal source / drain electrode may be made of a metal silicide using a metal composed of one or more elements of Ni, Co, Ti, Er, Yb, and Pt.

  According to the semiconductor device of this embodiment, since the cesium-containing region 37 is formed between the metal source / drain electrode (nickel silicide) 38 and the semiconductor layer (semiconductor region 33), the cesium near the metal source / drain electrode 38 is formed. As a result of ionization, the energy barrier height against holes increases, and as a result, the leakage current between the source / drain and the semiconductor layer can be significantly reduced as compared with the Schottky junction. At the same time, the Schottky barrier height for the electrons between the channel and the source / drain is effectively reduced and the Schottky barrier thickness is reduced, so the parasitic resistance is significantly reduced compared to a Schottky junction. can do.

  In addition, since cesium is not a silicon donor and acceptor, cesium is not ionized in a region sufficiently separated from the metal source / drain electrode 38 in the cesium-containing region 37. Therefore, there is no need to extremely reduce the thickness of the cesium-containing region 37 between the metal source / drain electrode 38 and the semiconductor layer (semiconductor region 33) (that is, there is no restriction when ion-implanting cesium). It is not necessary to use an impurity segregation technique as disclosed in Patent Document 1.

  As described above, according to the semiconductor device of the present embodiment, since the short channel effect characteristic is not deteriorated due to the diffusion of the donor impurity, an extremely good short channel effect characteristic can be obtained even in a three-channel FET. is there.

  Note that when a planar transistor is formed using an SOI substrate, the same cross-sectional structure as that in FIG. 17 can be obtained. In each of the above embodiments, the cesium-containing regions 5, 27, and 37 are regions of the P-type silicon substrates 1 and 21 and the semiconductor (silicon) region 33 that are in contact with the metal source / drain electrodes 6, 28, and 38. It is formed in all. However, the present invention is not limited to all of the “contact region”, and the same effect can be obtained even if it is formed on a part of the “contact region”.

  Of course, a new embodiment can be configured by combining a part or all of two or more different embodiments described above, and the invention of a certain embodiment and the invention of a modification are combined. Of course, a new embodiment can be configured by the invention created in this manner. In addition, the invention is created by combining two or more invention specific matters from the contents configured in all the embodiments and all the modifications performed in the description of the above specification, and constitutes a new embodiment of the present invention. Of course, we can do it.

1,21 P-type silicon substrate 2,22,34 Gate insulating film 3,23,35 Gate electrode 4a, 4b, 24,26,36 Gate sidewall film 5a, 5b, 12,27,37 Cesium containing region 6a First metal Source / drain electrode 6b Second metal source / drain electrode 11 P-type silicon 13, 28, 29, 38, 39 Nickel silicide 25 N-type impurity-containing region 31 Silicon 32 Silicon oxide 33 Semiconductor region

Claims (17)

A semiconductor layer;
A gate electrode formed on the semiconductor layer via a gate insulating film;
A first metal source / drain electrode formed on the semiconductor layer and on one side of the gate electrode;
A second metal source / drain electrode formed on the semiconductor layer and on the other side of the gate electrode;
An insulating gate sidewall film provided on the side surface of the gate electrode,
A part or all of the region in contact with the first and second metal source / drain electrodes in the semiconductor layer is a cesium-containing region containing cesium,
A semiconductor device characterized in that positive fixed charges exist in the gate sidewall film. The semiconductor device according to claim 1,
The semiconductor device, wherein the semiconductor layer is made of a semiconductor having an electron affinity greater than 3.89 eV. The semiconductor device according to claim 1 or 2,
The semiconductor device is characterized in that the semiconductor layer is made of any one of silicon, germanium, silicon germanium, gallium arsenide, and gallium nitride. The semiconductor device according to any one of claims 1 to 3,
At least a part of the fixed charge is cesium. 5. The semiconductor device according to claim 1, wherein:
A semiconductor device characterized in that the gate insulating film contains a nitrogen element. The semiconductor device according to any one of claims 1 to 5,
The semiconductor device, wherein a concentration of the cesium at the interface between the first metal source / drain electrode and the second metal source / drain electrode in the cesium-containing region is 1 × 10 ¹⁹ cm ⁻³ or more. The semiconductor device according to any one of claims 1 to 6,
The concentration of the cesium in the cesium-containing region has a peak at a position deeper than the interface between the first metal source / drain electrode and the second metal source / drain electrode in the cesium-containing region. Semiconductor device. The semiconductor device according to any one of claims 1 to 7,
Each of the first metal source / drain electrode and the second metal source / drain electrode is composed of a compound of the semiconductor layer and a metal. The semiconductor device according to claim 8,
The semiconductor layer includes at least one of silicon and germanium,
The semiconductor device includes one or more of nickel, cobalt, titanium, erbium, and ytterbium. The semiconductor device according to any one of claims 1 to 9,
The semiconductor layer is provided on an insulator,
At least a part of the first metal source / drain electrode and the second metal source / drain electrode is in contact with the insulator. A manufacturing method of a semiconductor device for manufacturing the semiconductor device according to claim 1,
Forming a gate electrode on the semiconductor layer via a gate insulating film;
Forming an insulating layer on the surface of the semiconductor layer and on both sides of the gate electrode;
Introducing cesium into the insulating layer;
Anisotropically etching the insulating layer so that part of the surface of the semiconductor layer is exposed to form a gate sidewall film made of the insulating layer;
Introducing cesium into a region where the surface of the semiconductor layer is exposed to form a cesium-containing region;
Forming the first and second metal source / drain electrodes so as to be in contact with the cesium-containing region. A manufacturing method of a semiconductor device for manufacturing the semiconductor device according to claim 1,
Forming a gate electrode on the semiconductor layer via a gate insulating film;
At least a region adjacent to the gate electrode on the surface of the semiconductor layer is exposed to an atmosphere containing at least one of a gas containing an oxidant composed of molecules containing nitrogen, nitrogen radicals, and nitrogen elements in a plasma state. Forming an insulating layer and forming a positive fixed charge;
Anisotropically etching the insulating layer such that a part of the surface of the semiconductor layer is exposed to form a gate sidewall made of the insulating layer;
Introducing cesium into a region where the surface of the semiconductor layer is exposed to form a cesium-containing region;
Forming the first and second metal source / drain electrodes so as to be in contact with the cesium-containing region. A manufacturing method of a semiconductor device for manufacturing the semiconductor device according to claim 1,
Forming a gate electrode on the semiconductor layer via a gate insulating film;
Introducing cesium into the upper part of the semiconductor layer and both sides of the gate electrode to form a cesium-containing region;
Forming a positive fixed charge by causing the cesium-containing region to react with other elements to form an insulating layer, thereby segregating the cesium to the interface between the semiconductor layer and the insulating layer;
Etching a part of the insulating layer to form an opening in the insulating layer so that at least a part of the surface of the cesium-containing region in the semiconductor layer is exposed;
Forming the first and second metal source / drain electrodes so as to be in contact with the cesium-containing region. A manufacturing method of a semiconductor device for manufacturing the semiconductor device according to claim 1,
Forming a gate electrode on the semiconductor layer via a gate insulating film;
Introducing cesium into the upper part of the semiconductor layer and both sides of the gate electrode to form a cesium-containing region;
Forming an insulating layer so as to cover at least a region adjacent to the gate electrode in the surface of the cesium-containing region;
Forming a positive fixed charge by segregating the cesium by annealing at the interface between the insulating layer and the semiconductor layer;
Etching a part of the insulating layer to form an opening in the insulating layer so that at least a part of the surface of the cesium-containing region in the semiconductor layer is exposed;
Forming the first and second metal source / drain electrodes so as to be in contact with the cesium-containing region. A manufacturing method of a semiconductor device for manufacturing the semiconductor device according to claim 1,
Forming a gate electrode on the semiconductor layer via a gate insulating film;
Forming an insulating layer on the surface of the semiconductor layer and on both sides of the gate electrode;
Introducing cesium into both sides of the gate electrode and the insulating layer above the semiconductor layer to form a cesium-containing region and forming a positive fixed charge in the insulating layer;
Etching part of the insulating layer to form an opening in the insulating layer so that at least part of the surface of the cesium-containing region in the semiconductor layer is exposed;
Forming the first and second metal source / drain electrodes so as to be in contact with the cesium-containing region. In the manufacturing method of the semiconductor device according to any one of claims 11 to 15,
The step of forming the first and second metal source / drain electrodes includes:
Depositing a metal on the cesium-containing region;
Performing annealing to react the semiconductor layer with the metal;
And a step of removing unreacted portions of the metal. In the manufacturing method of the semiconductor device according to claim 16,
The semiconductor layer includes at least one of silicon and germanium,
The method for manufacturing a semiconductor device, wherein the metal includes one or more of nickel, cobalt, titanium, erbium, and ytterbium.

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