TWI637526B - Semiconductor device and method for forming the same - Google Patents

Semiconductor device and method for forming the same

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Publication number
TWI637526B
TWI637526B TW106113409A TW106113409A TWI637526B TW I637526 B TWI637526 B TW I637526B TW 106113409 A TW106113409 A TW 106113409A TW 106113409 A TW106113409 A TW 106113409A TW I637526 B TWI637526 B TW I637526B
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Taiwan
Prior art keywords
region
semiconductor substrate
semiconductor device
gate structure
forming
Prior art date
Application number
TW106113409A
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Chinese (zh)
Other versions
TW201840002A (en
Inventor
王琮玄
陳侃昇
吳信霖
周永隆
魏雲洲
李家豪
廖志成
Original Assignee
世界先進積體電路股份有限公司
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Priority to TW106113409A priority Critical patent/TWI637526B/en
Application granted granted Critical
Publication of TWI637526B publication Critical patent/TWI637526B/en
Publication of TW201840002A publication Critical patent/TW201840002A/en

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Abstract

The present disclosure relates to a semiconductor device including a gate structure disposed on a semiconductor substrate, a sidewall spacer disposed on a sidewall of the gate structure, and a lightly doped source formed in a semiconductor substrate on both sides of the gate structure a pole/drain region, a source/drain region formed in a semiconductor substrate on both sides of the sidewall spacer, a semiconductor substrate formed under the gate structure and adjacent to the lightly doped source/drain region a halo implant region, a reverse doped region formed in the semiconductor substrate under the gate structure and located between the lightly doped source/drain region and the halo implant region (counter -doping region). The doping concentration of the counter doped region is lower than the doping concentration of the halo implant region.

Description

Semiconductor device and method of forming same

The present disclosure relates to a semiconductor device, and more particularly to a semiconductor device having a halo implant region and a method of forming the same.

Semiconductor devices have been widely used in various electronic products such as, for example, personal computers, mobile phones, and digital cameras. The semiconductor device is usually fabricated by sequentially depositing an insulating layer or a dielectric layer material, a conductive layer material, and a semiconductor layer material on a semiconductor substrate, and then patterning the various material layers formed by using a lithography process, whereby the semiconductor substrate is formed thereon. Circuit parts and components are formed on top.

During the evolution of semiconductor devices, the continued reduction in geometry poses some challenges for semiconductor fabrication, such as leakage current between source and drain and reverse short channel effect. If the above leakage current is too large, the life of the device will be lowered. In general, the doping concentration of the well region can be increased to reduce the leakage current, however this will make the threshold voltage of the semiconductor device large and unfavorable for operation. In addition, if the above-mentioned inverse short channel effect is too severe, the difference in threshold voltages of the short-channel and the long-channel of the semiconductor device may increase, causing design difficulties.

Therefore, although current semiconductor devices and their fabrication are generally full It is intended for its intended use, but it is not satisfactory at all levels.

The present disclosure provides a semiconductor device including: a semiconductor substrate; a gate structure disposed on the semiconductor substrate; a sidewall spacer disposed on a sidewall of the gate structure; and a lightly doped source/drain region formed on a semiconductor substrate on both sides of the gate structure; a source/drain region formed in a semiconductor substrate on both sides of the sidewall spacer; a halo implant region, a semiconductor formed under the gate structure In the substrate and adjacent to the lightly doped source/drain region; a counter-doping region formed in the semiconductor substrate under the gate structure and located at the lightly doped source/drain Between the area and the halo implanted area. The doping concentration of the counter doped region is lower than the doping concentration of the halo implant region.

The disclosure also provides a method for forming a semiconductor device, comprising: providing a semiconductor substrate; forming a gate structure on the semiconductor substrate; forming a halo implant region in the semiconductor substrate around the gate structure and under the gate structure; Forming a lightly doped source/drain region in the semiconductor substrate on both sides of the gate structure, wherein the halo implant region is adjacent to the lightly doped source/drain region; forming sidewall spacers on the gate structure Forming a source/drain region in the semiconductor substrate on both sides of the sidewall spacer; and forming a counter-doping region in the semiconductor substrate under the gate structure and located at the light Doped between the source/drain region and the halo implant region. The doping concentration of the counter doped region is lower than the doping concentration of the halo implant region.

100‧‧‧Semiconductor substrate

200‧‧‧ Well Area

300‧‧‧ gate structure

302‧‧‧ gate dielectric layer

304‧‧‧gate electrode

400‧‧‧Hao implant area

600‧‧‧Lightly doped source/drain regions

700‧‧‧ sidewall spacers

702‧‧‧Back doped area

800‧‧‧Source/Bungee Area

C‧‧‧ gate structure centerline

D‧‧‧First impurity

Embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. Note It is intended that the various features are not &quot In fact, the dimensions of the components may be enlarged or reduced to clearly show the technical features of the present disclosure.

Figures 1-6, 7A, 7B, and 8 are a series of cross-sectional views for explaining the manufacturing process of the semiconductor device of the disclosed embodiment.

The following disclosure provides many different embodiments or examples to implement various features of the present invention. The following disclosure sets forth specific examples of various components and their arrangement to simplify the description. Of course, these specific examples are not intended to be limiting. For example, if the disclosure describes a first feature formed on or above a second feature, that is, it may include an embodiment in which the first feature is in direct contact with the second feature, and may also include additional Features are formed between the first feature and the second feature described above, such that the first feature and the second feature may not be in direct contact with each other. In addition, the following different reference numerals and/or labels may be repeatedly used in different embodiments. These repetitions are not intended to limit the specific relationship between the various embodiments and/or structures discussed. It will be appreciated that additional operational steps may be performed before, during or after the method, and that in other embodiments of the method, portions of the operational steps may be substituted or omitted.

The method for forming a semiconductor device according to the present disclosure is to form a counter-doping region in a semiconductor substrate under a gate structure, and to make the doping concentration of the opposite doped region lower than halo The doping concentration of the implanted region, whereby the inverse short channel effect can be reduced. In addition, as described above, in order to reduce the leakage current between the source and the drain (or increase the ratio of I on /I off ), the doping concentration of the well region must be sufficient, and the semiconductor device of the present disclosure is applied to the gate The positive charge formed in the lower portion of the electrical layer can avoid or reduce the rise in the threshold voltage of the semiconductor device due to the increase in the doping concentration of the well region. In the following, an N-type metal oxide semiconductor field effect transistor (NMOS) will be described as an example. It should be understood that the person skilled in the art can also apply it to a P-type oxide semiconductor field effect transistor (PMOS), which is complementary. Metal oxide semiconductor transistor (CMOS), high voltage transistor, horizontally diffused gold oxide half field effect transistor (LDMOS), or other suitable semiconductor component.

Figure 1 illustrates the initial steps of an embodiment of the present disclosure. First, a semiconductor substrate 100 is provided. For example, the semiconductor substrate 100 may include germanium. In some other embodiments, the semiconductor substrate 100 may include an elemental semiconductor other than germanium, such as germanium; a compound semiconductor such as silicon carbide (SiC), gallium arsenic (GaAs), indium arsenide. (indium arsenide, InAs) or indium phosphide (InP); alloy semiconductors such as: Silicon germanium (SiGe), silicon germanium carbide (SiGeC), gallium arsenic phosphide , GaAsP) or gallium indium phosphide (GaInP). The semiconductor substrate 100 may further include a semiconductor-on-insulator (SOI), and the semiconductor substrate on the insulating layer may include a bottom plate, a buried oxide layer disposed on the bottom plate, and a semiconductor disposed on the buried oxide layer. Floor.

Next, as shown in FIG. 2, well region impurities are implanted in the semiconductor substrate 100 to form the well region 200. The well pattern of the well region 200 is matched to the conductivity pattern of the semiconductor component to be formed in the well region 200. In this embodiment, an N-type field effect transistor (NMOS) is subsequently formed in the well region 200, so that the well region impurity of the well region 200 is a P-type impurity, for example, implanting boron ions, Indium ions or boron difluoride ions (BF 2 + ) are implanted in a portion of the semiconductor substrate 100 to form a P-type well region 200 having a doping concentration of 1E12-7E13 atoms/cm 2 . For example, the depth of the well region 200 may be 0.03 um - 0.75 um, but is not limited thereto.

Next, as shown in FIG. 3, a gate structure 300 is formed over the well region 200. The gate structure 300 can include a gate dielectric layer 302 and a gate electrode 304 disposed on the gate dielectric layer 302. For example, the gate dielectric layer 302 may include a hafnium oxide or a high-k dielectric material such as hafnium oxide (HfO 2 ), hafnium silicon oxide (HfSiO), or hafnium oxynitride. (hafnium silicon oxynitride; HfSiON), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (HfZrO), silicon nitride, nitrogen Silicon oxynitride, zirconium oxide, titanium oxide, aluminum oxide, hafnium dioxide-alumina (HfO 2 -Al 2 O 3 ) alloy, Or other suitable dielectric materials, but not limited to this. For example, the gate electrode 304 may include polysilicon, aluminum, copper, tungsten, titanium, tantalum, titanium nitride, tantalum nitride, nickel silicide, cobalt silicide. ), tantalum carbide (TaC), tantalum nitride (TaSiN), tantalum nitride (TaCN), titanium aluminum (TiAl), titanium aluminum nitride (TiAlN), or other suitable materials.

The process of forming the gate structure 300 can include deposition, photolithographic patterning, and etching processes. The deposition process may include chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), high density plasma chemical vapor deposition (HDPCVD), metal organic chemical vapor deposition. (metal organic CVD; MOCVD), or plasma enhanced CVD (PECVD). The photolithographic patterning process can include photoresist coating (eg, spin coating), soft bake, mask alignment, exposure, post-exposure baking, photoresist development, cleaning, drying (eg: Hard baked), and/or other suitable processes. The etching process can include dry etching, wet etching, and/or other etching methods (eg, reactive ion etching).

Next, as shown in FIG. 4, a halo implant region 400 is formed in the semiconductor substrate 100 around the gate structure 300 and under the gate structure 300. The halo implant region 400 includes impurities of the same conductivity type as the well region 200. In the present embodiment, the halo implant region 400 includes a P-type impurity. For example, a boron implant, a boron ion, or a boron difluoride ion (BF 2 + ) can be implanted by a tilt implant process. A halo implant region 400 having a doping concentration of 1E13 to 4.5E13 atoms/cm 2 is formed in the semiconductor substrate 100, and an angle between an ion incident direction and a normal line of the upper surface of the semiconductor substrate may be 20° to 50°. In some embodiments, the doping concentration of the halo implant region 400 gradually decreases toward the centerline C of the gate structure.

Next, as shown in FIG. 5, the first impurity D is implanted in the gate electrode 304 and the semiconductor substrate 100. For example, the first impurity D may include nitrogen ions. In the present embodiment, nitrogen ions can be implanted in the gate electrode 304 and the semiconductor substrate 100 by an implantation process. If the planting energy of the above-mentioned planting process is too high, it will affect the part of the deeper well zone, which may cause deep leakage of the component or reduce the isolation effect from the adjacent well zone. If it is too low, it will affect the component characteristics. For example, the above cloth The planting energy of the planting process can be 6keV~40keV, preferably 10keV~30keV. If the implantation dose of the above-mentioned planting process is too high, the critical voltage of the original component will be rapidly lowered, and the difference of the threshold voltage of the long/short channel component will increase. If it is too low, the effect is not good. For example, the above-mentioned implantation process is The implantation dose may be 1E14-1E16 atoms/cm 2 , preferably 5E14-6E15 atoms/cm 2 .

Next, referring to FIG. 6, a lightly doped source/drain region 600 is formed in the semiconductor substrate 100 on both sides of the gate structure 300, and is adjacent to the halo implant region 400. The lightly doped source/drain region 600 includes impurities of opposite conductivity to the well region 200. In the present embodiment, the lightly doped source/drain region 600 includes an N-type impurity. For example, the gate structure 300 can serve as an implant mask to implant phosphorous or arsenic ions in the semiconductor substrate 100 on both sides of the gate structure 300 to form an N-type light having a doping concentration of 1E14-6E14 atoms/cm 2 . The source/drain region 600 is doped. It should be noted that, in the present embodiment, the step of implanting nitrogen ions in the gate electrode 304 and the semiconductor substrate 100 in the above FIG. 5 is performed before the step of forming the lightly doped source/drain region 600. In some other embodiments, the step of implanting nitrogen ions may be performed after the step of forming the lightly doped source/drain regions 600.

Next, referring to FIG. 7A, sidewall spacers 700 are formed on the sidewalls of the gate structure 300. For example, the sidewall spacers 700 include one or more layers of insulating material (eg, SiO 2 , SiN, SiON, SiOCN, or SiCN), which may be a chemical vapor deposition process (CVD), a physical vapor deposition process (PVD), A spacer vapor deposition process (ALD), electron beam evaporation process (e-beam evaporation), or other suitable process for depositing a spacer layer, followed by an anisotropic etchback process (eg, plasma etching process) ) formed. In the present embodiment, the process of depositing the sidewall spacer layer is performed at a temperature of 625 to 750 ° C, so that the nitrogen ions implanted in the semiconductor substrate 100 in the above FIG. 5 can be obtained without an additional heat step. A diffusion-driven halo implant region 400 is adjacent to a portion of the lightly doped source/drain region 600 to form a counter-doping region 702, as shown in FIG. 7B.

In the counter doped region 702, the diffusion-driven nitrogen ions can appropriately reduce the doping concentration of the P-type impurity in the original halo implant region to 15%-80%, in some embodiments, It is reduced to 40%-80% of the original and is suitable for general threshold voltage (for example: critical voltage is 0.37-0.45 volts) semiconductor, in other embodiments, it is reduced to 15%-50% and is suitable for low A threshold voltage (for example, a threshold voltage of 0.21 to 0.285 volts) semiconductor. In some embodiments, diffusion-driven nitrogen ions can appropriately reduce the doping concentration of the P-type impurities in the original halo implant region to 15%-80%, and reduce the effect of the reverse channel effect. For example, the halo implant region 400 and the counter doped region 702 have a doping concentration ratio of 20:3 to 20:16. In some embodiments, unlike the halo implant region 400, the doping concentration of the counter doped region 702 gradually increases toward the centerline C of the gate structure 300.

In addition, referring to FIG. 7B, the temperature at which the sidewall spacer process is formed in this embodiment may also cause the diffusion of nitrogen ions implanted in the gate electrode 304 in the fifth embodiment to be driven into the gate dielectric layer 302. A positive charge is formed on the lower portion of the gate dielectric layer 302. The positive charge described above can avoid or reduce the increase in the threshold voltage of the semiconductor device due to an increase in the doping concentration of the well region 200 (eg, to reduce leakage current between the source and the drain).

It should be noted that although the present embodiment is in the process of forming the sidewall spacers 700, the positive doping in the reverse doped region 702 and the lower portion of the gate dielectric layer 302 is formed at its process temperature, however, in some other In the examples, an additional heat treatment step may also be performed to achieve the same purpose.

Next, referring to FIG. 8, the source/drain regions 800 are formed in the semiconductor substrate 100 on both sides of the sidewall spacers 700. In the present embodiment, the source/drain region 800 includes N-type impurities. For example, the gate structure 300 and the sidewall spacers 700 can serve as an implant mask to implant phosphorous or arsenic ions into the sidewall spacers 700. In the semiconductor substrate 100 on both sides, a heat treatment step is then performed to activate the dopant to form an N-type source/drain region 800 having a doping concentration of 8E13-4.5E15 atoms/cm 2 . For example, the heat treatment step may be a rapid thermal process (RTP), and the heat treatment temperature may be 1000-1100 ° C, and the time may be 1 s-20 s. The heat treatment step may also be a furnace anneal, a Laser Spike Annealing (LSA) process, a Laser Thermal Processing (LTP) or other suitable heat treatment. Process. In some embodiments, the heat treatment process may also drive the diffusion of nitrogen ions implanted in the fifth image into the halo implant region 400 and the gate dielectric layer 302.

In summary, the semiconductor device of the present disclosure forms a counter-doping region between the semiconductor substrate under the gate structure and the lightly doped source/drain region and the halo implant region. And the doping concentration of the reverse doped region is lower than the doping concentration of the halo implant region, and the inverse short channel effect can be reduced. In addition, the positive charge formed by the semiconductor device of the present disclosure in the lower portion of the gate dielectric layer can avoid or reduce the threshold voltage rise of the semiconductor device caused by the increase of the doping concentration of the well region.

The foregoing summary of the invention is inferred by the claims It should be understood by those of ordinary skill in the art, and other processes and structures can be easily designed or modified based on the present disclosure to achieve the same purpose and/or Or the same advantages as the embodiments described herein are achieved. Those of ordinary skill in the art should also understand that such equivalent structures are not departing from the spirit and scope of the invention. Various changes, permutations, or alterations may be made in the present disclosure without departing from the spirit and scope of the invention. The scope of the present invention is defined by the scope of the appended claims. In addition, the present invention has been described above in terms of several preferred embodiments, which are not intended to limit the invention, and not all of the advantages thereof.

Claims (20)

  1. A semiconductor device comprising: a semiconductor substrate; a gate structure disposed on the semiconductor substrate; a sidewall spacer disposed on a sidewall of the gate structure; a lightly doped source/drain region formed And a source/drain region formed in the semiconductor substrate on both sides of the sidewall spacer; a halo implant region formed in the semiconductor substrate And adjacent to the lightly doped source/drain region, wherein the halo implant region extends into the semiconductor substrate under the gate structure; and a counter-doping region is formed in the In the semiconductor substrate under the gate structure and between the lightly doped source/drain region and the halo implant region; wherein the doping concentration of the counter doped region is lower than the halo implant region Doping concentration.
  2. The semiconductor device of claim 1, wherein the doping concentration of the counter doped region gradually increases toward a center line of the gate structure.
  3. The semiconductor device of claim 1, wherein the semiconductor device is an NMOS device, and the source/drain regions are N-type doped regions, the hazy implant region and the reverse doping The fauna is a P-type doped region.
  4. The semiconductor device of claim 3, wherein the NMOS device is formed in one of the P-type well regions of the semiconductor substrate.
  5. The semiconductor device according to claim 4, wherein the P-type well region has a doping concentration of 1E12 to 7E13 atoms/cm 2 .
  6. The semiconductor device of claim 3, wherein the gate structure comprises: a gate dielectric layer; and a gate electrode formed on the gate dielectric layer; wherein the gate dielectric One of the lower layers has a positive charge.
  7. The semiconductor device of claim 1, wherein the halo implant region and the counter doped region have a doping concentration ratio of 20:3 to 20:16.
  8. A method of forming a semiconductor device, comprising: providing a semiconductor substrate; forming a gate structure over the semiconductor substrate; forming a halo implant region in the semiconductor substrate surrounding the gate structure and extending into the gate structure In the lower semiconductor substrate; forming a lightly doped source/drain region in the semiconductor substrate on both sides of the gate structure, wherein the halo implant region is adjacent to the lightly doped source/drain region; a sidewall spacer on the sidewall of the gate structure; a source/drain region formed in the semiconductor substrate on both sides of the sidewall spacer; and a counter-doping region is formed on the gate a semiconductor substrate in a polar structure and located between the lightly doped source/drain region and the halo implant region; wherein the doping concentration of the counter doped region is lower than the blend of the halo implant region Miscellaneous concentration.
  9. The method of forming a semiconductor device according to claim 8, wherein a doping concentration of the counter doped region gradually increases toward a center line of the gate structure.
  10. The method of forming a semiconductor device according to claim 8, wherein the halo implant region and the counter doped region have a doping concentration ratio of 20:3 to 20:16.
  11. The method of forming a semiconductor device according to claim 8, wherein the semiconductor device is an NMOS device, and the source/drain region is an N-type doping region, the halo implant region and the opposite The doped region is a P-type doped region.
  12. The method for forming a semiconductor device according to claim 11, further comprising: implanting a P-type impurity in a well region to form a P-type well region in the semiconductor substrate; wherein the NMOS device is formed in the P-type In the well area.
  13. The method of forming a semiconductor device according to claim 11, wherein the gate structure comprises: a gate dielectric layer; a gate electrode formed on the gate dielectric layer; wherein the halo is formed The step of implanting a region includes: implanting a P-type impurity at an oblique angle to form the halo implant region in the semiconductor substrate around the gate structure and under the gate structure; wherein the reverse doped region is formed The method includes: implanting a first impurity in the gate electrode and the semiconductor substrate; and performing a heat treatment to drive the first impurity diffusion into the halo plant The inversion region is formed adjacent to a portion of the lightly doped source/drain region to form the counter doped region.
  14. The method of forming a semiconductor device according to claim 13, wherein the first impurity comprises nitrogen ions.
  15. The method of forming a semiconductor device according to claim 13, wherein the step of forming the sidewall spacer comprises: depositing the sidewall spacer on a sidewall of the gate structure at 625-750 ° C; wherein the heat treatment step It is carried out by the temperature at which the sidewall spacers are deposited.
  16. The method of forming a semiconductor device according to claim 13, wherein the step of implanting the first impurity in the gate electrode and the semiconductor substrate is to form the lightly doped source/drain region The steps in the semiconductor substrate are performed before.
  17. The method of forming a semiconductor device according to claim 13, wherein the step of implanting the first impurity in the gate electrode and the semiconductor substrate is to form the lightly doped source/drain region The steps in the semiconductor substrate are performed afterwards.
  18. The method for forming a semiconductor device according to claim 13, wherein the step of implanting the first impurity in the gate electrode and the semiconductor substrate is 6 keV to 40 keV and the implantation dose is 1E14- 1E16atoms/cm2.
  19. The method of forming a semiconductor device according to claim 13, wherein a lower portion of the gate dielectric layer has a positive charge.
  20. A method of forming a semiconductor device according to claim 19, which The positive charge in the lower portion of the gate dielectric layer is formed by the heat treatment step.
TW106113409A 2017-04-21 2017-04-21 Semiconductor device and method for forming the same TWI637526B (en)

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Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060141724A1 (en) * 2003-12-27 2006-06-29 Dongbuanam Semiconductor Inc. Method of manufacturing MOS transistor

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060141724A1 (en) * 2003-12-27 2006-06-29 Dongbuanam Semiconductor Inc. Method of manufacturing MOS transistor

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