JP7464864B2 - Fixed charge control method and thin film transistor manufacturing method - Google Patents
Fixed charge control method and thin film transistor manufacturing method Download PDFInfo
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Description
本発明は、固定電荷制御方法及び薄膜トランジスタの製造方法に関するものである。 The present invention relates to a fixed charge control method and a method for manufacturing a thin-film transistor.
近年、Ｉｎ－Ｇａ－Ｚｎ－Ｏ系（ＩＧＺＯ）等の酸化物半導体をチャネル層に用いた薄膜トランジスタ（ＴＦＴ）の開発が活発に行われている。 In recent years, there has been active development of thin-film transistors (TFTs) that use oxide semiconductors such as In-Ga-Zn-O (IGZO) in the channel layer.
このような薄膜トランジスタとして、例えば特許文献１には、チャネル層に接触するゲート絶縁層として、膜密度が小さい（２．７０～２．７９ｇ／ｃｍ３）酸化アルミニウムを用いるものが開示されている。この薄膜トランジスタでは、このような膜密度が小さい酸化アルミニウムを絶縁層とすることで、絶縁層の負の固定電荷密度を大きくでき、これにより薄膜トランジスタの閾値電圧を正方向へシフトさせ、信頼性を向上できることが記載されている。 As such a thin film transistor, for example, Patent Document 1 discloses one that uses aluminum oxide with a low film density (2.70 to 2.79 g/cm 3 ) as a gate insulating layer in contact with a channel layer. It is described that in this thin film transistor, by using aluminum oxide with such a low film density as an insulating layer, it is possible to increase the negative fixed charge density of the insulating layer, thereby shifting the threshold voltage of the thin film transistor in the positive direction and improving reliability.
しかしながら特許文献１に開示される薄膜トランジスタでは、絶縁層の膜密度を小さくすることにより、言い換えれば膜質を悪化させることにより必要な固定電荷を発現させるようにしているので、リーク電流の増大や環境変化による信頼性低下の恐れがある。 However, in the thin-film transistor disclosed in Patent Document 1, the necessary fixed charge is generated by reducing the film density of the insulating layer, in other words, by deteriorating the film quality, which may increase leakage current or reduce reliability due to environmental changes.
本発明はこのような問題に鑑みてなされたものであり、半導体デバイスに用いられる絶縁層内に、膜質の低下を抑えながら必要な固定電荷を効率よく生成することを主たる課題とするものである。 The present invention was made in consideration of these problems, and its main objective is to efficiently generate the necessary fixed charges in insulating layers used in semiconductor devices while suppressing deterioration of film quality.
すなわち本発明に係る固定電荷制御方法は、半導体デバイスに用いられる絶縁層内の固定電荷を制御する方法であって、前記絶縁層を形成した後、当該絶縁層の表層部にイオン注入を行い、当該イオン注入後の前記絶縁層の表面に金属膜又は絶縁膜からなるキャップ層を形成し、前記キャップ層が表面に形成された前記絶縁層に対して熱処理を行うことにより前記絶縁層中に固定電荷を発現させることを特徴とする。 That is, the fixed charge control method according to the present invention is a method for controlling fixed charges in an insulating layer used in a semiconductor device, and is characterized in that after forming the insulating layer, ions are implanted into the surface layer of the insulating layer, a cap layer made of a metal film or an insulating film is formed on the surface of the insulating layer after the ion implantation, and the insulating layer with the cap layer formed on its surface is subjected to a heat treatment to generate fixed charges in the insulating layer.
このような構成であれば、絶縁層の全体の膜質を変化させるのではなく、イオン注入により絶縁層の表層部だけの膜質を変化させて固定電荷を発現させるようにしているので、絶縁層の本来の絶縁特性をほぼ維持した状態で、部分的な機能の付加を行うことができる。またイオン注入を行うことにより絶縁層内には、注入イオンと、原子衝突により生成される欠陥とが分布するようになるが、上記構成であればイオン注入を行った絶縁層の表面に金属膜や絶縁膜から成るキャップ層が形成された状態で熱処理を行うようにしているので、絶縁層内の欠陥を修復するとともに、熱処理中における絶縁層内での遊離元素の結合を促進でき、効率よく必要な固定電荷を生成できる。そしてイオン注入を行う際のイオンの飛程やイオン種、又は熱処理の温度や時間等を調整することで、絶縁層内における固定電荷密度を容易に調整することができる。
なお、「キャップ層が表面に形成された絶縁層に対して熱処理を行う」とは、イオンが注入された絶縁層の表面がキャップ層により覆われている状態の絶縁層に対して熱処理を行うことを意味する。
In this configuration, the quality of the entire insulating layer is not changed, but only the quality of the surface layer of the insulating layer is changed by ion implantation to generate fixed charges, so that partial functions can be added while the original insulating properties of the insulating layer are almost maintained. In addition, by performing ion implantation, the injected ions and defects generated by atomic collisions are distributed in the insulating layer. In the above configuration, the heat treatment is performed in a state where a cap layer made of a metal film or an insulating film is formed on the surface of the insulating layer where ions are implanted, so that the defects in the insulating layer can be repaired and the bonding of free elements in the insulating layer during the heat treatment can be promoted, and the required fixed charges can be efficiently generated. In addition, the fixed charge density in the insulating layer can be easily adjusted by adjusting the range and type of ions when performing ion implantation, or the temperature and time of the heat treatment.
In addition, "performing a heat treatment on an insulating layer having a cap layer formed on its surface" means performing a heat treatment on an insulating layer in a state in which the surface of the insulating layer into which ions have been implanted is covered with a cap layer.
また前記固定電荷制御方法は、前記イオン注入によるイオンの平均飛程とその標準偏差の和が、前記絶縁層の厚みの半分より小さいのが好ましく、１／３以下であるのがより好ましい。
このようにすれば、注入イオンが絶縁層を通過して裏側に抜けることを防止でき、リークパスの形成を防止できる。
In the fixed charge control method, the sum of the average range of ions by the ion implantation and its standard deviation is preferably smaller than half the thickness of the insulating layer, and more preferably 1/3 or less.
In this way, the implanted ions can be prevented from passing through the insulating layer to the back side, and the formation of a leak path can be prevented.
前記固定電荷制御方法の効果を顕著に奏する前記絶縁層の具体的態様として、酸化膜、窒化膜又は酸窒化膜からなるものが挙げられる。 Specific examples of the insulating layer that exhibit the effects of the fixed charge control method include an oxide film, a nitride film, or an oxynitride film.
前記固定電荷制御方法では、前記キャップ層が、窒化膜又は酸窒化膜からなるものであるのが好ましい。
このようにすれば、ガス透過性が低い窒化膜や酸窒化膜等の絶縁膜をキャップ層として熱処理を行うことで、絶縁層内おける遊離元素の結合がより一層促進され、より効果的に固定電荷を発現できる。
In the fixed charge control method, the cap layer is preferably made of a nitride film or an oxynitride film.
In this way, by performing heat treatment using an insulating film such as a nitride film or an oxynitride film with low gas permeability as a cap layer, the bonding of free elements in the insulating layer is further promoted, and fixed charges can be more effectively generated.
また前記固定電荷制御方法では、前記キャップ層が、アルミニウム、アルミニウム合金、モリブデン、モリブデン合金、チタン又はチタン合金からなるものであるのが好ましい。
このようにすれば、ガス透過性が低い金属膜をキャップ層として熱処理を行うことで、金属の絶縁層内の元素との結合が促進され、より効果的に固定電荷を発現できる。
In the fixed charge control method, the cap layer is preferably made of aluminum, an aluminum alloy, molybdenum, a molybdenum alloy, titanium or a titanium alloy.
In this way, by performing heat treatment using a metal film with low gas permeability as a cap layer, bonding of the metal with elements in the insulating layer is promoted, and fixed charges can be more effectively generated.
また前記固定電荷制御方法は、前記絶縁層の表面に前記キャップ層を形成する際に生じる熱を利用して前記絶縁層の熱処理を行うのが好ましい。
このようにすれば、キャップ層を形成した後に、熱処理を行う工程を別途に設ける必要がないので、工程数を削減して低コスト化を図ることができる。
In the fixed charge control method, it is preferable to perform a heat treatment of the insulating layer by utilizing heat generated when the cap layer is formed on the surface of the insulating layer.
In this way, since there is no need to perform a separate step of heat treatment after forming the cap layer, the number of steps can be reduced, leading to lower costs.
前記固定電荷制御方法の効果を顕著に奏する前記イオン注入で注入するイオン種の具体的態様としては、Ｏ、Ｎ、Ｃ等の原子イオン、Ｏ２、Ｎ２、Ｃ２等の分子イオン、又はＡｒ等の希ガスイオンから選択される１種以上があげられる。 Specific examples of the ion species to be implanted in the ion implantation that significantly exhibits the effects of the fixed charge control method include one or more ions selected from atomic ions such as O, N, and C, molecular ions such as O 2 , N 2 , and C 2 , and rare gas ions such as Ar.
また本発明の薄膜トランジスタの製造方法は、酸化物半導体から成るチャネル層と、ゲート絶縁層と、ゲート電極層とが基板側から順に積層されたトップゲート型の薄膜トランジスタの製造方法であって、前記チャネル層を形成する工程と、前記チャネル層の表面に前記ゲート絶縁層を形成する工程と、前記ゲート絶縁層の表層部にイオン注入を行う工程と、イオン注入後の前記ゲート絶縁層の表面に、金属膜又は絶縁膜から成るキャップ層を形成する工程と、前記キャップ層が表面に形成された前記絶縁層に対して熱処理を行うことにより前記絶縁層中に負の固定電荷を発現させる工程とを含むことを特徴とする。 The method for manufacturing a thin-film transistor of the present invention is a method for manufacturing a top-gate type thin-film transistor in which a channel layer made of an oxide semiconductor, a gate insulating layer, and a gate electrode layer are stacked in this order from the substrate side, and is characterized by including the steps of forming the channel layer, forming the gate insulating layer on the surface of the channel layer, implanting ions into the surface portion of the gate insulating layer, forming a cap layer made of a metal film or an insulating film on the surface of the gate insulating layer after the ion implantation, and performing a heat treatment on the insulating layer with the cap layer formed on its surface to generate negative fixed charges in the insulating layer.
また本発明の別の薄膜トランジスタの製造方法は、正の固定電荷を有する固定電荷層と、酸化物半導体から成るチャネル層と、ゲート絶縁層と、ゲート電極層とが基板側から順に積層されたトップゲート型の薄膜トランジスタの製造方法であって、前記基板の表面に絶縁層を形成する工程と、前記絶縁層の表層部にイオン注入を行う工程と、イオン注入後の前記絶縁層の表面に、金属膜又は絶縁膜から成るキャップ層を形成する工程と、前記キャップ層が表面に形成された前記絶縁層に対して熱処理を行うことにより前記絶縁層中に正の固定電荷を発現させる工程とを含むことを特徴とする。 The present invention also provides a method for manufacturing a top-gate type thin-film transistor in which a fixed charge layer having a positive fixed charge, a channel layer made of an oxide semiconductor, a gate insulating layer, and a gate electrode layer are stacked in this order from the substrate side, and the method includes the steps of forming an insulating layer on the surface of the substrate, implanting ions into the surface portion of the insulating layer, forming a cap layer made of a metal film or an insulating film on the surface of the insulating layer after the ion implantation, and performing a heat treatment on the insulating layer with the cap layer formed on the surface thereof to generate a positive fixed charge in the insulating layer.
このような薄膜トランジスタの製造方法であれば、前記した固定電荷制御方法と同様の作用効果を奏することができ、固定電荷による電気的な特性制御が可能になり、高移動度で且つ正の閾値電圧での動作が容易な薄膜トランジスタを製造することができる。 This method of manufacturing a thin-film transistor can achieve the same effect as the fixed charge control method described above, making it possible to control electrical characteristics using fixed charges, and manufacturing thin-film transistors that have high mobility and can easily operate at a positive threshold voltage.
このように構成した本発明によれば、半導体デバイスに用いられる絶縁層内に、膜質の低下を抑えながら必要な固定電荷を効率よく生成することができる。 The present invention, configured in this way, can efficiently generate the necessary fixed charges within the insulating layer used in semiconductor devices while minimizing deterioration of the film quality.
以下に、本発明の固定電荷制御方法を利用して製造した薄膜トランジスタ１及びその製造方法の一実施形態について説明する。 Below, we will explain one embodiment of a thin-film transistor 1 manufactured using the fixed charge control method of the present invention and a method for manufacturing the same.
＜１．薄膜トランジスタ＞
本実施形態の薄膜トランジスタ１は所謂トップゲート型のＴＦＴであり、酸化物半導体をチャネルに用いたものである。具体的には図１に示すように、基板２と、チャネル層（活性層）３と、ゲート絶縁層（特許請求の範囲の絶縁層に相当）４と、ゲート電極層（特許請求の範囲のキャップ層に相当）５と、絶縁層６と、ソース電極７及びドレイン電極８とを有しており、基板２側からこの順に形成されている。以下、各部について詳述する。
1. Thin-film transistors
The thin film transistor 1 of this embodiment is a so-called top-gate type TFT, and uses an oxide semiconductor for the channel. Specifically, as shown in Fig. 1, the thin film transistor 1 includes a substrate 2, a channel layer (active layer) 3, a gate insulating layer (corresponding to an insulating layer in the claims) 4, a gate electrode layer (corresponding to a cap layer in the claims) 5, an insulating layer 6, a source electrode 7, and a drain electrode 8, which are formed in this order from the substrate 2 side. Each part will be described in detail below.
（１）基板
基板２は光を透過できるような任意の材料から構成されており、例えば、ポリエチレンテレフタレート（ＰＥＴ）、ポリエチレナフタレート（ＰＥＮ）、ポリエーテルサルフォン（ＰＥＳ）、アクリル、ポリイミド等のプラスチック（合成樹脂）やガラス等によって構成されてよい。
(1) Substrate The substrate 2 is made of any material that can transmit light, and may be made of, for example, plastics (synthetic resins) such as polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyethersulfone (PES), acrylic, polyimide, etc., glass, etc.
（２）チャネル層
チャネル層３は、ゲート電圧の印加により、ソース電極７とドレイン電極８間にチャネルを形成し、電流を通過させるものである。チャネル層３は、酸化物半導体からなり、例えばＩｎ、Ｇａ、Ｚｎ、Ｓｎ、Ａｌ、Ｔｉ等から選択される少なくとも１種の元素の酸化物を主成分として含んでいる。チャネル層３を構成する材料の具体例としては、例えば、Ｉｎ２Ｏ３を主構成要素とする酸化物材料、Ｉｎ－Ｇａ－Ｚｎ－Ｏ（ＩＧＺＯ）、Ｉｎ－Ａｌ－Ｍｇ－Ｏ、Ｉｎ－Ａｌ－Ｚｎ－Ｏ又はＩｎ－Ｈｆ－Ｚｎ－Ｏ等が挙げられる。このチャネル層３は例えば非晶質（アモルファス）の酸化物半導体膜により構成されている。本実施形態のチャネル層３は単層構造であるが、これに限らず、組成や結晶性が互いに異なる複数の層を重ねて構成した積層構造であってもよい。
(2) Channel Layer The channel layer 3 forms a channel between the source electrode 7 and the drain electrode 8 by application of a gate voltage, and allows current to pass through. The channel layer 3 is made of an oxide semiconductor, and contains, for example, an oxide of at least one element selected from In, Ga, Zn, Sn, Al, Ti, etc., as a main component. Specific examples of materials constituting the channel layer 3 include, for example, oxide materials containing In 2 O 3 as a main component, In-Ga-Zn-O (IGZO), In-Al-Mg-O, In-Al-Zn-O, or In-Hf-Zn-O. The channel layer 3 is, for example, composed of an amorphous oxide semiconductor film. The channel layer 3 in this embodiment has a single-layer structure, but is not limited thereto, and may have a layered structure composed of multiple layers having different compositions and crystallinity.
このチャネル層３は、基板２の表面の一部を覆うように形成されている。そして基板２の表面には、チャネル層３を両側から挟むとともに、チャネル層３に電気的に接続するようにして、ソース領域層Ｓとドレイン領域層Ｄとが形成されている。このソース領域層Ｓとドレイン領域層Ｄは、積層方向に沿って形成されたコンタクトホールＨを介して、ソース電極７とドレイン電極８にそれぞれ電気的に接続されている。なおコンタクトホールＨには、例えばモリブデン等の金属が充填されている。 The channel layer 3 is formed so as to cover a portion of the surface of the substrate 2. A source region layer S and a drain region layer D are formed on the surface of the substrate 2 so as to sandwich the channel layer 3 from both sides and to be electrically connected to the channel layer 3. The source region layer S and the drain region layer D are electrically connected to the source electrode 7 and the drain electrode 8, respectively, via contact holes H formed along the stacking direction. The contact holes H are filled with a metal such as molybdenum.
（３）ゲート絶縁層
ゲート絶縁層４は、チャネル層３、ソース領域層Ｓ及びドレイン領域層Ｄの表面を覆うように形成されている。このゲート絶縁層４は、高い絶縁性を有する酸化膜、窒化膜、酸窒化膜等の任意の絶縁材料から構成されている。ゲート絶縁層４は、例えば、ＳｉＯｘ、ＳｉＮｘ、ＳｉＯＮ、Ａｌ２Ｏ３、Ｙ２Ｏ３、Ｔａ２Ｏ５、Ｈｆ２等から選択される１つ以上の酸化物を含む絶縁膜であってよい。ゲート絶縁層４は、これらの導電性膜を単層構造又は２層以上の積層構造としたものであってよい。
(3) Gate Insulation Layer The gate insulation layer 4 is formed to cover the surfaces of the channel layer 3, the source region layer S, and the drain region layer D. The gate insulation layer 4 is made of any insulating material such as an oxide film, a nitride film, or an oxynitride film having high insulating properties. The gate insulation layer 4 may be an insulating film containing one or more oxides selected from, for example, SiOx , SiNx , SiON , Al2O3 , Y2O3 , Ta2O5 , Hf2 , etc. The gate insulation layer 4 may be a single-layer structure or a laminate structure of two or more layers of these conductive films.
（４）ゲート電極層
ゲート電極層５は、薄膜トランジスタ１に印加されるゲート電圧によってチャネル層３中のキャリア密度を制御するものである。ゲート電極層５は、ゲート絶縁層４の表面において、チャネル層３の真上に位置するように形成されている。より具体的にゲート電極層５は、層内方向（積層方向に直交する方向）に沿ったその両端面の位置が、チャネル層３の両端面の位置と揃うようにして形成されている。このゲート電極層５は、高い導電性を有する任意の金属材料から構成されており、例えばＳｉ、Ａｌ、Ｍｏ、Ｃｒ、Ｔａ、Ｔｉ、Ｐｔ、Ａｕ、Ａｇ等から選択される１種以上の金属から構成されてよく、Ａｌ合金、Ａｇ合金、Ｍｏ合金、Ｔｉ合金等の合金により構成されてよい。
(4) Gate electrode layer The gate electrode layer 5 controls the carrier density in the channel layer 3 by the gate voltage applied to the thin film transistor 1. The gate electrode layer 5 is formed on the surface of the gate insulating layer 4 so as to be located directly above the channel layer 3. More specifically, the gate electrode layer 5 is formed so that the positions of both end faces along the in-layer direction (direction perpendicular to the stacking direction) are aligned with the positions of both end faces of the channel layer 3. The gate electrode layer 5 is made of any metal material having high conductivity, and may be made of one or more metals selected from, for example, Si, Al, Mo, Cr, Ta, Ti, Pt, Au, Ag, etc., or may be made of an alloy such as an Al alloy, an Ag alloy, an Mo alloy, or a Ti alloy.
（５）絶縁層
絶縁層６は、ゲート電極層５と、ソース電極７及びドレイン電極８との間を絶縁するものであり、例えばフッ素を含有するシリコン酸化膜などにより構成される。絶縁層６は、ゲート電極層５の全面（上面及び側面）と、ゲート絶縁層４の表面を覆うように形成されている。
(5) Insulating Layer The insulating layer 6 provides insulation between the gate electrode layer 5 and the source electrode 7 and drain electrode 8, and is made of, for example, a silicon oxide film containing fluorine. The insulating layer 6 is formed so as to cover the entire surface (upper surface and side surface) of the gate electrode layer 5 and the surface of the gate insulating layer 4.
（６）ソース電極、ドレイン電極
ソース電極７及びドレイン電極８は、チャネル層３の表面を部分的に覆うように、互いに離間して形成されている。ソース電極７及びドレイン電極８は、ゲート電極層５と同様に、電極として機能するように高い導電性を有する材料から構成されている。ソース電極７及びドレイン電極８は、単一の材料からなる単層構造でよく、互いに異なる材料からなる複数の層を重ねた積層構造であってもよい。ソース電極７及びドレイン電極８は、絶縁層６及びゲート絶縁層４を積層方向に沿って貫通するコンタクトホールＨを介して、ソース領域層Ｓ及びドレイン領域層Ｄにそれぞれ電気的に接続されている。
(6) Source Electrode, Drain Electrode The source electrode 7 and the drain electrode 8 are formed to be spaced apart from each other so as to partially cover the surface of the channel layer 3. The source electrode 7 and the drain electrode 8 are made of a material having high conductivity so as to function as an electrode, similar to the gate electrode layer 5. The source electrode 7 and the drain electrode 8 may have a single-layer structure made of a single material, or may have a laminated structure in which a plurality of layers made of different materials are laminated. The source electrode 7 and the drain electrode 8 are electrically connected to the source region layer S and the drain region layer D, respectively, via contact holes H penetrating the insulating layer 6 and the gate insulating layer 4 along the lamination direction.
（７）ゲート絶縁層内の固定電荷
そして本実施形態の薄膜トランジスタ１では、ゲート絶縁層４内におけるゲート電極層５との界面近傍に、イオン注入を行うことにより形成された（発現された）負の固定電荷が存在している。
(7) Fixed Charge in Gate Insulation Layer In the thin film transistor 1 of the present embodiment, negative fixed charges are present in the gate insulation layer 4 near the interface with the gate electrode layer 5 by ion implantation.
本実施形態の薄膜トランジスタ１では、ゲート絶縁層４の厚みｄｉと、注入イオン（例えば、Ｏ、Ｎ、Ｃ等の原子イオン、Ｏ２、Ｎ２、Ｃ２等の分子イオン、Ａｒ等の希ガスイオン）の平均飛程Ｒｐと、その標準偏差ΔＲｐとの関係を調整することで、注入イオンの多くを、ゲート絶縁層４内における表層部に留まるようにしている。具体的に本実施形態の薄膜トランジスタ１では、イオン注入によるイオンの平均飛程Ｒｐとその標準偏差ΔＲｐの和が、ゲート絶縁層４の厚みｄｉの半分より小さくしており、より具体的には、ゲート絶縁層４の厚みｄｉの１／３よりも小さくしている。なお、イオンの平均飛程Ｒｐとは、イオン注入されたイオンの膜中における深さ方向（積層方向）の分布の最大値の深さ位置であり、またこの場合の標準偏差ΔＲｐは、同分布の奥側（層内方向側）への拡がりを示す指標である。 In the thin film transistor 1 of this embodiment, the relationship between the thickness d i of the gate insulating layer 4, the average range R p of the implanted ions (e.g., atomic ions such as O, N, C, molecular ions such as O 2 , N 2 , C 2 , and rare gas ions such as Ar) and its standard deviation ΔR p is adjusted so that most of the implanted ions remain in the surface layer of the gate insulating layer 4. Specifically, in the thin film transistor 1 of this embodiment, the sum of the average range R p of the ions by ion implantation and its standard deviation ΔR p is smaller than half the thickness di of the gate insulating layer 4, and more specifically, is smaller than ⅓ of the thickness di of the gate insulating layer 4. The average range R p of the ions is the depth position of the maximum value of the distribution of the implanted ions in the depth direction (stacking direction) in the film, and the standard deviation ΔR p in this case is an index indicating the spread of the distribution toward the back side (intralayer direction).
そして本実施形態の薄膜トランジスタ１では、イオン注入による注入イオンと欠陥は、ゲート絶縁層４とゲート電極層５の界面近傍において、ゲート絶縁層４側にのみ形成されており、ゲート電極層５側には形成されていない。 In the thin-film transistor 1 of this embodiment, the implanted ions and defects due to ion implantation are formed only on the gate insulating layer 4 side near the interface between the gate insulating layer 4 and the gate electrode layer 5, and are not formed on the gate electrode layer 5 side.
また元素の分布の観点から言うと、本実施形態の薄膜トランジスタ１では、ゲート絶縁層４におけるゲート電極層５との界面近傍にイオン注入により添加された元素が分布しており、ごく微量の拡散はあるものの、ゲート電極層５内にはイオン注入により添加された元素がほとんど分布していない。 In terms of element distribution, in the thin-film transistor 1 of this embodiment, the elements added by ion implantation are distributed in the gate insulating layer 4 near the interface with the gate electrode layer 5, and although there is a very small amount of diffusion, the elements added by ion implantation are hardly distributed in the gate electrode layer 5.
＜２．薄膜トランジスタの製造方法＞
次に、上述した構造の薄膜トランジスタ１の製造方法を、図３を参照して説明する。本実施形態の薄膜トランジスタ１の製造方法は、チャネル層形成工程と、ゲート絶縁層形成工程と、ゲート電極形成工程と、ソース領域／ドレイン領域形成工程と、絶縁層形成工程と、ソース電極／ドレイン電極形成工程とを含んでいる。以下、各工程について説明する。
2. Manufacturing method of thin film transistor
Next, a method for manufacturing the thin film transistor 1 having the above-mentioned structure will be described with reference to Fig. 3. The method for manufacturing the thin film transistor 1 of this embodiment includes a channel layer forming step, a gate insulating layer forming step, a gate electrode forming step, a source region/drain region forming step, an insulating layer forming step, and a source electrode/drain electrode forming step. Each step will be described below.
（１）チャネル層形成工程
まず、基板２上にチャネル層３を形成する。このチャネル層３は、既知の方法により形成してよい。例えばプラズマを用いて、ＩｎＧａＺｎＯ等の導電性酸化物焼結体をターゲットとしてスパッタリングすることにより、基板２の全面を覆うようにチャネル層３を形成してよい。なおこれに限らず、他の方法により、酸化物半導体からなるチャネル層３を形成してもよい。
(1) Channel Layer Formation Step First, the channel layer 3 is formed on the substrate 2. The channel layer 3 may be formed by a known method. For example, the channel layer 3 may be formed so as to cover the entire surface of the substrate 2 by sputtering a conductive oxide sintered body such as InGaZnO as a target using plasma. However, the method is not limited to this, and the channel layer 3 made of an oxide semiconductor may be formed by another method.
（２）ゲート絶縁層形成工程
次に、酸化膜、窒化膜、酸窒化膜等の任意の絶縁材料から構成されるゲート絶縁層４をチャネル層３上に形成する。ここでは、例えばプラズマＣＶＤ法等の既知の方法により、チャネル層３の全面を覆うようにゲート絶縁層４を形成する。
(2) Gate Insulating Layer Forming Step Next, the gate insulating layer 4 made of any insulating material such as an oxide film, a nitride film, or an oxynitride film is formed on the channel layer 3. Here, the gate insulating layer 4 is formed so as to cover the entire surface of the channel layer 3 by a known method such as a plasma CVD method.
（３）第１イオン注入工程
次に、図３の（ａ）に示すように、形成したゲート絶縁層４の表層部にイオン注入を行う。イオン注入は既知のイオン注入法により行ってよい。このイオン注入工程は、積層方向から視てゲート絶縁層４の全面に対してイオンを注入するように行われる。注入するイオン種は、例えばＯ、Ｎ、Ｃ等の原子イオン、Ｏ２、Ｎ２、Ｃ２等の分子イオン、Ａｒ等の希ガスイオンであるが、これに限らない。イオンエネルギーは、例えば５ｋｅＶ～３０ｋｅＶであるがこれに限らない。またイオン注入量（ドーズ量）は、例えば１×１０１３ｉоｎｓ／ｃｍ２～１×１０１５ｉоｎｓ／ｃｍ２であるが、これに限らない。イオンエネルギー及びイオン注入量は、イオン注入によるイオンの平均飛程Ｒｐとその標準偏差ΔＲｐの和が、ゲート絶縁層４の厚みｄｉの半分より小さくなるように、好ましくはゲート絶縁層４の厚みｄｉの１／３よりも小さくなるように設定される。これにより、ゲート絶縁層４における表層部に注入イオンの多くが分布する。
(3) First Ion Implantation Step Next, as shown in FIG. 3A, ions are implanted into the surface layer of the gate insulating layer 4. The ion implantation may be performed by a known ion implantation method. This ion implantation step is performed so as to implant ions into the entire surface of the gate insulating layer 4 as viewed from the stacking direction. The ion species to be implanted include, but are not limited to, atomic ions such as O, N, and C, molecular ions such as O 2 , N 2 , and C 2 , and rare gas ions such as Ar. The ion energy is, but is not limited to, for example, 5 keV to 30 keV. The ion implantation amount (dose amount) is, but is not limited to, for example, 1×10 13 ions/cm 2 to 1×10 15 ions/cm 2 . The ion energy and the amount of ion implantation are set so that the sum of the average range Rp of the ions by ion implantation and its standard deviation ΔRp is smaller than half the thickness di of the gate insulating layer 4, and preferably smaller than ⅓ of the thickness di of the gate insulating layer 4. This distributes most of the implanted ions in the surface layer portion of the gate insulating layer 4.
（４）ゲート電極形成工程
次に図３（ｂ）に示すように、イオン注入が行われたゲート絶縁層４の表面（イオン注入面）に、キャップ層として機能するゲート電極層５を形成する。ゲート電極層５は、ゲート絶縁層４のイオン注入面の全面を覆うように形成される。このゲート電極層５の形成は、真空蒸着法、スパッタリング法等の既知の方法により行ってよい。
3B, a gate electrode layer 5 functioning as a cap layer is formed on the surface (ion-implanted surface) of the gate insulating layer 4 into which ions have been implanted. The gate electrode layer 5 is formed so as to cover the entire ion-implanted surface of the gate insulating layer 4. The gate electrode layer 5 may be formed by a known method such as a vacuum deposition method or a sputtering method.
（５）ソース領域／ドレイン領域形成工程
次に、図３の（ｃ）に示すように、チャネル層３を挟むようにソース領域層Ｓ及びドレイン領域層Ｄを形成する。この工程は、レジストパターニング工程と、エッチング工程と、第２イオン注入工程とを含む。
3C, a source region layer S and a drain region layer D are formed to sandwich the channel layer 3. This step includes a resist patterning step, an etching step, and a second ion implantation step.
（５－１）レジストパターニング工程
まず、ゲート電極層５上にフォトレジストＲを塗布し、露光及び現像を行う。このフォトレジストＲは、ゲート電極層５上において、最終的にチャネル層３となる部位の直上にのみ選択的に塗布する。
(5-1) Resist Patterning Step First, photoresist R is applied onto the gate electrode layer 5, and exposed and developed. This photoresist R is selectively applied only directly above the portion of the gate electrode layer 5 that will eventually become the channel layer 3.
（５－２）エッチング工程
次に、ゲート電極層５におけるフォトレジストＲが塗布されていない部分をエッチングにより除去し、ゲート電極層５のパターニングを行う。このエッチング工程において、ゲート絶縁層４におけるゲート電極層５との界面近傍の領域（すなわち、第１イオン注入工程でイオンが注入された表層部領域）を除去する。
(5-2) Etching Step Next, the portion of the gate electrode layer 5 on which the photoresist R is not applied is removed by etching, thereby patterning the gate electrode layer 5. In this etching step, the region of the gate insulating layer 4 near the interface with the gate electrode layer 5 (i.e., the surface layer region into which ions are implanted in the first ion implantation step) is removed.
（５－３）第２イオン注入工程
次に、エッチング後のゲート絶縁層４を介して、チャネル層３におけるゲート電極層５の外側の領域にイオン注入を行い、チャネル層３の両外側にソース領域層Ｓとドレイン領域層Ｄとを形成する。このイオン注入工程では、積層したフォトレジストＲ及びゲート電極層５をマスクとして行われる。なお、当該工程のイオン注入は既知の任意の方法により行われてよい。
(5-3) Second Ion Implantation Step Next, ions are implanted into the region of the channel layer 3 outside the gate electrode layer 5 through the etched gate insulating layer 4, to form a source region layer S and a drain region layer D on both sides of the channel layer 3. This ion implantation step is performed using the laminated photoresist R and the gate electrode layer 5 as a mask. The ion implantation in this step may be performed by any known method.
（６）絶縁層形成工程
第２イオン注入工程の後、図３の（ｄ）に示すように、フォトレジストＲを除去してから絶縁層６を形成する。絶縁層６は、ゲート絶縁層４及びゲート電極層５の表面の全面を覆うようにして形成される。絶縁層６は、例えばプラズマＣＶＤ法等の任意の方法により形成されてよい。
(6) Insulating Layer Forming Step After the second ion implantation step, the photoresist R is removed and then the insulating layer 6 is formed as shown in Fig. 3(d). The insulating layer 6 is formed so as to cover the entire surfaces of the gate insulating layer 4 and the gate electrode layer 5. The insulating layer 6 may be formed by any method such as a plasma CVD method.
（７）ソース電極／ドレイン電極形成工程
その後、図３の（ｅ）に示すように、ゲート絶縁層４上にソース電極７及びドレイン電極８を形成する。ソース電極７およびドレイン電極８の形成は、例えば、ＲＦマグネトロンスパッタリング等を用いた既知の方法により形成することができる。このソース電極７及びドレイン電極８は、エッチング等により積層方向に形成したコンタクトホールＨを介して、ソース領域層Ｓ及びドレイン領域層Ｄにそれぞれ接続させる。
3(e), a source electrode 7 and a drain electrode 8 are formed on the gate insulating layer 4. The source electrode 7 and the drain electrode 8 can be formed by a known method using, for example, RF magnetron sputtering. The source electrode 7 and the drain electrode 8 are connected to the source region layer S and the drain region layer D, respectively, via contact holes H formed in the stacking direction by etching or the like.
（８）熱処理工程
そして熱処理を行う。この熱処理を行うことで、ゲート絶縁層４の表層部に形成されているイオン注入による欠陥を低減するとともに、ゲート絶縁層４内に負の固定電荷を発現する。この熱処理は、少なくともゲート絶縁層４のイオン注入面がキャップ層（本実施形態ではゲート電極層５）により被覆された後であれば、どの段階で行ってもよい。この熱処理は、酸素を含む大気圧下の雰囲気中で行ってもよく、窒素雰囲中で行ってもよい。また熱処理温度は特に限定されず例えば１５０℃以上３００℃以下で行ってよい。熱処理時間も特に限定されず例えば１ｈ以上３ｈ以下でよい。またこの熱処理工程は、加熱炉等を用いることなく、例えばスパッタリング等により、ゲート電極層５を成膜している最中に、例えばスパッタリング等により生じる熱エネルギーを利用して行ってもよい。
(8) Heat Treatment Step Then, heat treatment is performed. By performing this heat treatment, defects due to ion implantation formed in the surface layer of the gate insulating layer 4 are reduced, and negative fixed charges are generated in the gate insulating layer 4. This heat treatment may be performed at any stage after at least the ion-implanted surface of the gate insulating layer 4 is covered with a cap layer (the gate electrode layer 5 in this embodiment). This heat treatment may be performed in an atmosphere under atmospheric pressure containing oxygen, or in a nitrogen atmosphere. The heat treatment temperature is not particularly limited, and may be, for example, 150°C to 300°C. The heat treatment time is also not particularly limited, and may be, for example, 1 hour to 3 hours. This heat treatment step may be performed without using a heating furnace, for example, by utilizing thermal energy generated by sputtering, etc., during the formation of the gate electrode layer 5 by sputtering, etc.
以上により、本実施形態の薄膜トランジスタ１を得ることができる。 By the above steps, the thin film transistor 1 of this embodiment can be obtained.
＜３．本実施形態の効果＞
このようにした本実施形態の薄膜トランジスタ１の製造方法によれば、ゲート絶縁層４の全体の膜質を変化させるのではなく、イオン注入によりゲート絶縁層４の表層部だけの膜質を変化させて負の固定電荷を発現させるようにしているので、ゲート絶縁層４の本来の絶縁特性をほぼ維持した状態で部分的な機能の付加を行うことができる。またイオン注入を行うことによりゲート絶縁層４内には、注入イオンと、原子衝突により生成される欠陥とが分布するようになるが、本実施形態の製造方法であればイオン注入を行ったゲート絶縁層４の表面にキャップ層であるゲート絶縁層５が形成された状態で熱処理を行うようにしているので、ゲート絶縁層４内の欠陥を修復するとともに、熱処理中におけるゲート絶縁層４内での遊離元素の結合を促進でき、効率よく必要な負の固定電荷を生成できる。そしてイオン注入を行う際のイオンの飛程やイオン種、又は熱処理の温度や時間等を調整することで、ゲート絶縁層４内における固定電荷密度を容易に調整することができ、高移動度で且つ正の閾値電圧での動作が容易な薄膜トランジスタ１を製造することができる。
3. Effects of this embodiment
According to the manufacturing method of the thin film transistor 1 of the present embodiment, the film quality of the entire gate insulating layer 4 is not changed, but only the film quality of the surface layer of the gate insulating layer 4 is changed by ion implantation to generate negative fixed charges, so that partial functions can be added while the original insulating properties of the gate insulating layer 4 are almost maintained. In addition, by performing ion implantation, the gate insulating layer 4 is distributed with implanted ions and defects generated by atomic collisions. However, in the manufacturing method of the present embodiment, the heat treatment is performed in a state where the gate insulating layer 5, which is a cap layer, is formed on the surface of the gate insulating layer 4 after ion implantation. This makes it possible to repair defects in the gate insulating layer 4 and promote the bonding of free elements in the gate insulating layer 4 during the heat treatment, so that the required negative fixed charges can be efficiently generated. By adjusting the range and species of ions during ion implantation, or the temperature and time of the heat treatment, the fixed charge density in the gate insulating layer 4 can be easily adjusted, and a thin film transistor 1 with high mobility and easy operation at a positive threshold voltage can be manufactured.
なお、本発明の固定電荷制御方法は前記実施形態に限られるものではない。
例えば前記実施形態では固定電荷制御方法の一例として薄膜トランジスタ１の製造方法を例示したがこれに限らない。他の実施形態では、薄膜トランジスタ以外の他の半導体デバイスの製造方法において本発明の固定電荷制御方法が用いられてもよい。
The fixed charge control method of the present invention is not limited to the above embodiment.
For example, in the above embodiment, the manufacturing method of the thin film transistor 1 is exemplified as an example of the fixed charge control method, but the present invention is not limited to this. In other embodiments, the fixed charge control method of the present invention may be used in manufacturing other semiconductor devices other than thin film transistors.
また前記実施形態では、ゲート絶縁層４にイオン注入を行った後、このイオン注入面上にゲート電極層５を直接形成してキャップ層としていたがこれに限らない。他の実施形態では、ゲート絶縁層４にイオン注入を行った後、ゲート電極層５を形成する前に、例えば窒化膜や酸窒化膜等の絶縁膜をキャップ層としてゲート絶縁層４のイオン注入面上に形成してもよい。 In the above embodiment, after ions are implanted into the gate insulating layer 4, the gate electrode layer 5 is formed directly on the ion-implanted surface to serve as a cap layer, but this is not limited to the above. In other embodiments, after ions are implanted into the gate insulating layer 4, an insulating film such as a nitride film or an oxynitride film may be formed as a cap layer on the ion-implanted surface of the gate insulating layer 4 before the gate electrode layer 5 is formed.
また前記実施形態の製造方法は、薄膜トランジスタ１のフロントチャネル側の絶縁層（ゲート絶縁層４）に負の固定電荷を発現させるものであったが、これに限らない。他の実施形態では、薄膜トランジスタ１のバックチャネル側に絶縁層を形成し、この絶縁層に正の固定電荷を発現させるようにしてもよい。 In addition, the manufacturing method of the above embodiment is to generate a negative fixed charge in the insulating layer (gate insulating layer 4) on the front channel side of the thin film transistor 1, but is not limited to this. In other embodiments, an insulating layer may be formed on the back channel side of the thin film transistor 1, and a positive fixed charge may be generated in this insulating layer.
例えば他の実施形態の薄膜トランジスタ１は、図４に示すように、基板２とチャネル層３との間に、正の固定電荷を有する固定電荷層９を有していている。この固定電荷層９は、基板２側から順に積層された第１絶縁層（特許請求の範囲の絶縁層に相当）９１と第２絶縁層（特許請求の範囲のキャップ層に相当）９２とを備えている。この第１絶縁層９１と第２絶縁層９２は、上記したゲート絶縁層４と同様の材料により構成されている。なお。第１絶縁層９１と第２絶縁層９２との間に金属層が設けられ、当該金属層がキャップ層として機能するようにしてもよい。 For example, as shown in FIG. 4, a thin-film transistor 1 according to another embodiment has a fixed charge layer 9 having a positive fixed charge between the substrate 2 and the channel layer 3. This fixed charge layer 9 includes a first insulating layer (corresponding to the insulating layer in the claims) 91 and a second insulating layer (corresponding to the cap layer in the claims) 92, which are stacked in this order from the substrate 2 side. The first insulating layer 91 and the second insulating layer 92 are made of the same material as the gate insulating layer 4 described above. Note that a metal layer may be provided between the first insulating layer 91 and the second insulating layer 92, and the metal layer may function as the cap layer.
そしてこの実施形態では、第１絶縁層９１内における第２絶縁層９２との界面近傍に、イオン注入を行うことにより形成された（発現された）正の固定電荷が存在するようにしている。そしてこの実施形態の薄膜トランジスタ１では、第１絶縁層９１の厚みｄｉと、注入イオンの平均飛程Ｒｐと、その標準偏差ΔＲｐとの関係を調整することで、注入イオンの多くを、ゲート絶縁層４内における表層部に留まるようにしている。具体的にこの実施形態の薄膜トランジスタ１では、イオン注入によるイオンの平均飛程Ｒｐとその標準偏差ΔＲｐの和が、第１絶縁層９１の厚みｄｉの半分より小さくしており、より具体的には、第１絶縁層９１の厚みｄｉの１／３よりも小さくしている。なお、イオンの平均飛程Ｒｐとは、イオン注入されたイオンの膜中における深さ方向（積層方向）の分布の最大値の深さ位置であり、またこの場合の標準偏差ΔＲｐは、同分布の奥側（層内方向側）への拡がりを示す指標である。 In this embodiment, a positive fixed charge formed (expressed) by ion implantation is present in the first insulating layer 91 near the interface with the second insulating layer 92. In the thin film transistor 1 of this embodiment, the relationship between the thickness d i of the first insulating layer 91, the average range R p of the implanted ions, and its standard deviation ΔR p is adjusted to make most of the implanted ions remain in the surface layer of the gate insulating layer 4. Specifically, in the thin film transistor 1 of this embodiment, the sum of the average range R p of the ions by ion implantation and its standard deviation ΔR p is smaller than half the thickness di of the first insulating layer 91, and more specifically, is smaller than ⅓ of the thickness di of the first insulating layer 91. The average range R p of the ions is the depth position of the maximum value of the distribution of the implanted ions in the depth direction (stacking direction) in the film, and the standard deviation ΔR p in this case is an index indicating the spread of the distribution toward the back side (intralayer direction).
そしてこの実施形態の薄膜トランジスタ１では、イオン注入による注入イオンと欠陥は、第１絶縁層９１と第１絶縁層９２の界面近傍において、第１絶縁層９１側にのみ形成されており、第２絶縁層９２側には形成されていない。また元素の分布の観点から言うと、第１絶縁層９１における第２絶縁層９２との界面近傍にイオン注入により添加された元素が分布しており、第２絶縁層９２内にはイオン注入により添加された元素が分布していない。 In the thin film transistor 1 of this embodiment, the implanted ions and defects are formed only on the first insulating layer 91 side near the interface between the first insulating layer 91 and the first insulating layer 92, and are not formed on the second insulating layer 92 side. In terms of element distribution, the elements added by ion implantation are distributed in the first insulating layer 91 near the interface with the second insulating layer 92, but are not distributed in the second insulating layer 92.
次にこの実施形態の薄膜トランジスタ１の製造方法について図５を用いて説明する。 Next, the manufacturing method of the thin-film transistor 1 of this embodiment will be described with reference to FIG.
この実施形態では、図５（ａ）に示すように、まず基板２上に、酸化膜、窒化膜、酸窒化膜等の任意の絶縁材料から構成される第１絶縁層９１を積層する。ここでは、例えばプラズマＣＶＤ法等の既知の方法により、基板２の全面を覆うように第１絶縁層９１を形成する。 In this embodiment, as shown in FIG. 5(a), a first insulating layer 91 made of any insulating material such as an oxide film, a nitride film, or an oxynitride film is first laminated on the substrate 2. Here, the first insulating layer 91 is formed so as to cover the entire surface of the substrate 2 by a known method such as a plasma CVD method.
次に、形成した第１絶縁層９１の表層部にイオン注入を行う。イオン注入の条件は、上記した（３）第１イオン注入工程と同じである。 Next, ions are implanted into the surface layer of the first insulating layer 91. The conditions for the ion implantation are the same as those for the first ion implantation process (3) described above.
次に図５（ｂ）に示すように、イオン注入が行われた第１絶縁層９１の表面（イオン注入面）に、キャップ層として機能する第２絶縁層９２を形成する。第２絶縁層９２は、第１絶縁層９１のイオン注入面の全面を覆うように形成される。この第２絶縁層９２の形成は、プラズマＣＶＤ法等の既知の方法により行われてよい。 Next, as shown in FIG. 5(b), a second insulating layer 92 that functions as a cap layer is formed on the surface (ion-implanted surface) of the first insulating layer 91 where ions have been implanted. The second insulating layer 92 is formed so as to cover the entire ion-implanted surface of the first insulating layer 91. The formation of this second insulating layer 92 may be performed by a known method such as plasma CVD.
その後、第２絶縁層９２の上にチャネル層３を形成した後、上記した図３に記載の工程と同様の処理を行い、薄膜トランジスタ１を得ることができる。 Then, a channel layer 3 is formed on the second insulating layer 92, and the same process as that described in FIG. 3 above is performed to obtain a thin-film transistor 1.
その他、本発明は前記実施形態に限られず、その趣旨を逸脱しない範囲で種々の変形が可能であるのは言うまでもない。例えば、上述した複数の例示的な実施形態は、以下の態様の具体例であることが当業者により理解される。 Needless to say, the present invention is not limited to the above-described embodiments, and various modifications are possible without departing from the spirit of the present invention. For example, it will be understood by those skilled in the art that the above-described exemplary embodiments are specific examples of the following aspects:
（態様１）半導体デバイスに用いられる絶縁層内の固定電荷を制御する方法であって、前記絶縁層を形成した後、当該絶縁層の表層部にイオン注入を行い、当該イオン注入後の前記絶縁層の表面に金属膜又は絶縁膜からなるキャップ層を形成し、前記キャップ層が表面に形成された前記絶縁層に対して熱処理を行うことにより前記絶縁層中に固定電荷を発現させる固定電荷制御方法。 (Aspect 1) A method for controlling fixed charges in an insulating layer used in a semiconductor device, comprising the steps of: forming the insulating layer, implanting ions into a surface portion of the insulating layer; forming a cap layer made of a metal film or an insulating film on the surface of the insulating layer after the ion implantation; and subjecting the insulating layer with the cap layer formed on its surface to a heat treatment, thereby generating fixed charges in the insulating layer.
（態様２）前記イオン注入によるイオンの平均飛程とその標準偏差の和が、前記絶縁層の厚みの半分より小さい態様１に記載の固定電荷制御方法。 (Aspect 2) A fixed charge control method according to aspect 1, in which the sum of the average range of ions by the ion implantation and its standard deviation is less than half the thickness of the insulating layer.
（態様３）前記絶縁層が、酸化膜、窒化膜又は酸窒化膜からなるものである態様１又は２に記載の固定電荷制御方法。 (Aspect 3) The fixed charge control method according to aspect 1 or 2, in which the insulating layer is made of an oxide film, a nitride film, or an oxynitride film.
（態様４）前記キャップ層が、窒化膜又は酸窒化膜からなるものである態様１～３のいずれかに記載の固定電荷制御方法。 (Aspect 4) A fixed charge control method according to any one of aspects 1 to 3, in which the cap layer is made of a nitride film or an oxynitride film.
（態様５）前記キャップ層が、アルミニウム、アルミニウム合金、モリブデン、モリブデン合金、チタン又はチタン合金からなるものである態様１～４のいずれかに記載の固定電荷制御方法。 (Aspect 5) A fixed charge control method according to any one of aspects 1 to 4, in which the cap layer is made of aluminum, an aluminum alloy, molybdenum, a molybdenum alloy, titanium, or a titanium alloy.
（態様６）前記絶縁層の表面に前記キャップ層を形成する際に生じる熱を利用して前記絶縁層の熱処理を行う態様１～５のいずれかに記載の固定電荷制御方法。 (Aspect 6) A fixed charge control method according to any one of aspects 1 to 5, in which the insulating layer is heat-treated using heat generated when the cap layer is formed on the surface of the insulating layer.
（態様７）前記イオン注入で注入するイオン種は、Ｏ、Ｎ、Ｃ等の原子イオン、Ｏ２、Ｎ２、Ｃ２等の分子イオン、又はＡｒ等の希ガスイオンから選択される１種以上である態様１～６のいずれかに記載の固定電荷制御方法。 (Aspect 7) The fixed charge control method according to any one of aspects 1 to 6, wherein the ion species implanted in the ion implantation is one or more selected from atomic ions such as O , N, and C, molecular ions such as O2, N2 , and C2 , and rare gas ions such as Ar.
（態様８）酸化物半導体から成るチャネル層と、ゲート絶縁層と、ゲート電極層とが基板側から順に積層されたトップゲート型の薄膜トランジスタの製造方法であって、前記チャネル層を形成する工程と、前記チャネル層の表面に前記ゲート絶縁層を形成する工程と、前記ゲート絶縁層の表層部にイオン注入を行う工程と、イオン注入後の前記ゲート絶縁層の表面に、金属膜又は絶縁膜から成るキャップ層を形成する工程と、前記キャップ層が表面に形成された前記絶縁層に対して熱処理を行うことにより前記絶縁層中に負の固定電荷を発現させる工程とを含む薄膜トランジスタの製造方法。 (Aspect 8) A method for manufacturing a top-gate type thin film transistor in which a channel layer made of an oxide semiconductor, a gate insulating layer, and a gate electrode layer are stacked in this order from the substrate side, the method comprising the steps of forming the channel layer, forming the gate insulating layer on the surface of the channel layer, implanting ions into a surface portion of the gate insulating layer, forming a cap layer made of a metal film or an insulating film on the surface of the gate insulating layer after the ion implantation, and performing a heat treatment on the insulating layer with the cap layer formed on its surface to generate a negative fixed charge in the insulating layer.
（態様９）正の固定電荷を有する固定電荷層と、酸化物半導体から成るチャネル層と、ゲート絶縁層と、ゲート電極層とが基板側から順に積層されたトップゲート型の薄膜トランジスタの製造方法であって、前記基板の表面に絶縁層を形成する工程と、前記絶縁層の表層部にイオン注入を行う工程と、イオン注入後の前記絶縁層の表面に、金属膜又は絶縁膜から成るキャップ層を形成する工程と、前記キャップ層が表面に形成された前記絶縁層に対して熱処理を行うことにより前記絶縁層中に正の固定電荷を発現させる工程とを含む薄膜トランジスタの製造方法。 (Aspect 9) A method for manufacturing a top-gate type thin film transistor in which a fixed charge layer having a positive fixed charge, a channel layer made of an oxide semiconductor, a gate insulating layer, and a gate electrode layer are stacked in this order from the substrate side, the method including the steps of forming an insulating layer on the surface of the substrate, implanting ions into a surface portion of the insulating layer, forming a cap layer made of a metal film or an insulating film on the surface of the insulating layer after the ion implantation, and performing a heat treatment on the insulating layer with the cap layer formed on its surface to generate a positive fixed charge in the insulating layer.
以下、実施例を挙げて本発明をより具体的に説明する。本発明は以下の実施例によって制限を受けるものではなく、前記、後記の趣旨に適合し得る範囲で適当に変更を加えて実施することが勿論可能であり、それらはいずれも本発明の技術的範囲に包含される。 The present invention will be described in more detail below with reference to examples. The present invention is not limited to the following examples, and can of course be modified as appropriate within the scope of the above and below-described aims, and all such modifications are within the technical scope of the present invention.
＜実施例：イオン注入後の熱処理と固定電荷密度との関係性＞
イオン注入後の熱処理と固定電荷密度との関係性を評価した。
Example: Relationship between heat treatment after ion implantation and fixed charge density
The relationship between the heat treatment after ion implantation and the fixed charge density was evaluated.
（１）評価サンプル
この実施例では、シリコン基板上に絶縁層と金属層を積層したサンプルを複数準備した。各評価サンプルにおいて、シリコン基板は、ｎ型であり、比抵抗１～１０Ωｃｍのものを用い、絶縁層として膜厚約１００ｎｍの熱酸化シリコン膜を形成し、金属層として膜厚約１０ｎｍのＡｌ－Ｓｉ合金膜を形成した。
(1) Evaluation Samples In this example, a number of samples were prepared in which an insulating layer and a metal layer were laminated on a silicon substrate. In each evaluation sample, the silicon substrate was of n-type and had a resistivity of 1 to 10 Ωcm. A thermally oxidized silicon film with a thickness of about 100 nm was formed as the insulating layer, and an Al-Si alloy film with a thickness of about 10 nm was formed as the metal layer.
また各評価サンプルは、熱酸化シリコン膜を形成した後金属層を形成する前に、熱酸化シリコン膜の表面にイオン注入を行った。イオン注入は、サンプル毎にイオン注入量とイオン種を変えて行った。イオン注入量（ドーズ量）は１×１０１３ｉоｎｓ／ｃｍ２～１×１０１５ｉоｎｓ／ｃｍ２とした。また注入イオン種は、Ｎ＋、Ｏ＋、Ａｒ＋とした。またいずれの評価サンプルも、注入するイオンエネルギーを１０ｋｅＶとした。なお、注入イオン（Ｎ＋，Ｏ＋、Ａｒ＋）のイオンエネルギーと注入深さとの関係との関係をシミュレーションソフト（ＳＲＩＭ２０１３）を用いて計算した結果を図７に示す。このシミュレーションでは、イオン注入の対象を、Ｓｉ基板上に酸化シリコン膜（膜厚１００ｎｍ）とし、注入イオンのエネルギーを５～３０ｋｅＶとしている。 In addition, for each evaluation sample, ion implantation was performed on the surface of the thermally oxidized silicon film after the formation of the thermally oxidized silicon film and before the formation of the metal layer. The ion implantation was performed by changing the amount of ion implantation and the ion species for each sample. The amount of ion implantation (dose) was set to 1×10 13 ions/cm 2 to 1×10 15 ions/cm 2. The implanted ion species were set to N + , O + , and Ar + . The ion energy for implantation was set to 10 keV for each evaluation sample. The results of calculations using simulation software (SRIM2013) for the relationship between the ion energy of the implanted ions (N + , O + , and Ar + ) and the implantation depth are shown in FIG. 7 . In this simulation, the target of ion implantation was a silicon oxide film (film thickness 100 nm) on a Si substrate, and the energy of the implanted ions was set to 5 to 30 keV.
（２）熱処理
そして評価サンプルに対して熱処理を行った。熱処理は、大気圧下の窒素雰囲気中で、２００℃で２時間行った。
(2) Heat Treatment The evaluation sample was then subjected to a heat treatment at 200° C. for 2 hours in a nitrogen atmosphere under atmospheric pressure.
（３）固定電荷密度の評価
そして熱処理後の各評価サンプルにおける熱酸化シリコン膜の固定電荷密度をＣ－Ｖ法により測定した。なおこの実施例では、各評価サンプルの熱処理前の固定電荷密度も、Ｃ－Ｖ法により予め測定している。その結果を図８に示す。
(3) Evaluation of fixed charge density The fixed charge density of the thermally oxidized silicon film of each evaluation sample after the heat treatment was measured by the CV method. In this example, the fixed charge density of each evaluation sample before the heat treatment was also measured in advance by the CV method. The results are shown in FIG.
図８に示すように、イオン注入を行うことで正の固定電荷の増加が見られたが、イオン注入後に熱処理を行うことで、一様に正の固定電荷を減少できることを確認できた。酸化シリコン中の欠陥は正の固定電荷を発現することが知られていることから、イオン注入時に生成される欠陥により正の電荷が増加したものと考えられる。イオン注入後に熱処理を行うことで、欠陥が修復されて正の固定電荷が減少し、負の固定電荷を生成できたことが分かる。この図８の結果から、イオン種とイオン注入とにより、絶縁層内の固定電荷を制御できることが確認できた。また図７からは、低イオンエネルギーの条件ではイオンの注入深さが酸化シリコン膜厚よりも浅いことから、絶縁層としての機能を損なわずに機能を付加できたことが分かる。 As shown in Figure 8, an increase in positive fixed charges was observed by ion implantation, but it was confirmed that the positive fixed charges could be uniformly reduced by performing heat treatment after ion implantation. Since it is known that defects in silicon oxide generate positive fixed charges, it is believed that the positive charges increased due to the defects generated during ion implantation. It can be seen that by performing heat treatment after ion implantation, the defects were repaired, the positive fixed charges decreased, and negative fixed charges were generated. From the results in Figure 8, it was confirmed that the fixed charges in the insulating layer can be controlled by the ion species and ion implantation. Also, from Figure 7, it can be seen that under low ion energy conditions, the ion implantation depth is shallower than the silicon oxide film thickness, so functions can be added without impairing the function as an insulating layer.
１ ・・・薄膜トランジスタ
２ ・・・基板
３ ・・・チャネル層
４ ・・・ゲート絶縁層
５ ・・・ゲート電極層（キャップ層）
６ ・・・絶縁層
７ ・・・ソース電極層
８ ・・・ドレイン電極層
REFERENCE SIGNS LIST 1 thin film transistor 2 substrate 3 channel layer 4 gate insulating layer 5 gate electrode layer (cap layer)
6: Insulating layer 7: Source electrode layer 8: Drain electrode layer
Claims (9)
前記絶縁層を形成した後、当該絶縁層の表層部にイオン注入を行い、
当該イオン注入後の前記絶縁層の表面に金属膜又は絶縁膜からなるキャップ層を形成し、
前記キャップ層が表面に形成された前記絶縁層に対して熱処理を行うことにより前記絶縁層中に固定電荷を発現させ、
前記イオン注入によるイオンの平均飛程とその標準偏差の和が、前記絶縁層の厚みの半分より小さい、固定電荷制御方法。 1. A method for controlling fixed charge in an insulating layer used in a semiconductor device, comprising:
After forming the insulating layer, ions are implanted into a surface layer of the insulating layer;
forming a cap layer made of a metal film or an insulating film on the surface of the insulating layer after the ion implantation;
a heat treatment is performed on the insulating layer having the cap layer formed on the surface thereof to generate fixed charges in the insulating layer ;
The method for controlling fixed charge , wherein the sum of the average range of the ions by the ion implantation and its standard deviation is smaller than half the thickness of the insulating layer .
前記絶縁層を形成した後、当該絶縁層の表層部にイオン注入を行い、After forming the insulating layer, ions are implanted into a surface layer of the insulating layer;
当該イオン注入後の前記絶縁層の表面に金属膜又は絶縁膜からなるキャップ層を形成し、forming a cap layer made of a metal film or an insulating film on the surface of the insulating layer after the ion implantation;
前記キャップ層が表面に形成された前記絶縁層に対して熱処理を行うことにより前記絶縁層中に固定電荷を発現させ、a heat treatment is performed on the insulating layer having the cap layer formed on the surface thereof to generate fixed charges in the insulating layer;
前記キャップ層が、アルミニウム、アルミニウム合金、モリブデン、モリブデン合金、チタン又はチタン合金からなるものである、固定電荷制御方法。The method for controlling fixed charges, wherein the cap layer is made of aluminum, an aluminum alloy, molybdenum, a molybdenum alloy, titanium, or a titanium alloy.
前記チャネル層を形成する工程と、
前記チャネル層の表面に前記ゲート絶縁層を形成する工程と、
前記ゲート絶縁層の表層部にイオン注入を行う工程と、
イオン注入後の前記ゲート絶縁層の表面に、金属膜又は絶縁膜から成るキャップ層を形成する工程と、
前記キャップ層が表面に形成された前記絶縁層に対して熱処理を行うことにより前記絶縁層中に負の固定電荷を発現させる工程とを含む薄膜トランジスタの製造方法。 A method for manufacturing a top-gate type thin film transistor in which a channel layer made of an oxide semiconductor, a gate insulating layer, and a gate electrode layer are stacked in this order from a substrate side, the method comprising the steps of:
forming the channel layer;
forming the gate insulating layer on a surface of the channel layer;
performing ion implantation on a surface portion of the gate insulating layer;
forming a cap layer made of a metal film or an insulating film on the surface of the gate insulating layer after ion implantation;
and generating negative fixed charges in the insulating layer by performing a heat treatment on the insulating layer having the cap layer formed on the surface thereof.
前記基板の表面に絶縁層を形成する工程と、
前記絶縁層の表層部にイオン注入を行う工程と、
イオン注入後の前記絶縁層の表面に、金属膜又は絶縁膜から成るキャップ層を形成する工程と、
前記キャップ層が表面に形成された前記絶縁層に対して熱処理を行うことにより前記絶縁層中に正の固定電荷を発現させる工程とを含む薄膜トランジスタの製造方法。 A method for manufacturing a top-gate thin film transistor in which a fixed charge layer having a positive fixed charge, a channel layer made of an oxide semiconductor, a gate insulating layer, and a gate electrode layer are stacked in this order from a substrate side, the method comprising the steps of:
forming an insulating layer on a surface of the substrate;
performing ion implantation on a surface portion of the insulating layer;
forming a cap layer made of a metal film or an insulating film on the surface of the insulating layer after the ion implantation;
and generating positive fixed charges in the insulating layer by performing a heat treatment on the insulating layer having the cap layer formed on the surface thereof.
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| CN202380010868.7A CN117501419A (en) | 2022-05-31 | 2023-03-17 | Fixed charge control method and manufacturing method of thin film transistor |
| PCT/JP2023/010545 WO2023233762A1 (en) | 2022-05-31 | 2023-03-17 | Fixed electric charge control method and method for manufacturing thin-film transistor |
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| JP2014036213A (en) | 2012-08-10 | 2014-02-24 | Sharp Corp | Semiconductor device and method for manufacturing the same |
| JP2015057818A (en) | 2013-08-09 | 2015-03-26 | 株式会社半導体エネルギー研究所 | Method for manufacturing semiconductor device |
| JP2019208068A (en) | 2019-08-07 | 2019-12-05 | 株式会社東芝 | Semiconductor device, power source circuit, and computer |
| JP2020150173A (en) | 2019-03-14 | 2020-09-17 | 株式会社ジャパンディスプレイ | Semiconductor device and method for manufacturing the same |
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| JP2011222767A (en) | 2010-04-09 | 2011-11-04 | Sony Corp | Thin film transistor, display device, and electronic device |
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| JP2015057818A (en) | 2013-08-09 | 2015-03-26 | 株式会社半導体エネルギー研究所 | Method for manufacturing semiconductor device |
| JP2020150173A (en) | 2019-03-14 | 2020-09-17 | 株式会社ジャパンディスプレイ | Semiconductor device and method for manufacturing the same |
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