JPS61105870A - Manufacture of thin film transistor - Google Patents
Manufacture of thin film transistorInfo
- Publication number
- JPS61105870A JPS61105870A JP22828584A JP22828584A JPS61105870A JP S61105870 A JPS61105870 A JP S61105870A JP 22828584 A JP22828584 A JP 22828584A JP 22828584 A JP22828584 A JP 22828584A JP S61105870 A JPS61105870 A JP S61105870A
- Authority
- JP
- Japan
- Prior art keywords
- polycrystalline silicon
- deposited
- film
- resist
- interface
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000010409 thin film Substances 0.000 title claims description 16
- 238000004519 manufacturing process Methods 0.000 title claims description 8
- 238000000034 method Methods 0.000 claims abstract description 18
- 239000000758 substrate Substances 0.000 claims abstract description 13
- 239000011521 glass Substances 0.000 claims abstract description 11
- 125000004429 atom Chemical group 0.000 claims abstract description 6
- 239000012535 impurity Substances 0.000 claims abstract description 6
- 125000004430 oxygen atom Chemical group O* 0.000 claims abstract description 6
- 239000010408 film Substances 0.000 claims description 30
- 239000004065 semiconductor Substances 0.000 claims description 9
- 238000000151 deposition Methods 0.000 claims description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 13
- 239000000463 material Substances 0.000 abstract description 4
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 abstract description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 abstract description 2
- 229910052785 arsenic Inorganic materials 0.000 abstract description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 abstract description 2
- 229910052796 boron Inorganic materials 0.000 abstract description 2
- 229910052698 phosphorus Inorganic materials 0.000 abstract description 2
- 239000011574 phosphorus Substances 0.000 abstract description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 2
- 229910052681 coesite Inorganic materials 0.000 abstract 1
- 229910052906 cristobalite Inorganic materials 0.000 abstract 1
- 239000000377 silicon dioxide Substances 0.000 abstract 1
- 235000012239 silicon dioxide Nutrition 0.000 abstract 1
- 229910052682 stishovite Inorganic materials 0.000 abstract 1
- 229910052905 tridymite Inorganic materials 0.000 abstract 1
- 238000005468 ion implantation Methods 0.000 description 8
- 230000007547 defect Effects 0.000 description 5
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 238000007796 conventional method Methods 0.000 description 3
- 239000011229 interlayer Substances 0.000 description 3
- 238000010884 ion-beam technique Methods 0.000 description 3
- 239000010410 layer Substances 0.000 description 3
- 238000004544 sputter deposition Methods 0.000 description 3
- 238000000137 annealing Methods 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/6675—Amorphous silicon or polysilicon transistors
- H01L29/66757—Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78651—Silicon transistors
- H01L29/7866—Non-monocrystalline silicon transistors
- H01L29/78672—Polycrystalline or microcrystalline silicon transistor
- H01L29/78675—Polycrystalline or microcrystalline silicon transistor with normal-type structure, e.g. with top gate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Manufacturing & Machinery (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、ガラス基板を用いた薄膜トランジスタの製造
方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a thin film transistor using a glass substrate.
従来、ガラス基板上に薄膜トランジスタを作製する場合
には、熱酸化法によるゲート絶縁膜を用いることはでき
ないために、一般にＣＶＤ（化学的気相成長）法あるい
は、スパッタ法などの絶縁膜を堆積する方法を用いるの
が一般的である。例えば特許出願公開昭５９−２２８６
５に述べられている。従来方法を第２図に示す。同図（
ａ）のように透明絶縁基板１６に半導体薄膜１７を堆積
させ島状にパターニングし、ゲート絶縁膜１８をＣＶＤ
法あるいはスパッタ法で堆積させ、ゲート電極１９を形
成する。次いで同図（ｂ）に示すようにゲート電極１９
をマスクとし、■族またはＶ族の不純物原子をイオン注
入し、前記半導体薄膜１７中にソース領域側及びドレイ
ン領域２１を形成する。２２はイオンビームを示す。続
いて同図（、ｌｉ）に示すように層間絶縁膜器を堆積さ
せて、コンタクトホールをあは、ソース電極冴及びドレ
イン電極５を形成する。以上述べたように、フォト４工
程で作製される。Conventionally, when manufacturing a thin film transistor on a glass substrate, it is not possible to use a gate insulating film using a thermal oxidation method, so an insulating film is generally deposited using a CVD (chemical vapor deposition) method or a sputtering method. It is common to use a method. For example, patent application publication 1986-2286
5. The conventional method is shown in FIG. Same figure (
As shown in a), a semiconductor thin film 17 is deposited on a transparent insulating substrate 16 and patterned into an island shape, and a gate insulating film 18 is formed by CVD.
The gate electrode 19 is formed by depositing by a method or a sputtering method. Next, as shown in FIG.
Using this as a mask, ion implantation of group (I) or group V impurity atoms is performed to form a source region side and a drain region 21 in the semiconductor thin film 17. 22 indicates an ion beam. Subsequently, as shown in the same figure (11), an interlayer insulating film is deposited, a contact hole is formed, and a source electrode and a drain electrode 5 are formed. As described above, it is manufactured through four photo steps.
しかしながら、従来の方法では、ゲート絶縁膜も半導体
薄膜上に堆積させるだけなので、その界面単位や、欠陥
準位は非常に多い。界面準位が多いために、トランジス
タの７ｔｈ（スレッシュホルド電圧）が高い。さらに欠
陥準位が電子や正孔をトラップするためにデバイスとし
ての安定性力・び信頼性が低下する。However, in the conventional method, the gate insulating film is simply deposited on the semiconductor thin film, so there are a large number of interface units and defect levels. Since there are many interface states, the 7th (threshold voltage) of the transistor is high. Furthermore, since the defect level traps electrons and holes, the stability and reliability of the device decrease.
また、半導体薄膜の膜厚が、ソース領域、ドレイン領域
、チャネル領域にわたってすべて同一である。従って、
トランジスタのＯＦＦ電流を低けるために半導体薄膜を
薄くすると、ソース電極及びドレイン電極とソース領域
及びドレイン領域とのコンタクト抵抗が増大してしまう
。一方、該コンタクト抵抗を低減するために半導体薄膜
の膜厚を厚くすると、逆にＯＦＦ電流が増大し、どちら
にしろ９Ｎ１０ＦＦ比（ＯＮ電流とＯＦＦ電流の比）を
大きくすることができないという欠点を有する。Further, the thickness of the semiconductor thin film is the same throughout the source region, drain region, and channel region. Therefore,
If the semiconductor thin film is made thinner in order to lower the OFF current of the transistor, the contact resistance between the source electrode and the drain electrode and the source region and the drain region increases. On the other hand, if the thickness of the semiconductor thin film is increased to reduce the contact resistance, the OFF current will increase, and in any case, the disadvantage is that the 9N10FF ratio (ratio of ON current to OFF current) cannot be increased. have
本発明の薄膜トランジスタの製造方法は、ガラス基板上
に、島状に半導体薄膜を形成する工程とゲート絶縁膜を
堆積させる工程と、チャネル領域を構成する界面に酸素
原子をイオン注入する工程とリフトオフ法によりゲート
電極を形成する工程と前記ゲート電極をマスクとし、■
族あるいはＶ族の不純物原子をイオン注入して、ソース
領域及びドレイン領域を形成する工程から成ることを特
徴とする。The method for manufacturing a thin film transistor of the present invention includes a step of forming an island-shaped semiconductor thin film on a glass substrate, a step of depositing a gate insulating film, a step of ion-implanting oxygen atoms into an interface forming a channel region, and a lift-off method. A step of forming a gate electrode by using the gate electrode as a mask,
It is characterized by comprising a step of ion-implanting group or V group impurity atoms to form a source region and a drain region.
第１図に、半導体薄膜として多結晶シリコンを用いた場
合の実施例を示す。第１図（Ｇ）において、ガラス基板
１上に、多結晶シリコン膜２を堆積させ島状にパターニ
ングする。その上にゲート酸化膜５ｉ０２３を堆積させ
る。該ゲート酸化膜の堆積方法としては、ＣＶＤ法ある
いはプラズマＣＶＤ法あるいはスパッタ法などのように
生成温度の低い（約６００℃以下）方法を採用する。こ
れは前記ガラス基板（コーニング７０５９など）の伸び
あるいはソリを防ぐためである。次に同図（ｂ）に示す
ようにレジスト４を形成する。続いて、同図（Ｃ）に示
すように、前記レジスト４をマスクとし、多結晶シリコ
ン膜２中のチャネル領域を構成する４一
部分にイオン打込み法により酸素原子を注入する。FIG. 1 shows an example in which polycrystalline silicon is used as the semiconductor thin film. In FIG. 1(G), a polycrystalline silicon film 2 is deposited on a glass substrate 1 and patterned into an island shape. A gate oxide film 5i023 is deposited thereon. As a method for depositing the gate oxide film, a method having a low formation temperature (approximately 600° C. or lower) such as a CVD method, a plasma CVD method, or a sputtering method is employed. This is to prevent the glass substrate (such as Corning 7059) from elongating or warping. Next, a resist 4 is formed as shown in FIG. 4(b). Subsequently, as shown in FIG. 1C, oxygen atoms are implanted into a portion of polycrystalline silicon film 2 constituting a channel region by ion implantation using resist 4 as a mask.
この場合、ゲート酸化膜８を通して酸素原子をイオン注
入することになるので、イオン注入により形成されるＳ
ｉＯ２層と、堆積により形成された前記ゲート酸化膜８
との間にｓ７層が残らないようにイオン打込み条件を設
定しなければならない。In this case, since oxygen atoms are ion-implanted through the gate oxide film 8, S
iO2 layer and the gate oxide film 8 formed by deposition
Ion implantation conditions must be set so that no s7 layer remains between the two.
このようにして多結晶シリコン膜２中に、新しい界面５
が形成される。図中６は酸素のイオンビームを示してい
る。続いて、同図（めに示すようにレジスト４を残した
状態でゲート電極を構成する材料７と８と９を堆積させ
る。該ゲート電極材料としてはＩＴＯ（透明導電膜）あ
るいはアルミニウムなどの低抵抗材料を用いる。耐熱性
の優れたレジストを使うことができれば、多結晶シリコ
ン膜をゲート電極として用いることもできる。次に前記
レジスト４を剥離し、リフトオフ法によってゲート電極
９を形成する。このようにして同図（ｅ）に示すような
構造となる。次に同図のに示すように前記ゲート電極９
をマスクとして■族（ボロン）あるいは■族（リン、ヒ
素など）不純物原子をイオン注入し、ソース領域１０及
びドレイン領域１１を形成する。図中１２は不純物原子
のイオンビームを示す。ここでイオン打込みによるダメ
ージが考えられる場合には、レーザ−７ニールあるいは
電子ビームアニールなどの処理を行なう。たソしガラス
基板が損傷を受けないように、ガラス基板をあらかじめ
酸化膜でコーディングしておいたほうがよい。最後に同
図ω）に示すように層間絶縁膜１３を堆積させ、コンタ
クトホールをあけて、ソース電極１４及びドレイン電極
１５を形成する。In this way, a new interface 5 is created in the polycrystalline silicon film 2.
is formed. In the figure, 6 indicates an oxygen ion beam. Next, as shown in the same figure, materials 7, 8, and 9 constituting the gate electrode are deposited with the resist 4 remaining.As the gate electrode material, a low-resistance material such as ITO (transparent conductive film) or aluminum is used. A resistive material is used. If a resist with excellent heat resistance can be used, a polycrystalline silicon film can also be used as the gate electrode. Next, the resist 4 is peeled off and a gate electrode 9 is formed by a lift-off method. In this way, a structure as shown in the figure (e) is obtained.Next, as shown in the figure, the gate electrode 9 is
Using the mask as a mask, ion implantation of ■ group (boron) or ■ group (phosphorus, arsenic, etc.) impurity atoms is performed to form a source region 10 and a drain region 11. In the figure, 12 indicates an ion beam of impurity atoms. If damage due to ion implantation is suspected, treatment such as laser-7 annealing or electron beam annealing is performed. To prevent damage to the glass substrate, it is better to coat the glass substrate with an oxide film in advance. Finally, as shown in ω) in the figure, an interlayer insulating film 13 is deposited, contact holes are made, and a source electrode 14 and a drain electrode 15 are formed.
なお、実施例では信頼性の良い多結晶シリコン膜を用い
た場合について説明したが、非晶質シリコン膜を用いた
場合にも、本発明は同様に応用することができる。また
、同図（１７）に述べた層間絶縁膜１３は必要なければ
形成しなくてもよい。In the embodiment, a case where a highly reliable polycrystalline silicon film is used has been described, but the present invention can be similarly applied to a case where an amorphous silicon film is used. Furthermore, the interlayer insulating film 13 described in FIG. 17 (17) may not be formed if it is not necessary.
このように本発明は、酸素のイオン注入により多結晶シ
リコン膜中に界面を形成しているので、界面準位や欠陥
密度は非常に少ない。従ってトランジスタのｖｔｈを低
くおさえることができる。As described above, in the present invention, since the interface is formed in the polycrystalline silicon film by oxygen ion implantation, the interface states and defect density are extremely small. Therefore, the vth of the transistor can be kept low.
さらに界面のトラップ準位が小さいのでトランジスタ特
性の安定性を向上させることができ、デバイスの信頼性
改善に大きな役割りをはたす。しい為も低温プロセス（
約６００℃以下）で作製する（二とができるので、高温
加熱により生じる欠陥（オ、、を層欠陥や転位など）を
考慮する必要がまったくない。さらには低コスト化、基
板の大面積化も可能となる。Furthermore, since the trap level at the interface is small, the stability of transistor characteristics can be improved, which plays a major role in improving device reliability. Low temperature process (
Since it can be fabricated at a temperature of approximately 600°C or below), there is no need to consider defects caused by high-temperature heating (e.g., layer defects, dislocations, etc.).In addition, costs can be reduced and the substrate area can be increased. is also possible.
また本発明ではイオン打込みによりゲート酸化膜を形成
するのでゲート酸化膜厚の制御性が改善される。さらに
酸累のイオン注入条件を任意に設定することにより、チ
ャネル領域の多結晶シリコン膜厚を、ソース領域及びド
レイン領域の多結晶シリコン膜厚よりも制御性良く薄く
することができる。このようにソース領域及びドレイン
領域の膜厚は厚く、チャネル領域の膜厚は薄くできるの
で、薄膜トランジスタのＯＦＦ電流は低減され、ソース
領域及びドレイン領域とソース電極及びドレイン電極と
のコンタクト抵抗は低減される。従って、０Ｎ１０ＦＦ
比が増大される。Further, in the present invention, since the gate oxide film is formed by ion implantation, controllability of the gate oxide film thickness is improved. Furthermore, by arbitrarily setting the conditions for ion implantation of the oxide, the thickness of the polycrystalline silicon film in the channel region can be made thinner with better control than the thickness of the polycrystalline silicon film in the source and drain regions. In this way, the film thickness of the source region and drain region can be made thick and the film thickness of the channel region can be made thin, so that the OFF current of the thin film transistor is reduced and the contact resistance between the source region and drain region and the source electrode and drain electrode is reduced. Ru. Therefore, 0N10FF
The ratio is increased.
また、ゲート電極はリフトオフ法により形成されるので
フォト工程が増えることな〈従来方法と同様に、フォト
４工程で作製できる。In addition, since the gate electrode is formed by a lift-off method, the number of photo steps is not increased (it can be produced in four photo steps as in the conventional method).
このように、本発明は、■ｔんが小さく、ＯＮ／ ＯＦ
Ｆ比が大きく、動作速度の速い薄膜トランジスタをガ
ラス基板上に実現し、しかも、その信頼性を向上させて
フォト４工程で作製する方法を提供するものである。In this way, the present invention has a small t and ON/OF
The present invention provides a method for realizing a thin film transistor with a large F ratio and a high operating speed on a glass substrate, improving its reliability, and manufacturing it in four photo steps.
第１図（、ｚ）〜ω）は本発明の製造方法を示す工程図
であり、第２図＜ａ）〜（Ｃ）は従来の製造方法を示す
工程図である。
１・・・ガラス基板
２・−・多結晶シリコン膜
８・・・ゲート酸化膜
４・ｅ・レジスト
５・・ψ界面FIG. 1 (, z) to ω) are process diagrams showing the manufacturing method of the present invention, and FIGS. 2<a) to (C) are process diagrams showing the conventional manufacturing method. 1... Glass substrate 2... Polycrystalline silicon film 8... Gate oxide film 4... Resist 5... ψ interface
Claims (1)
ゲート絶縁膜を堆積させる工程と、チャネル領域を構成
する界面に酸素原子をイオン注入する工程と、リフトオ
フ法によりゲート電極を形成する工程と、前記ゲート電
極をマスクとし、III族あるいはＶ族の不純物原子をイ
オン注入して、ソース領域及びドレイン領域を形成する
工程を含むことを特徴とする薄膜トランジスタの製造方
法。a step of forming an island-shaped semiconductor thin film on a glass substrate;
A step of depositing a gate insulating film, a step of ion-implanting oxygen atoms into the interface constituting the channel region, a step of forming a gate electrode by a lift-off method, and a step of depositing group III or group V impurities using the gate electrode as a mask. 1. A method of manufacturing a thin film transistor, comprising the step of ion-implanting atoms to form a source region and a drain region.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22828584A JPS61105870A (en) | 1984-10-30 | 1984-10-30 | Manufacture of thin film transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22828584A JPS61105870A (en) | 1984-10-30 | 1984-10-30 | Manufacture of thin film transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61105870A true JPS61105870A (en) | 1986-05-23 |
Family
ID=16874074
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP22828584A Pending JPS61105870A (en) | 1984-10-30 | 1984-10-30 | Manufacture of thin film transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61105870A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5702960A (en) * | 1994-02-25 | 1997-12-30 | Samsung Electronics Co., Ltd. | Method for manufacturing polysilicon thin film transistor |
| US6214684B1 (en) * | 1995-09-29 | 2001-04-10 | Canon Kabushiki Kaisha | Method of forming a semiconductor device using an excimer laser to selectively form the gate insulator |
| US6391701B1 (en) | 1999-05-18 | 2002-05-21 | Nec Corporation | Semiconductor device and process of fabrication thereof |
| EP1533838A2 (en) * | 2003-11-24 | 2005-05-25 | Samsung SDI Co., Ltd. | Method for manufacturing transistor and image display device using the same |
| US20160315200A1 (en) * | 2015-04-21 | 2016-10-27 | Incheon University Industry Academic Cooperation Foundation | Method of manufacturing amorphous igzo tft-based transient semiconductor |
| CN110265303A (en) * | 2019-06-12 | 2019-09-20 | 深圳市华星光电半导体显示技术有限公司 | A kind of production method of display panel |
-
1984
- 1984-10-30 JP JP22828584A patent/JPS61105870A/en active Pending
Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5702960A (en) * | 1994-02-25 | 1997-12-30 | Samsung Electronics Co., Ltd. | Method for manufacturing polysilicon thin film transistor |
| US6214684B1 (en) * | 1995-09-29 | 2001-04-10 | Canon Kabushiki Kaisha | Method of forming a semiconductor device using an excimer laser to selectively form the gate insulator |
| US6391701B1 (en) | 1999-05-18 | 2002-05-21 | Nec Corporation | Semiconductor device and process of fabrication thereof |
| EP1533838A2 (en) * | 2003-11-24 | 2005-05-25 | Samsung SDI Co., Ltd. | Method for manufacturing transistor and image display device using the same |
| EP1533838A3 (en) * | 2003-11-24 | 2005-08-03 | Samsung SDI Co., Ltd. | Method for manufacturing transistor and image display device using the same |
| US7199406B2 (en) | 2003-11-24 | 2007-04-03 | Samsung Sdi Co., Ltd. | Method for manufacturing transistor and image display device using the same |
| US7615803B2 (en) | 2003-11-24 | 2009-11-10 | Samsung Mobile Display Co., Ltd. | Method for manufacturing transistor and image display device using the same |
| US7951658B2 (en) | 2003-11-24 | 2011-05-31 | Samsung Mobile Display Co., Ltd. | Method for manufacturing diode-connected transistor and image display device using the same |
| US20160315200A1 (en) * | 2015-04-21 | 2016-10-27 | Incheon University Industry Academic Cooperation Foundation | Method of manufacturing amorphous igzo tft-based transient semiconductor |
| US10134913B2 (en) * | 2015-04-21 | 2018-11-20 | Incheon University Industry Academic Cooperation Foundation | Method of manufacturing amorphous IGZO TFT-based transient semiconductor |
| CN110265303A (en) * | 2019-06-12 | 2019-09-20 | 深圳市华星光电半导体显示技术有限公司 | A kind of production method of display panel |
| CN110265303B (en) * | 2019-06-12 | 2021-04-02 | 深圳市华星光电半导体显示技术有限公司 | Manufacturing method of display panel |
| US11158724B1 (en) | 2019-06-12 | 2021-10-26 | Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd. | Method of manufacturing display panel |
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