JPS6265465A - Manufacture of insulated-gate type semiconductor device - Google Patents

Abstract

PURPOSE:To obtain a dielectric strength which is equivalent to the dielectric strength of an ordinary low impurity concentration structure without additional processes by a method wherein ion implantation energy is predetermined by taking the thicknesses of spacers in contact with both sides of a gate and the thickness of a gate oxide film into account and then an impurity is introduced. CONSTITUTION:An isolation oxide (SiO2) film 2, a thin gate oxide film 3 and a polycrystalline Si gate 4 are formed on an Si substrate 1. Then a silicon oxide film 5 is formed over the whole surface in order to form spacers and the parts of the silicon oxide film 5 in contact with the sides of the gate 4 are left as spacers while the other part of the silicon oxide film 5 is removed. Then ion implantation of arsenic is applied over the whole surface and the N-type impurity is introduced into the sub strate surface. In this case, ion implantation energy is predetermined by taking the thicknesses of the spacers and the thickness of the gate oxide film 3 into account so as to have As ions introduced into the Si substrate perfectly with high concentration where the spacer does not exist and introduced a little directly under the spacers too. Then annealing is carried out to diffuse As ions in the silicon substrate to form N<+>type layers which are to be source and drain and an N<-> type layer which is to be an offset gate.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to an insulated gate semiconductor device, particularly a short channel MO8
This article relates to technology for improving hot carrier resistance of FETs.

[Background technology]

CMOS devices have the current state-of-the-art gate length of 1, 2~
As the size becomes smaller from 1.3 μm to O.S. μm to 0.5 μm, hot carriers and short channel effects tend to become more severe.

The short channel effect is a phenomenon in which the source and drain become close to each other, resulting in a decrease in the threshold voltage and punch-through voltage due to the influence of the voltage at the channel part. The voltage begins to drop rapidly.

On the other hand, the hot carrier effect is a phenomenon in which electrons flowing through the channel are scattered and injected in the direction of the gate.The higher the drain voltage, the more likely it is to occur, and the injection deteriorates the gate insulating film, resulting in deterioration of transistor characteristics. bring about.

To solve these problems, the n-channel MO3FET uses an LDD (low impurity concentration drain) structure. It is described on days p136-p140.

In the LDD structure, an offset gate layer with a low impurity concentration is formed on the substrate surface between the gate and the source/drain to increase punch-through voltage and hot carrier breakdown voltage.

FIG. 7 shows a cross-sectional view of an example of a C-MOSFET having an LDD structure.

In the figure, 4 is a gate, 6 is a spacer, and 7 is a source/drain/high impurity concentration layer. n channel MO8F
On the ET side, an offset gate 8 made of a single layer of low impurity concentration n formed by LDD&C connects the channel part and the source/drain n+
formed between the layers.

In order to obtain a unique LDD structure, a manufacturing method as shown in FIGS. 8 to 10 has been adopted so far.

That is, (1) as shown in FIG. 8, a gate (poly 51) 4 is formed on the insulating film 3, and low concentration n impurity ions are implanted using the gate as a mask. f21 1st
As shown in the figure, spacers 6 made of an insulator are formed on both sides of the gate 40, and high concentration n impurity ions are implanted using the spacers 6 and the gate 4 as masks. (3) Perform annealing (heat treatment) and as shown in FIG.
self-aligned).

In this conventional method, the offset layer) n layer 8 and the source layer are
For the drain n layer 7, ion implantation is required for each K layer. This example is an LDD structure with only n-MO8FET, but in this case, an extra step for fC4, n- impurity ion implantation is added. p with C-MOSFET
If a simple structure including a channel MO8FET or an LDD structure is required for both n-channel and p-channel,
The inventors have clarified that by adding the n-impurity ion implantation and photoresist process, and the p-impurity ion implantation and photoresist process, the number of processes becomes extremely large, resulting in an unavoidable increase in cost.

[Purpose of the invention]

The present invention has been made to overcome the above-mentioned problems, and its purpose is to provide a method for manufacturing an MO8 semiconductor device that can obtain the same breakdown voltage as a normal LDD structure without doubling the number of steps. It is in.

The above and other objects and novel features of the present invention include:
It will become clear from the description of this specification and the attached drawings.

[Summary of the invention]

A brief overview of typical inventions disclosed in this application is as follows.

That is, K forming the KMO8FET on the semiconductor substrate surface
For example, an insulated gate made of poly-Si is formed on the surface of a p-type semiconductor substrate via a gate oxide film, and spacers in contact with both sides of this gate are formed of an insulating material.
High-concentration impurity ions are implanted into the substrate surface by applying mask pressure to the gate having this spacer, and by adjusting the ion implantation energy taking into account the thickness of the spacer, source and drain can be formed on the substrate surface where no spacer is formed. By this method, a high impurity concentration layer is formed, and at the same time, a low impurity concentration layer is formed as an offset trap immediately below the spacer.

An MO8 semiconductor device having a counter pressure equivalent to that of a normal LDD structure can be obtained without increasing the number of steps.

The above objective can be achieved.

〔Example〕

1 to 5 show one embodiment of the present invention, and are sectional views of main steps in the manufacturing process of an n-channel MO8FET having an LDD structure. below.

Each step will be explained in detail.

(1) In Figure 1, 1 is a high resistivity p-type single crystal S
t substrate, 2 is isolation oxide (
3 is a thin (500-1000^) gate oxide film generated on the surface of the St substrate by thermal oxidation, and 4 is a poly-Si gate, which is a poly-Si gate deposited on the gate oxide film 3 to a thickness of 3000A. The Si is patterned to a predetermined gate length by photoetching.

(2) Full-surface KC as shown in Figure 2 for spacer formation.
An insulator made of VD (Chemical Vapor Deposition) K, such as a silicon oxide film 5, is formed by high temperature and low pressure growth.

(3) For example, dry etching the silicon oxide film using CF4 gas, etc., and taking advantage of the phenomenon that the part in contact with the side surface of the gate is less likely to be etched than the part further away, the third
As shown in the figure, the other silicon oxide film is removed, leaving the portion in contact with the side surface of the gate as a spacer. The width a and thickness b of this spacer are about 2000A.

(4) Arsenic (As) ions are implanted into the entire surface, and Kn-type impurities are introduced into the substrate surface at 5 as shown in FIG. The ion implantation energy at this time is about 400 K e V, and the isolation oxide film 2 and gate 4 serve as masks to implant As into the substrate surface through the thin insulating film. In this case, As is completely 8 in the part without spacer.
High concentration (dose amount I x 10” Ato
ms-”cy, beak 2×10!OAtoms-”c
ln), and set the ion implantation energy in consideration of the spacer thickness, gate fostering film thickness, etc. so that the ion implantation energy is introduced just below the spacer (peak dose I x 10"Atoms-"cnl). (5) Annealing is performed to diffuse Aa in the SiSicon substrate to form an n+ layer that will become a source/drain and an n layer that will become an offset gate, as shown in FIG.

(6) After this, the entire surface K CV D-8jo2M1
9k is generated, contact photolithography is performed to open the source/drain regions, AJ is evaporated (sputtered) and photoetched to form the A2 electrode 10, and the L as shown in FIG. 6 is formed.
A DD structure n-channel MO3FET is completed.

〔effect〕

According to the present invention explained in the examples, the following effects are brought about.

By introducing impurities by setting the ion implantation energy in consideration of the thickness of the spacer in contact with both sides of the gate and the thickness of the gate oxide film, regions with high impurity concentration and regions with low impurity concentration are created on the St substrate surface, unlike conventional methods. For example, it is possible to perform selective ion implantation with one ion implantation instead of two ion implantations. In other words, normal L without increasing engineering a
A breakdown voltage equivalent to that of the DD structure can be obtained. For example, when ions are implanted without a spacer, the breakdown voltage is about 5.0V, but by effectively using the spacer and providing a single layer, the breakdown voltage is 8.5 to 9. I was able to make it Ov.

Although the invention has been specifically described above based on embodiments made by the present inventor, the present invention is not limited to the embodiments, and can be modified in various ways without departing from the gist thereof.

For example, in C-MO8IC, n-channel MO8F
When both the ET and the p-channel MO8FET have an LDD structure, impurity ion implantation is only required once for each, so the number of mask steps can be significantly reduced, leading to cost savings.

[Application field]

The present invention is an n-channel MO8FET, 0MO8IC.

It can be applied to any bipolar CMO8IC.

[Brief explanation of drawings]

FIGS. 1 to 6 are process cross-sectional views showing one embodiment of the process of the present invention. FIG. 7 is a sectional view showing an example of an LDD structure CMO8FET. Figures 8 to 10 show the conventional LDD structure MO8FE.
It is a process sectional view showing the process of T. DESCRIPTION OF SYMBOLS 1... p''-Si substrate, 2... Isolation oxide film, 3... Gate oxide film, 4... Poly Sl gate, 5... HLO film, 6... Spacer, 7...Source/drain n+ layer, 8...Offset gate n single layer, 9...C Fig. 1 Fig. 2 Fig. 3 Fig. 7 Fig. 8

Claims (1)

[Claims] 1. In forming an insulated gate field effect transistor on the surface of a semiconductor substrate, a gate is formed on one main surface of the semiconductor substrate of the first conductivity type with an insulating film interposed therebetween, and both sides of the gate are By forming a spacer made of an insulator in contact with the surface, and then implanting high-concentration impurity ions into the substrate surface using the gate as a mask, adjusting the ion implantation energy in consideration of the thickness of the spacer. A method for manufacturing an insulated gate semiconductor device, comprising forming a low resistivity layer serving as a source/drain in a surface portion of a substrate where a spacer is not formed, and forming a high resistivity layer immediately below the spacer. 2. The above spacer is made by forming an insulator over the entire surface of the gate using chemical vapor deposition, and then etching the entire surface, so that the spacer remains in a self-aligned manner at the portions that contact both sides of the gate. A method for manufacturing an insulated gate semiconductor device according to claim 1.