JP2008252123A - Solid-state imaging device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To widen a dynamic range by precisely forming the concentration and width of a bypass region between a photodiode and a transfer switch. <P>SOLUTION: A solid-state image sensor comprises, within each pixel, a semiconductor region 1102 of a first conductivity type, a photodiode 1104 formed in the semiconductor region, a transfer MOS transistor 1103 for transferring a photoelectric charge accumulated in the photodiode, and a region for receiving the transferred the photoelectric charge, wherein a region 1106 continuous from the photodiode 1104 extends under the control electrode of the transfer MOS transistor 1103, and a diffused floating region 1107 that functions as a region for receiving the photoelectric charge has an LDD structure. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a solid-state imaging device, and more particularly to a solid-state imaging device having a signal amplification unit for each pixel.

  Typical solid-state imaging devices include a CCD sensor composed of a photodiode and a CCD shift register, and a CMOS sensor such as an APS (Active Pixel Sensor) composed of a photodiode and a MOS transistor.

  APS includes a photodiode, a MOS switch, an amplifier circuit for amplifying the signal from the photodiode for each pixel, and has many advantages such as "XY addressing" and "single chip of sensor and signal processing circuit". have. However, on the other hand, since the number of elements in one pixel is large, it is difficult to reduce the pixel aperture ratio and to reduce the chip size that determines the size of the optical system, and the CCD occupies most of the market. ing.

  In recent years, it has attracted attention due to the improvement in the miniaturization technology of MOS transistors and the increasing demand for “single-chip sensor and signal processing circuit” and “low power consumption”.

  FIG. 11 shows an equivalent circuit diagram of a pixel portion of a conventional APS and a solid-state imaging device using the pixel portion. These are reported in Non-Patent Document 1. The configuration of the prior art will be briefly described below.

The photoelectric conversion unit is an embedded photodiode used in a CCD or the like. The embedded photodiode suppresses the dark current generated on the SiO ₂ surface by providing a thick p layer on the surface, and also provides a junction capacitance between the n layer of the storage portion and the p layer on the surface. And the saturation charge amount of the photodiode can be increased.

The optical signal charge Q _sig accumulated in the photoelectric conversion unit PPD is read out to a floating diffusion area through a transfer unit TX made of a MOS transistor.

The capacity _{C FD} of the floating diffusion region, converted into a voltage to the signal charge _Q sig _{/ C FD,} reads the signal through the source follower circuit.
1995 IEEE Work Shop; Eric R. Fossum, etc.

  However, in the prior art, the n layer that is the charge storage portion is located at a portion away from the surface, and in order to read the charge from here to the floating diffusion region, the MOS transistor (transfer MOS transistor) used in the transfer portion is used. It was necessary to apply a higher voltage to the control electrode than a normal MOS transistor.

FIG. 3 is a diagram showing the potentials of the channel portions of a normal MOS transistor and a transfer MOS transistor. According to the figure, light is incident from the left side of the figure, and a transparent insulating film such as transparent SiO ₂ , SiN, etc., a dark p layer of a photodiode, and an n layer are sequentially laminated on the right side. At this time, a level change curve indicated by the potential at the time of application is represented.

  That is, as shown in the potential diagram of FIG. 3, since the n layer is in a portion away from the surface, it is necessary to bend the potential more greatly.

A threshold voltage _Vth of a normal MOS transistor is given by the following equation.

Here, φ _F is Fermi potential, Vs is substrate bias ε _Si , Si dielectric constant q is electron charge amount Nsub is substrate impurity concentration V _FB is flat band voltage C _OX is floating diffusion On the other hand, the threshold voltage _Vth of the transfer MOS transistor from the embedded photodiode is given by the following equation. X _j is the junction depth of the p layer on the surface of the photodiode portion.

  The difference between the two becomes more prominent as the substrate concentration is higher. Therefore, the higher the substrate concentration is associated with the miniaturization of elements, the more difficult it is to read out charges.

Specifically, the threshold voltage of the embedded source is about 0.7 volt while the threshold voltage of the normal MOS transistor is about 0.7 volt at the oxide film thickness of 15 nm and the p-type well concentration of 8 × 10 ¹⁶ cm ⁻³ . Reaches 5.0 volts. In the prior art, as the threshold voltage increases, almost all charges cannot be read from the photodiode. As a result, there is a problem in that unread reading of charges occurs in the photodiode, resulting in an afterimage or noise, and the image is significantly deteriorated.

  In order to solve this problem, the inventors provided a region of the same conductivity type as that of the charge storage layer between the photodiode and the transfer MOS transistor as shown in FIG. For example, an n-type impurity region is provided in the case of a photodiode comprising an n-type charge storage portion in a p-type well and a thick p-type surface layer on the surface of the charge storage portion. Hereinafter, this region is referred to as a bypass region. As a result, the electrons in the charge storage section pass through the surface of the transfer MOS transistor via the bypass region having a low potential and reach floating diffusion, so that the threshold voltage of the transfer MOS transistor can be made smaller than in the prior art.

  However, the concept of the bypass region has already been implemented in an imaging device using a CCD shift register. As shown in FIG. 12B, the Television Society Technical Report Vol. 13, no. 11 reported. The fact that the bypass region is produced by shifting the p-layer having a thick surface with a mask is explained by forming a p-layer having a thick surface by providing a resist as shown in FIG.

The bypass area must satisfy the following conditions:
1) A certain level of concentration and width are required to function as a bypass region. 2) The depletion transfer causes the bypass region to be depleted for all readout conditions. That is, the concentration and width of the bypass region are lower than 1). 2) determines the upper limit. As the substrate density increases as the pixels are reduced, the allowable range of the density and width of the bypass region is reduced.

Further, when a CCD shift register is used, there are the following restrictions on the configuration.
1) The density of the n region which is the channel region of the vertical CCD shift register corresponding to the drain region of the transfer MOS transistor is low. 2) The difference between the gate voltage of the transfer MOS transistor and the voltage of the drain region (channel region of the vertical CCD shift register). As a result, in an imaging device using a CCD shift register, the electric lines of force from the drain region of the transfer MOS transistor are not on the photodiode side. Has no effect.

On the other hand, this invention has the following characteristics on the structure.
1) The drain region of the transfer MOS transistor is a dense n-type impurity region which is a diffusion floating region. 2) The drain voltage can be controlled independently of the gate voltage. A photoelectric conversion unit having a second semiconductor region of a second conductivity type and a third semiconductor region of the first conductivity type provided in contact with the light incident side of the second semiconductor region;
A fourth semiconductor region of the second conductivity type in the first semiconductor region;
A first semiconductor region between the photoelectric conversion unit and the fourth semiconductor region for transferring the signal charge accumulated in the photoelectric conversion unit to the fourth semiconductor region, the first semiconductor region A charge transfer unit having an upper insulating film and a control electrode on the insulating film;
In a solid-state imaging device having at least
The second semiconductor region is provided to extend under the control electrode;
The fourth semiconductor region has an LDD structure.

  As a result, in the present invention, the electric lines of force from the drain region can act on the photodiode side, and this effect has the effect of assisting the extraction of electrons from the charge storage layer.

  Therefore, the allowable range of the concentration and width of the bypass region described above can be expanded as compared with the conventional case. The state of the potential of the present invention is shown in FIG.

According to the present invention, the dynamic range can be widened by reducing the threshold value of the transfer MOS transistor that transfers the photocharge accumulated in the photodiode of the solid-state imaging device. In particular, a diffusion floating region in the bypass region that can effectively transfer the accumulated charge of electrons or holes between the photodiode and the control electrode of the transfer MOS transistor is provided.
1) The impurity concentration of the diffusion floating region can be set high, and the depletion layer generated between the well and the diffusion floating region can be effectively expanded to the p-type well side by the bias applied to the control electrode of the transfer switch. This is because a voltage (reset voltage) at the time of reading can be input arbitrarily and directly.

  2) A wide dynamic range that can be controlled by an external voltage can be ensured against a small dynamic range that can be determined by the built-in potential of the impurity profile, as in a CCD sensor.

  3) By optimizing the voltage at the time of reading, the potential barrier in the vicinity of the bypass region is moderately pushed down to make it easier to read the photocharges.

  FIG. 1 is a cross-sectional structure diagram that best represents the features of the present invention. In FIG. 1, the photoelectric conversion element is formed by forming a p-type well 102 on an n-type substrate 101, forming a photodiode n-layer 104 thereon, and forming a photodiode p-layer 105 thereon with a thickened surface. The gate region 103 of the transfer MOS transistor is formed on the side surface of the photodiode via an insulating layer, and a bypass region 106 continuous from the n layer of the photodiode is formed between the gate region 103 of the transfer MOS transistor and the side surface of the photodiode. Has been.

  In addition, a diffusion floating region FD107 is formed below the side surface of the gate region 103 of the transfer MOS transistor. The diffusion floating region FD107 is connected to the gate of the amplification MOS transistor of the output circuit, and the source of the amplification MOS transistor includes The drain of the row selection switch MOS transistor 111 is connected, and the source of the row selection switch MOS transistor 111 is connected to a current source I112 serving as a load of the amplification MOS transistor to constitute a source follower amplifier circuit.

  The diffusion floating region FD107 is connected to the source of a reset MOS transistor for resetting the diffusion floating region FD107, and the drain is connected to the reset power source 109.

Next, features of the present invention will be described in detail while explaining a read operation. Light enters and electrons generated by photoelectric conversion accumulate in the n-layer of the photodiode. At this time, the transfer MOS transistor is in an OFF state. After a predetermined accumulation time has elapsed, a positive voltage is applied to the control electrode (gate region) 103 of the transfer MOS transistor, the transfer MOS transistor is turned on, and the accumulated charge in the n layer of the photodiode is transferred to the diffusion floating region. . Before the transfer MOS transistor is turned on, the diffusion floating region is reset to a predetermined voltage in advance. When the accumulated charge is transferred to the diffusion floating region, the voltage of the diffusion floating region is Q _sig / C _FD because the transfer charge is an electron when the transfer charge Q _sig and the diffusion floating capacitance C _FD are used. Decreases from reset voltage. If the storage layer of the photodiode is p-type, since the transfer charge is a hole, the voltage rises conversely.

In such an APS, the output signal V _r1 immediately after the reset of the diffusion floating region 107 is temporarily held, and the difference (V _sig1 −V _r1 ) from the output signal V _sig1 superimposed on the reset signal by Q _sig / C _FD. ), Most of the reset noise in the diffusion floating region 107 can be removed. In particular, when the photodiode and the transfer MOS transistor 103 satisfy the conditions described below, a higher noise removal rate is achieved. In other words, it is important to read out the signal charge accumulated in the n layer of the photodiode at a higher rate.

More specifically, if the voltage in the diffusion floating region, which is lower than the reset voltage after reading the signal by the voltage of Q _sig / C _FD , is VFD _{sig 1} , and the transfer MOS transistor is in a sufficiently ON state, the n layer of the photodiode A reverse bias of VFD _sig1 is applied to the GND potential of the p-type well and the deep p-layer on the surface. At this time, in the n layer, a depletion layer extends from the p-type well and the deep p layer on the surface, and the entire n layer of the photodiode is depleted, so that the signal charge is left in the diffusion floating region without leaving almost any signal charge in the photodiode. Can be read out.

In this case, the photodiode is reset simultaneously with reading out the signal charges to the diffusion floating region. If the number of electrons remaining in the n layer is 0 after reading, that is, with the reverse bias of VFD _sig1 applied to the n layer of the photodiode, the output signal V _r1 and the reset signal immediately after reset are Q _sig / C _FD By taking the difference from the superimposed output signal V _sig1 , the reset noise can be completely removed, and V _sig1 −V _r1 = Q _sig / C _FD × A (A is the gain of the output circuit for each pixel. ) Output signal can be obtained.

The output circuit noise ΔV _{n1 for} each pixel is superimposed on the output signal, and the output from the integrated circuit IC formed as a final area sensor has a readout system noise ΔV _n2 after the output circuit for each pixel. Superimposed.

In order to realize reading as described above, if a reverse bias is applied to the n layer of the photodiode and the voltage at which the entire n layer begins to be depleted is V _dep , it is necessary to _satisfy V _dep <V _sig1 . Here, the depletion voltage of a photodiode is broadly
It means a reverse bias voltage in which the number of accumulated charges in the accumulation unit <the number of net impurities. Ideally, the number of electrons remaining in the n-layer of the photodiode after reading is zero, but how completely read out is a matter of design. In practice, it is sufficient if it is sufficiently smaller than the noises ΔV _n1 and ΔV _n2 of the readout system described above.

  What is important here is that the transfer MOS transistor needs to be in a sufficiently ON state in order to realize the operation as described above, and the present invention provides a technique for this purpose between an embedded photodiode and a transfer MOS transistor. A bypass region 106 was provided. As shown in FIG. 2, the bypass region does not necessarily need to be in contact with the semiconductor surface. This is because the bypass region is interposed between the n-layer of the photodiode and the channel of the transfer MOS transistor, and of course, if it is a buried channel, the bypass region does not need to reach the surface. Even if there is a channel on the surface, it is best that the bypass region reaches the channel on the surface, but even if it does not, a transfer MOS transistor having a sufficiently lower threshold voltage than the prior art is obtained according to the above formula. be able to.

  Furthermore, the fact that this bypass region exists under the gate of the transfer MOS transistor is also an effective point, and when a gate voltage is applied, the potential under the gate is pushed up, but this effect is also added to the bypass, It becomes possible to lower the potential.

  The inventors of the present invention have found that the transfer MOS transistor is connected to the diffusion floating region and has the following effects.

  1) The impurity concentration of the diffusion floating region can be set high, and the depletion layer generated between the well and the diffusion floating region can be effectively spread to the p-type well side by the applied bias. This is because a voltage (reset voltage) at the time of reading can be input arbitrarily and directly.

  2) As with a CCD, a wide dynamic range that can be controlled by an external voltage can be secured against a small dynamic range that can be determined by the built-in potential of an impurity profile.

  3) By making the voltage at the time of reading appropriate, the potential barrier in the vicinity of the bypass region is moderately pushed down to facilitate reading.

In APS, since there are many transistors included in one pixel, in order to reduce the size of the pixel, the transistor itself must be miniaturized, which inevitably increases the well concentration of the photodiode and the transfer MOS transistor. In addition, with the miniaturization of transistors, it is necessary to reduce the power supply voltage. In order to reduce the depletion voltage V _dep while maintaining the amount of charge handled by the photodiode, it is necessary to increase the impurity concentration of the accumulation layer (n layer in FIG. 1) of the depletion photodiode and to reduce the thickness. Since the bypass region needs to be depleted similarly to the n-layer of the photodiode, the width of the bypass region also needs to be reduced.

  Furthermore, while the processing dimensional accuracy of the width of the n-layer and bypass region of the photodiode becomes severe, the well concentration increases, thereby increasing the processing variation factor, requiring further processing dimensional accuracy and leading to yield deterioration. In particular, the width of the bypass region is the accuracy in the surface direction of the silicon substrate, and generally the processing accuracy is lower than that in the depth direction, which is a major factor in yield deterioration. In the present invention, the allowable range of the width of the bypass region is widened and the yield is improved by the effect 3) described above.

  In the present invention, the processing method is as follows, thereby improving the processing accuracy of the width of the bypass region and improving the yield.

  The bypass region of the CCD, which is the prior art, is formed by the ion implantation of the n layer of the photodiode before the formation of the control electrode of the transfer MOS transistor and the ion implantation of the deep p layer of the surface using the control electrode of the transfer MOS transistor as a mask material. For this reason, the width of the bypass region varies greatly depending on the alignment accuracy of the exposure apparatus. The reason for this manufacturing method is that the operating voltage of the CCD is high and the depletion voltage of the n-layer of the photodiode is also high. Therefore, in general, the junction depth between the p-type well and the n-layer of the photodiode is Deep as 0.5 μm or more. Therefore, since the thickness of the control electrode is at most 0.5 μm, the control electrode cannot be ion-implanted into the mask material.

  In contrast, in the present invention, as shown in the third embodiment, for example, the bypass layer is formed by implanting ions obliquely using the n layer of the photodiode as a control electrode of the transfer MOS transistor, for example, polycrystalline silicon as a mask material. Thus, the width can be determined from the projection range of the ion implantation from the control electrode. Processing accuracy is high because the projection range of ion implantation is used. In addition, some examples will be shown in the following embodiments. Essentially, the bypass region is formed by using the control electrode of the transfer MOS transistor as a mask material and using ion implantation, thereby improving the processing accuracy. It is.

  In the above, the case where electrons are stored is taken as an example, and the features of the present invention are described. However, the present invention is limited to the case where holes are stored and the types of stored charges and transfer MOS transistors. Is not to be done.

  Example 1 will be described with reference to FIG. The photodiode of this embodiment and its periphery are formed by the following procedure.

Boron is introduced into the n-type substrate 901 using ion implantation, heat treatment is performed, a p-type well 902 having a surface concentration of about 2 × 10 ¹⁶ cm ⁻³ is formed, a photoresist 908 is formed, and the n-type substrate 901 is formed. A layer 904 was formed <FIG. 4A>.

  Further, a gate oxide film 910 having a thickness of 30 nm is formed on the entire substrate surface by a thermal oxidation method, and then a control electrode 903 of the transfer MOS transistor is formed (FIG. 4B).

  Next, a photoresist 909 is formed on the photodiode on the substrate surface and in some other region of the control electrode, and after heat treatment in a nitrogen atmosphere at 950 ° C./20 minutes, the control electrode 903 is used as a mask to form a deep surface. A p-layer 905 was formed (FIG. 4C).

  A diffusion floating region 907 made of arsenic was formed in accordance with a normal semiconductor manufacturing process <FIG. 4D>.

  In this step, a source / drain region of a normal MOS transistor was formed.

  Thereafter, in accordance with a normal semiconductor manufacturing process, a first interlayer insulating film, a contact, a first metal wiring, a second interlayer insulating film, a via connecting the first metal wiring and the second metal wiring, a second metal wiring, A passivation film was sequentially formed.

  As a result, a bypass region 906 of about 100 nm was formed. The threshold voltage of a normal MOS transistor composed of a thick n-type diffusion layer on both sides and the threshold voltage of the case where there is no bypass region of the transfer MOS transistor composed of a buried n layer of the source and the case of the present invention are evaluated. As a result, they were 0.7 volts, 2.2 volts, and 0.7 volts. As a result, it was confirmed that the threshold voltage was reduced to the level of a normal MOS transistor due to the bypass region. It can be seen that the dynamic range of the floating diffusion region has increased by at least 1.5 volts as the threshold voltage decreases.

  Example 2 will be described with reference to FIG. The photodiode of this embodiment and its periphery are formed by the following procedure.

Boron was introduced into the n-type substrate 601 using ion implantation, and heat treatment was performed to form a p-type well 602 having a surface concentration of about 4 × 10 ¹⁶ cm ⁻³ . After forming a gate oxide film with a thickness of 15 nm by thermal oxidation, polycrystalline silicon was deposited with a thickness of 400 nm to form a control electrode 603 of a transfer MOS transistor <FIG. 5A>.

  Thereafter, phosphorus was ion-implanted at 100 KeV using the photoresist 608 and the control electrode 603 as a mask material.

  At this time, the projected range and standard deviation of phosphorus were 120 nm and 45 nm, respectively, with respect to the film thickness of 400 nm of polycrystalline silicon, and the polycrystalline silicon functioned as a sufficient mask material (FIG. 5B).

Next, the photoresist 608 is removed, heat treatment is performed at 950 ° C. for 20 minutes in a nitrogen atmosphere, and phosphorus is slightly diffused. Then, a photoresist 609 is formed again, and BF ₂ is formed using the photoresist 609 and the control electrode 603 as a mask material. Ion implantation was performed at 35 KeV <FIG. 5 (c)>.

  A diffusion floating region 607 made of arsenic was formed in accordance with a normal semiconductor manufacturing process <FIG. 5D>. In this step, a source / drain region of a normal MOS transistor was formed.

  Thereafter, in accordance with a normal semiconductor manufacturing process, a first interlayer insulating film, a contact, a first metal wiring, a second interlayer insulating film, a via connecting the first metal wiring and the second metal wiring, a second metal wiring, A passivation film was sequentially formed.

  As a result, a bypass region 606 of about 100 nm was formed. The threshold voltage of a normal MOS transistor composed of a thick n-type diffusion layer on both sides, the threshold voltage when there is no bypass region of a transfer MOS transistor composed of a buried n layer of the source, and the threshold voltage when present (the present invention) And were evaluated to be 0.7, 3.5, and 0.7 volt, respectively. It was confirmed that the threshold voltage was reduced to the same level as a normal MOS transistor due to the bypass region.

  Example 3 will be described with reference to FIGS. 5 and 6. The photodiode of this embodiment and its periphery are formed by the following procedure.

In FIG. 5, boron was introduced into the n-type substrate 601 using ion implantation, and heat treatment was performed to form a p-type well 602 having a surface concentration of about 4 × 10 ¹⁶ cm ⁻³ . After forming a gate oxide film with a thickness of 15 nm by thermal oxidation, polycrystalline silicon was deposited with a thickness of 400 nm to form a control electrode 603 of a transfer MOS transistor <FIG. 5A>.

  Thereafter, ion implantation was performed at an angle of 100 KeV with phosphorus using the photoresist 1008 and the control electrode 1003 as a mask material. The ion implantation angle θ at this time was 20 °. In order to perform this oblique ion implantation, phosphorus extends under the control electrode 1003 even immediately after the ion implantation. At this time, the projected range and standard deviation of phosphorus were 120 nm and 45 nm, respectively, with respect to the thickness of 400 nm of polycrystalline silicon, and polycrystalline silicon functioned as a sufficient mask material <FIG. 6>.

A photoresist 609 was formed again, and ion implantation was performed with BF ₂ at 35 KeV using the photoresist 609 and the control electrode 603 as a mask material. The ion implantation angle θ at this time was set to 7 ° for suppressing channeling (FIG. 5C).

  A diffusion floating region 607 made of arsenic was formed in accordance with a normal semiconductor manufacturing process <FIG. 5D>.

  In this step, a source / drain region of a normal MOS transistor was formed.

  Thereafter, in accordance with a normal semiconductor manufacturing process, a first interlayer insulating film, a contact, a first metal wiring, a second interlayer insulating film, a via connecting the first metal wiring and the second metal wiring, a second metal wiring, A passivation film was sequentially formed.

  As a result, a bypass region 606 of about 100 nm was formed. A threshold voltage of a normal MOS transistor composed of a thick n-type diffusion layer on both sides, a threshold voltage when there is no bypass region of a transfer MOS transistor whose source is a buried n layer, and a threshold voltage when present (the present invention) Were evaluated to be 0.7, 3.5, and 0.7 volt, respectively. It was confirmed that the threshold voltage was reduced to the same level as a normal MOS transistor due to the bypass region.

  In order to form a bypass region by ion implantation of phosphorus obliquely, the heat treatment at 950 ° C. for 20 minutes in the nitrogen atmosphere for diffusing phosphorus in Example 2 was omitted. As a result, the heat treatment time of the semiconductor process can be shortened, and the peripheral MOS transistors used for signal processing and the like can be further miniaturized.

  As a fourth embodiment of the present invention, in the formation process in the third embodiment, the first ion implantation for providing a bypass region for the phosphorus ion implantation and the second ion implantation for providing the n layer of the photodiode are performed twice. I went to divide.

  In the first ion implantation, the ion implantation angle θ = 45 °, considering the profile of the p-layer with a deep surface at 80 KeV, and arranging the peak value near the surface and securing the bypass region, the ion implantation angle θ is It was larger than 20 °.

  The second ion implantation was performed at an ion implantation angle θ = 7 ° and 90 KeV in order to control the depletion voltage of the n-layer of the photodiode.

  By separating the ion implantation in the bypass region and the ion implantation in the n layer of the photodiode according to the above embodiment, the ion implantation angle, ion implantation energy, and ion implantation dose amount could be optimized according to the respective characteristics. .

  Example 5 will be described with reference to FIG. The photodiode of this embodiment and its periphery are formed by the following procedure.

Boron was introduced into the n-type substrate 1101 using ion implantation and heat treatment was performed to form a p-type well 1102 having a surface concentration of about 2 × 10 ¹⁶ cm ⁻³ , and an n-layer of a photodiode was formed. After forming a gate oxide film with a thickness of 30 nm by a thermal oxidation method, a control electrode of a transfer MOS transistor was formed. Thereafter, ion implantation was performed at 100 KeV using phosphorus 1100 and the control electrode 1103 as a mask material (FIG. 7A).

  After providing a low concentration n layer for LDD in the diffusion floating region, side spacers were formed with a width of 150 nm <FIG. 7B>.

A photoresist 1109 was formed, and ion implantation was performed at 35 KeV with BF ₂ using the photoresist 1109, the control electrode 1103, and the side spacer as a mask material. The ion implantation angle θ at this time is set to 7 ° for suppressing channeling (FIG. 7C).

  A diffusion floating region 1107 made of arsenic was formed in accordance with a normal semiconductor manufacturing process <FIG. 7 (d)>.

  In this step, a source / drain region of a normal MOS transistor was formed.

  Thereafter, in accordance with a normal semiconductor manufacturing process, a first interlayer insulating film, a contact, a first metal wiring, a second interlayer insulating film, a via connecting the first metal wiring and the second metal wiring, a second metal wiring, A passivation film was sequentially formed.

  As a result, a bypass region 1106 of about 150 nm was formed. The threshold voltage of a normal MOS transistor composed of a thick n-type diffusion layer on both sides, the threshold voltage when there is no bypass region of a transfer MOS transistor composed of a buried n layer of the source, and the threshold voltage when present (the present invention) And were evaluated to be 0.7, 3.5, and 0.7 volt, respectively. It was confirmed that the threshold voltage was reduced to the same level as a normal MOS transistor due to the bypass region. Here, the side spacer corresponds to the mask means.

  Of course, the mask means may form silicide, salicide, or the like instead of the side spacers.

  Example 6 will be described with reference to FIGS. 5, 6, and 8. The photodiode of this embodiment and its periphery are formed by the following procedure.

Boron was introduced into the n-type substrate 601 using ion implantation, and heat treatment was performed to form a p-type well 602 having a surface concentration of about 4 × 10 ¹⁶ cm ⁻³ . After forming a gate oxide film with a thickness of 15 nm by thermal oxidation, polycrystalline silicon was deposited with a thickness of 400 nm to form a control electrode 603 of a transfer MOS transistor <FIG. 5A>.

  Thereafter, ion implantation was performed at an angle of 100 KeV with phosphorus using the photoresist 1008 and the control electrode 1003 as a mask material. The ion implantation angle θ at this time was 10 °. In order to perform this oblique ion implantation, phosphorus extends under the control electrode even immediately after the ion implantation. At this time, the projected range and standard deviation of phosphorus were 120 nm and 45 nm, respectively, with respect to the thickness of 400 nm of polycrystalline silicon, and polycrystalline silicon functioned as a sufficient mask material <FIG. 6>.

A photoresist 1209 was formed again, and ion implantation was performed at 35 KeV with BF ₂ using the photoresist 1209 and the control electrode 1203 as a mask material. The ion implantation angle θ at this time was −15 ° <FIG. 8>.

  As a result, the control electrode 1203 was shaded, and the p-layer with a thick surface could be provided 400 * sin (15) = 100 nm away from the control electrode.

  A diffusion floating region 607 made of arsenic was formed in accordance with a normal semiconductor manufacturing process <FIG. 5D>. In this step, a source / drain region of a normal MOS transistor was formed.

  Thereafter, in accordance with a normal semiconductor manufacturing process, a first interlayer insulating film, a contact, a first metal wiring, a second interlayer insulating film, a via connecting the first metal wiring and the second metal wiring, a second metal wiring, A passivation film was sequentially formed.

  As a result, a bypass region 606 of about 150 nm was formed. The threshold voltage of a normal MOS transistor composed of a thick n-type diffusion layer on both sides, the threshold voltage when there is no bypass region of a transfer MOS transistor composed of a buried n layer of the source, and the threshold voltage when present (the present invention) And were evaluated to be 0.7, 3.5, and 0.7 volt, respectively. It was confirmed that the threshold voltage was reduced to the same level as a normal MOS transistor due to the bypass region.

  In order to form a bypass region by ion implantation of phosphorus obliquely, the heat treatment at 950 ° C. for 20 minutes in the nitrogen atmosphere for diffusing phosphorus in Example 2 was omitted. As a result, the heat treatment time of the semiconductor process can be shortened, and the peripheral MOS transistors used for signal processing and the like can be further miniaturized.

  Using the photodiode 705 and the transfer MOS transistor Q1 of Examples 1 to 6, an area sensor having the pixel configuration shown in FIG. 9 and the readout circuit shown in FIG. 10 was produced.

  In FIG. 9, a photodiode 705 and a transfer switch Q1 of a transfer MOS transistor are provided, Q2 is a reset switch of a reset MOS transistor for resetting the diffusion floating region, Q3 is connected to the gate of the diffusion floating region, and a load on the source side An input MOS transistor Q4 of a source follower amplifier circuit composed of a constant current source 812 connected as a reference switch Q4 is a selection switch for selecting a readout pixel.

  FIG. 10 shows a solid-state imaging device using pixel cells of photoelectric conversion elements composed of these in 3 rows and 3 columns.

The basic operation of FIGS. 9 and 10 will be described below.
1) A reset operation for inputting a reset voltage to the input gate of the source follower by the reset switch Q2 and a row selection by the selection switch Q4 are performed.
2) Floating the gate of the floating diffusion region at the input node of the source follower, reading out noise components including fixed pattern noise such as reset noise and variation in threshold voltage of the source follower MOS, and sending the information to the signal storage unit 805 Hold once.
3) Thereafter, the transfer switch Q1 is opened and closed, the accumulated charge of the photodiode generated by the optical signal is transferred to the input node of the source follower, the sum of the noise component and the optical signal component is read out, and held in the signal storage unit 805 4) The common signal lines 809 and 809 ′ are connected to the common signal line 1 via the transfer switches 808 and 808 ′ to the common signal line, respectively. (808), the transfer switch of the common signal line 2 (808 ') is turned on, read out, and output as outputs 811 and 811' via the respective output amplifiers 810.

  Thereafter, by taking the difference between the outputs 811 and 811 ′, the reset noise and the fixed pattern noise are removed, the optical signal component is extracted, and an image signal having a high S / N can be obtained.

Reading was performed by the above method, and signal and noise were evaluated. As a result, a high S / N of dynamic range (S / N) = 75 to 85 dB for each bit was obtained. In addition, as a result of evaluating the S / N variation in each example, the size of the variation is as follows,
Example 3, Example 4 <Example 2, Example 5, Example 6 << Example 1
As a result, it is shown that a low-temperature and self-aligned formation method using a control electrode is more effective.

  The present invention is applied to a solid-state imaging device having a signal amplification unit for each pixel.

1 is a cross-sectional structure diagram that best represents the features of the present invention. FIG. 2 is a planar potential diagram of FIG. 1. It is a cross-sectional potential diagram of FIG. FIG. 3 is a cross-sectional structure diagram illustrating a manufacturing process of Example 1. It is sectional structure drawing which showed the manufacturing process of this invention. 6 is a cross-sectional structure diagram showing a manufacturing process of Example 3. FIG. 10 is a cross-sectional structure diagram showing a manufacturing process of Example 5. FIG. 10 is a cross-sectional structure diagram showing a manufacturing process of Example 6. FIG. It is an equivalent circuit diagram of a pixel using the present invention. It is an equivalent circuit diagram including the readout circuit of the area sensor using the present invention. It is sectional drawing of a prior art. It is a cross-sectional structure diagram when a bypass region is provided in a CCD.

Explanation of symbols

101, 501, 601, 901, 1001, 1101 Semiconductor substrate 102, 502, 602, 902, 1002, 1102 Well 103, 603, 903, 1003, 1103 Control electrodes 104, 504, 604, 904, 1004 of the transfer MOS transistor 1104 Photodiode n-layer 105, 505, 605, 905, 1105 Dark p-layer 106, 606, 906, 1106 on the surface of the photodiode Bypass region 107, 607, 907, 1107 Diffusion floating region 108 Reset MOS transistor 109 Reset electrode 110 Output circuit (Source follower) input MOS transistor 111 Select switch MOS transistor 112 Source follower constant current load 113 Output terminal 301 Oxide film 302 Photo diode n Fermi level 303 bypass region Fermi level potential when a voltage is applied potential 305 threshold voltage when a voltage is applied in 304 threshold voltage 608,609,908,909,1008 photoresist of

Claims (2)

A second semiconductor region of the second conductivity type in the first semiconductor region of the first conductivity type, and a third semiconductor of the first conductivity type provided in contact with the light incident side of the second semiconductor region A photoelectric conversion unit having a region;
A fourth semiconductor region of the second conductivity type in the first semiconductor region;
A first semiconductor region between the photoelectric conversion unit and the fourth semiconductor region for transferring the signal charge accumulated in the photoelectric conversion unit to the fourth semiconductor region, the first semiconductor region A charge transfer unit having an upper insulating film and a control electrode on the insulating film;
In a solid-state imaging device having at least
The second semiconductor region is provided to extend under the control electrode;
The solid-state imaging device, wherein the fourth semiconductor region has an LDD structure. The second semiconductor region is provided so as to be disposed between an end portion of the third semiconductor region on the charge transfer portion side and the first semiconductor region of the charge transfer portion. The solid-state imaging device according to claim 1.