KR100835526B1 - Method for manufacturing a cmos image semsor - Google Patents

Abstract

A method for manufacturing a CMOS image sensor is provided to prevent a dark current by using FSG(Fluorine doped Silicate Glass) so that fluorine ions contained in the FSG can be distributed to a silicon boundary to fill electron trap sites. A gate electrode(104) is formed by inserting a gate insulating layer on a semiconductor substrate(100). A photodiode region(106) is formed in the surface of the semiconductor substrate of the one side of the gate electrode, and an LDD region is formed at the other side. Sidewalls of an insulating layer are formed at both sides of the gate electrode. A source/drain dopant region(111) is formed in the surface of the substrate of the other side of the gate electrode. An FSG(112) is formed from the one side of the gate electrode to the photodiode region. A metal silicide layer is formed from the other side of the gate electrode to the source/drain dopant region.

Description

Manufacturing method of CMOS image sensor {METHOD FOR MANUFACTURING A CMOS IMAGE SEMSOR}

1 is a layout diagram showing unit pixels of a general 3T CMOS image sensor.

FIG. 2 is a cross-sectional view of a CMOS image sensor according to the related art according to line AA ′ of FIG. 1.

3A to 3F are cross-sectional views illustrating a method of manufacturing the CMOS image sensor according to the present invention.

The present invention relates to a method for manufacturing a CMOS image sensor to reduce the dark current to improve the characteristics of the image sensor.

In general, an image sensor is a semiconductor device that converts an optical image into an electrical signal, and a dual charge-coupled device (CCD) is a device in which each metal-oxide-silicon (MOS) capacitor is connected to each other. It is a device in which the charge carrier is stored in the capacitor and transported in a very close position.

CMOS image sensors use CMOS technology, which uses control circuits and signal processing circuits as peripheral circuits, to create as many pixel transistors as transistors, and to sequentially detect the output. It is an element that adopts a switching method.

CCD (charged coupled device) has a complicated driving method, high power consumption, and a large number of mask process steps, which makes the process complicated and the signal processing circuit cannot be implemented in the CCD chip, which makes it difficult to realize one chip. In recent years, the development of CMOS image sensors using sub-micron CMOS manufacturing techniques has been studied in order to overcome such disadvantages.

The CMOS image sensor forms a photodiode and a MOS transistor in a unit pixel to detect an image in turn using a switching method to implement an image, and the CMOS fabrication technology is used to reduce power consumption and reduce mask power by 20 to 30. Compared to the CCD process, which requires 40 masks, the process is much simpler, enabling multiple signal processing circuits and one-chip chips, which are attracting attention with next-generation image sensors, and are used in many applications such as digital cameras, digital cameras, and mobile cameras. It is used.

On the other hand, CMOS image sensors are classified into 3T type, 4T type, and 5T type according to the number of transistors. The 3T type consists of one photodiode and three transistors, and the 4T type consists of one photodiode and four transistors. The layout of the unit pixels of the 3T type CMOS image sensor is as follows.

1 is a layout diagram illustrating unit pixels of a general 3T CMOS image sensor.

1 is a unit pixel layout diagram of a conventional 3-T structure CMOS image sensor.

As shown in the figure, the unit pixel of the 3-T CMOS image sensor is composed of one photodiode PD and three transistors.

The three transistors include a reset gate (Rx) for resetting photocharges collected in the photodiode (PD), a drive gate (Dx) and switching (Switching) serving as a source follow buffer amplifier (Source Follow Buffer Amplifier). It consists of a select gate (Sx) that allows addressing () in the role.

Here, a salicide is not formed in the photodiode region 10 including the photodiode PD, and a salicide is formed in a region other than the photodiode region 10, that is, a logic region. It is an area.

The reason for forming the salicide in the logic region is to reduce the resistance to improve the speed of the transistors (Rx, Dx, Sx), and the reason for not forming the salicide in the photodiode region 10 is the photodiode (PD). ), You need to play the image from the light source, because salicide reflects the light.

FIG. 2 is a cross-sectional view of the CMOS image sensor according to the prior art along the AA ′ direction of FIG. 1, showing a photodiode PD and a reset gate Rx.

As shown in FIG. 2, a reset gate 3 is formed on the semiconductor layer 1 on which a high concentration P ++ semiconductor substrate and a P-Epi layer are stacked via a gate insulating film 2. (3) A photodiode impurity region (hereinafter referred to as PDN) 4 is formed in one side of the photodiode region 10.

An N + diffusion region 5 is formed in the other semiconductor layer 1 of the reset gate 3, an insulating film sidewall 6 is formed on both sides of the reset gate 3, and the N + diffusion region ( The LDD region 7 is formed in the semiconductor layer 1 under the insulating film sidewall 6 formed on the side 5.

As described above, the salicide film 8 should not be formed in the photodiode region 10, but only in a logic region that is a region other than the photodiode region, so that the reset gate included in the photodiode region 10 is formed. The salicide film 8 is not formed in (3), and the salicide film 8 is formed in the reset gate 3 and the N + diffusion region 5 included in the logic region. Unexplained reference numeral 9 is an element isolation film.

However, the CMOS image sensor according to the related art has the following problems.

That is, there is a limit in controlling the dark current when performing the heat treatment process by using a TEOS film used to prevent salicide in the photodiode region in order to control the dark current.

The present invention provides a method for manufacturing a CMOS image sensor that prevents dark current by preventing electron traps from occurring by diffusing fluorine to a silicon interface by a heat treatment process to fill an electron trap site. Its purpose is to.

A method of manufacturing a CMOS image sensor according to the present invention includes forming a gate electrode on a semiconductor substrate through a gate insulating film; Forming a photodiode region in a surface of the semiconductor substrate on one side of the gate electrode; Forming sidewalls of an insulating film on both sides of the gate electrode; Forming a source / drain impurity region in a surface of the semiconductor substrate on the other side of the gate electrode; Forming an FSG on the photodiode region of the semiconductor substrate; Forming a metal film on an entire surface of the semiconductor substrate including the FSG; Performing a heat treatment process on the semiconductor substrate to form a metal silicide layer on the gate electrode and the source / drain impurity region; And removing the metal film that has not reacted with the gate electrode and the source / drain impurity region.

Hereinafter, a method of manufacturing the CMOS image sensor according to the present invention will be described in detail with reference to the accompanying drawings.

3A to 3F are cross-sectional views illustrating a method of manufacturing the CMOS image sensor according to the present invention.

As shown in FIG. 3A, a low concentration first conductivity type (P ⁻ type) epi layer 101 is applied to a semiconductor substrate 100 such as a high concentration first conductivity type (P ⁺⁺ type) polycrystalline silicon by an epitaxial process. ).

In this case, the epitaxial layer 101 is formed to form a depletion region large and deep in the photodiode to increase the ability of the low voltage photodiode to collect the photocharge and further improve the light sensitivity.

Next, an active region and an isolation region of the semiconductor substrate 100 are defined, and an isolation layer 102 is formed in the isolation region using an STI process or a LOCOS process.

The gate insulating layer 103 and the conductive layer are sequentially deposited on the entire epitaxial layer 101 on which the device isolation layer 102 is formed, and the conductive layer and the gate insulating layer are selectively removed to remove the gate electrode 104 of each transistor. Form.

Subsequently, the first photoresist film 105 is coated on the entire surface of the semiconductor substrate 100 including the gate electrode 104, and the patterned first photoresist film 105 is selectively patterned so that the photodiode region is exposed through an exposure and development process. do.

The PDN region 106 is formed by implanting low concentration n ⁻ -type impurity ions into the exposed photodiode region using the patterned first photoresist layer 105 as a mask.

As shown in FIG. 3B, after removing all of the first photoresist layer 105, the second photoresist layer 107 is coated on the entire surface of the semiconductor substrate 100, and the transistor region is exposed through an exposure and development process. The second photosensitive film 107 is patterned.

Subsequently, the LDD region 108 is formed by implanting low concentration n ⁻ -type impurity ions into the epi layer 101 using the patterned second photoresist layer 107 as a mask.

Here, impurity ion implantation for forming the PDN region 106 is formed deeper by ion implantation with higher energy than the LDD region 108.

As shown in FIG. 3C, all of the second photoresist film 107 is removed, and an insulating film is formed over the entire surface of the semiconductor substrate 100.

Next, an etch back process is performed on the entire surface of the insulating film to form nitride film sidewalls 109 on both sides of the gate electrode 104.

As shown in FIG. 3D, the third photoresist layer 110 is coated on the entire surface of the semiconductor substrate 100, and is selectively patterned so as to remain only on the photodiode region and the device isolation layer 102 by exposure and development processes.

Next, using the patterned third photoresist layer 110 as a mask, high concentration n ⁺ type impurity ions are implanted into the exposed source / drain impurity regions to form a high concentration n ⁺ type diffusion region 111 (hereinafter referred to as “source / drain”). Impurity region ".

As shown in FIG. 3E, after the third photosensitive film 110 is removed, a heat treatment process (for example, a rapid heat treatment process of 800 ° C. or higher) is performed to form the n ⁻ type diffusion region 106 and a low concentration n ⁻ type. Impurity ions in the diffusion region 108 and the source / drain impurity region 111 are diffused.

Subsequently, an FSG 112 is formed on the entire surface of the semiconductor substrate 100, the fourth photoresist layer 113 is coated on the FSG 112, and then the fourth photoresist layer 113 is exposed through an exposure and development process. It is selectively patterned to define the region where the silicide film is to be formed.
The region in which the silicide layer is to be formed becomes a region from the source / drain impurity region 111 to the other side portion of the gate electrode 104.

Subsequently, the exposed FSG 112 is selectively removed using the patterned fourth photoresist layer 113 as a mask to expose the surface of the source / drain impurity region 111 from the other side of the gate electrode 104. Let's do it.
Accordingly, the FSG 112 extends from one side portion of the gate electrode 104 to the photodiode region 106 (PDN region).
As shown in FIG. 3F, the fourth photoresist film 113 is removed, a metal film is deposited on the entire surface of the semiconductor substrate 100, and a heat treatment process is performed to remove the fourth photoresist film 113 from the other side of the gate electrode 104. The metal film is silicided on the surface of the source / drain impurity region 111.
In other words, the semiconductor substrate is subjected to a heat treatment process to suicide the metal film in the region where the FSG 112 is not formed.

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In this case, the metal film may be formed of a material to be silicided by reacting with the semiconductor substrate 100, for example, any one of Ti, Ta, Ni, and Co.

Subsequently, the metal film that does not react with the semiconductor substrate 100, that is, the non-silicided metal film on the FSG 112 is removed to remove the source / drain impurity region 111 from the other side of the gate electrode 104. To form the metal silicide layer.

On the other hand, the present invention described above is not limited to the above-described embodiment and the accompanying drawings, it is possible that various substitutions, modifications and changes within the scope without departing from the technical spirit of the present invention. It will be apparent to those of ordinary skill in Esau.

As described above, the method for manufacturing the CMOS image sensor according to the present invention has the following effects.

That is, by using FSG to prevent salicide in the photodiode region to control the dark current, which is a problem for the CMOS image sensor, the fluorine ions contained in the FSG are diffused to the silicon interface by the heat treatment process, and the electron trap site Can no longer be an electronic trap, preventing dark current to stabilize the image sensor.

Claims (3)

Forming a gate electrode on the semiconductor substrate via the gate insulating film; Forming a photodiode region in a surface of the semiconductor substrate on one side of the gate electrode and forming an LDD region in the surface of the semiconductor substrate on the other side of the gate electrode; Forming sidewalls of an insulating film on both sides of the gate electrode; Forming a source / drain impurity region in a surface of the semiconductor substrate on the other side of the gate electrode; Forming an FSG from one side of the gate electrode to the photodiode region; And Forming a metal silicide film from the other side of the gate electrode to the source / drain impurity region. The method of claim 1, The metal silicide film is a method of manufacturing a CMOS image sensor, characterized in that formed using any one of Ti, Ta, Ni, Co. The method of claim 1, wherein the forming of the metal silicide layer Forming a metal film on an entire surface of the semiconductor substrate including the FSG; Performing a heat treatment process on the semiconductor substrate to silicide a metal film in a region where the FSG is not formed; And Removing the unsilicided metal film on the FSG to form the metal silicide film from the other side of the gate electrode to the source / drain impurity region.

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