CN102832112A - Method for forming metal silicide - Google Patents
Method for forming metal silicide Download PDFInfo
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- CN102832112A CN102832112A CN2011101650037A CN201110165003A CN102832112A CN 102832112 A CN102832112 A CN 102832112A CN 2011101650037 A CN2011101650037 A CN 2011101650037A CN 201110165003 A CN201110165003 A CN 201110165003A CN 102832112 A CN102832112 A CN 102832112A
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- metal silicide
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Abstract
The invention provides a method for forming metal silicide. Before a metal silicide block layer is formed, a layer of silicofluoride glass film is deposited on a silicon substrate to be as a buffer layer. Fluorine element in the silicofluoride glass film can spread into the silicon substrate. Introduction of the fluorine element can restrain the metal from suddenly entering the silicon substrate together in an initial stage when the metal silicide is formed, and can fix the metal element which has already spread into the silicon substrate, thereby reducing defects.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, relate in particular to a kind of formation method of metal silicide.
Background technology
Along with developing rapidly of very lagre scale integrated circuit (VLSIC), the integrated level of device is increasingly high, and size is more and more littler.When device dimensions shrink to time micron dimension; Can produce many problems accordingly; Like metal oxide semiconductor field-effect (MOS) transistor; Owing to reduce size, can cause the gate electrode of MOS transistor and the sheet resistance and the contact resistance of source/drain regions to increase, make MOS transistor signal delay occur.
Reduce the problem that device size brings in order to solve; The general metal silicide technology that adopts; Go up deposition refractory metal titanium (Ti), cobalt (Co), nickel (Ni) etc. at the active area (surface is the zone of silicon materials) in the most of zone of device; Form metal silicide through annealing process, but also have the active area of subregion can not form metal silicide, like zones such as high resistance polysilicon district, isolation active areas.Therefore; Before making metal silicide; Need to form in the zone that can not form metal silicide earlier metal silicide barrier structure (salicide block layer; SAB), the characteristic of utilizing the metal silicide barrier structure can not react with metal is to prevent forming metal silicide in the zone that can not form metal silicide.
The method that the common metal silicide forms is as shown in Figure 1; Comprise the steps: on silicon substrate, to form earlier blocking layer of metal silicide; On blocking layer of metal silicide, form the patterning photoresist corresponding with the presumptive area of the required generation silicide of silicon substrate; Utilize the patterning photoresist to carry out etching as mask; Expose the silicon substrate predetermined portions that need to generate metal silicide, deposition layer of metal layer carries out annealing first time on this substrat structure then, and etching is carried out annealing in process one time after removing not the metal that reacts with silicon substrate again.
In the forming process of metal silicide, be also noted that the influence of silicon surface oxidation layer, if having oxide layer at silicon face, can make that the formation of metal silicide is second-rate, cause device resistance to raise, leakage current strengthens.Yet in the manufacture process of chip, silicon chip inevitably can be exposed in the air, forms natural oxidizing layer (native oxide).The general method of removing the influence of silicon surface oxidation layer mainly comprises two kinds, and a kind of is before generating metal silicide, to utilize hydrofluoric acid (HF) to soak to remove silica, and a kind of is to utilize nitrogen fluoride and ammonia (NF
3/ NH
3) carry out the oxide layer that plasma etching is removed silicon face.Two kinds of methods all can be diffused into fluorine element in the silicon substrate.The introducing of fluorine element can be suppressed at generate metal silicide during the initial stage metal concentrate suddenly and get in the silicon substrate, and can fix the metallic element that has been diffused in the silicon substrate, and then reduce defective.Generating nickle silicide (NiSi) with refractory metal Ni is example, and Ni and Si can generate three kinds of silicides, i.e. nickle silicide (NiSi), nickel disilicide (NiSi
2) and a silication two nickel (Ni
2Si), NiSi
2Resistive increased the consumption of silicon, Ni the most by force and accordingly
2Si is unstable, and its shape is wayward, and the resistivity of NiSi is relatively low, and its to form temperature required be about 350 degrees centigrade, its heat loss is also relatively low, so NiSi is preferred metal silicide.The introducing of fluorine element can suppress to generate NiSi and diffuse into the Ni that the silicon substrate generation is not expected during the initial stage in a large amount of Ni element sets
2Si, in addition, fluorine element can also improve NiSi
2The nucleus formation temperature time, reduce the surface roughness between NiSi and the silicon substrate.
Summary of the invention
The technical problem that the present invention will solve is in order further to improve the content of fluorine element in the silicon substrate, to the invention provides a kind of metal silicide formation method.
Technical scheme of the present invention is following: a kind of metal silicide formation method comprises: deposition one deck fluorine silex glass film is as resilient coating on silicon substrate;
Plated metal silicide barrier layer on resilient coating;
On blocking layer of metal silicide, form the patterning photoresist corresponding with the presumptive area of the required generation silicide of silicon substrate;
Carry out etching through said patterning photoresist as mask, exposing needs on the silicon substrate to generate the presumptive area of metal silicide and remove photoresist;
Deposition layer of metal layer on the silicon substrate structure after the etching, and carry out the annealing in process first time;
Carry out the annealing in process second time after removing not the metal with the silicon substrate reaction through etching.
Further, said method also is included in and generates behind the fluorine silex glass film resilient coating the silicon substrate structure step of heat treatment; Said heat treated temperature is preferably 200-500 degree centigrade.
Further, said method also is included on the silicon substrate and utilizes hydrofluoric acid dips or carry out the step that plasma etching is removed the oxide layer of silicon face through nitrogen fluoride and ammonia before the deposition fluorine silex glass film.
Further, on silicon substrate, deposit one deck fluorine silex glass film resilient coating through PCVD; The optimal process parameter of PCVD is:
The silicon tetrafluoride flow is a 200-2000 mark condition milliliter per minute;
The silicon tetrahydride flow is a 200-2000 mark condition milliliter per minute;
The nitrous oxide flow is a 2000-30000 mark condition milliliter per minute;
Power is 500-2000 watt;
Temperature is 250-600 degree centigrade;
The thickness of fluorine silex glass film resilient coating is the 50-150 dust.
Further, said blocking layer of metal silicide is a silicon nitride; Said metal level is the nickel platinum alloy.
Further, the atomic ratio of platinum is preferably 5-15% in the said nickel platinum alloy, and the thickness of nickel platinum alloy layer is preferably the 50-200 dust.
Further, the thickness of said silicon nitride barrier is preferably the 150-350 dust.
Further, said first time annealing in process temperature less than the temperature of the annealing in process second time.
Description of drawings
Fig. 1 forms method flow diagram for existing metal silicide;
Fig. 2 forms method flow diagram for metal silicide of the present invention;
Fig. 3 a-3d is the semiconductor structure schematic cross-section of a kind of embodiment of metal silicide formation method of the present invention.
Embodiment
Below in conjunction with accompanying drawing principle of the present invention and characteristic are described, institute gives an actual example and only is used to explain the present invention, is not to be used to limit scope of the present invention.
Fig. 2 is the flow chart of a kind of metal silicide of the present invention formation method, and as shown in Figure 2, the key step of this method comprises:
Deposition one deck fluorine silex glass film is as resilient coating on silicon substrate;
Plated metal silicide barrier layer on fluorine silex glass film resilient coating;
On blocking layer of metal silicide, form the patterning photoresist corresponding with the presumptive area of the required generation silicide of silicon substrate;
Carry out etching through said patterning photoresist as mask, exposing needs on the silicon substrate to generate the presumptive area of metal silicide and remove photoresist;
Deposition layer of metal layer on the silicon substrate structure after the etching, and carry out the annealing in process first time;
Carry out the annealing in process second time after removing not the metal with the silicon substrate reaction through etching.
Existing is example on silicon substrate, to generate nickel silicon, describes the inventive method process in detail.
Shown in Fig. 3 a, at first, through PCVD one deck fluorine silex glass film resilient coating 2, the optimal process parameter of PCVD is: silicon tetrafluoride (SiF on silicon substrate 1
4) flow is 200-2000 mark condition milliliter per minute (sccm); Silicon tetrahydride (SiH
4) flow is 200-2000sccm; Nitric oxide (N
2O) flow is 2000-30000sccm; Power is 500-2000 watt; Temperature is 250-600 degree centigrade; The thickness of fluorine silex glass film resilient coating 2 is preferably the 50-150 dust.The deposition layer of sin is as blocking layer of metal silicide 3 on fluorine silex glass film resilient coating 2, and the thickness of SiN layer is preferably the 150-350 dust.Fluorine element in the fluorine silex glass film resilient coating 2 can be through diffusing into silicon substrate 1, shown in Fig. 3 b.Because temperature can be so that the quickening of the fluorine element diffusion velocity in the fluorine silex glass film resilient coating 2 greatly about 250-600 degree centigrade when carrying out PCVD; Preferably, in deposition fluorine silex glass film resilient coating 2 backs substrat structure is heat-treated, improve the diffusion of fluorine element in substrate 1, heat treated temperature is preferably 200-500 degree centigrade.
Then; Shown in Fig. 3 c, on the SiN layer, form the patterning photoresist 4 corresponding, and to pass through patterning photoresist 4 be the mask etching silicon substrate structure with the presumptive area of the required generation silicide of silicon substrate; To expose the presumptive area that needs to generate SiNi on the silicon substrate, remove photoresist 4 then.
Shown in Fig. 3 d, deposition one deck nickel platinum alloy layer 5 on silicon substrate structure, the atomic ratio of platinum is preferably 5-15% in the nickel platinum alloy, and thickness is preferably the 50-200 dust; Then silicon substrate structure is carried out the annealing in process first time, the nickel of layer in 5 can fully be reacted with silicon generate SiNi, be diffused into the fluorine element in the silicon substrate, can suppress to generate NiSi and diffuse into silicon substrate during the initial stage in a large amount of Ni element sets and produce the Ni that does not expect
2Si, and fixing be diffused into the nickel in the silicon substrate, and then reduce defective, can also improve NiSi
2The nucleus formation temperature time, reduce the surface roughness between NiSi and the silicon substrate.Optional, before the annealed substrate structure, can on nickel platinum alloy layer 5, deposit the oxidation of one deck titanium nitride (TiN) with the nickel that reduces in annealing process, to cause.Remove the nickel platinum alloy layer that does not react through etching at last; And pass through annealing in process for the second time once more, formation has the silicon substrate structure of SiNi, wherein; The temperature of annealing in process is less than the temperature of the annealing in process second time for the first time; The main effect of annealing for the first time is diffusion, and temperature is low relatively, forms Ni
2Si, annealing temperature is higher relatively for the second time, makes Ni
2Si is converted into more stable NiSi.
Need not form in the silicon substrate structure of SiNi, though introduced fluorine silex glass film, it to substrat structure, and does not have substantial influence to the semiconductor device that on substrat structure, forms as resilient coating.
The above is merely preferred embodiment of the present invention, and is in order to restriction the present invention, not all within spirit of the present invention and principle, any modification of being made, is equal to replacement, improvement etc., all should be included within the scope that the present invention protects.
Claims (10)
1. metal silicide formation method comprises:
Deposition one deck fluorine silex glass film is as resilient coating on silicon substrate;
Plated metal silicide barrier layer on resilient coating;
On blocking layer of metal silicide, form the patterning photoresist corresponding with the presumptive area of the required generation silicide of silicon substrate;
Carry out etching through said patterning photoresist as mask, exposing needs on the silicon substrate to generate the presumptive area of metal silicide and remove photoresist;
Deposition layer of metal layer on the silicon substrate structure after the etching, and carry out the annealing in process first time;
Carry out the annealing in process second time after removing not the metal with the silicon substrate reaction through etching.
2. method according to claim 1 is characterized in that, after generating fluorine silex glass film resilient coating to the silicon substrate structure step of heat treatment.
3. method according to claim 2 is characterized in that, said heat treated temperature is 200-500 degree centigrade.
4. method according to claim 1 is characterized in that, on silicon substrate, utilizes hydrofluoric acid dips or carries out the step that plasma etching is removed the oxide layer of silicon face through nitrogen fluoride and ammonia before the deposition fluorine silex glass film.
5. according to each described method of claim 1-4, it is characterized in that, on silicon substrate, deposit one deck fluorine silex glass film through PCVD.
6. method according to claim 5 is characterized in that, the technological parameter of said PCVD is:
The silicon tetrafluoride flow is a 200-2000 mark condition milliliter per minute;
The silicon tetrahydride flow is a 200-2000 mark condition milliliter per minute;
The nitrous oxide flow is a 2000-30000 mark condition milliliter per minute;
Power is 500-2000 watt;
Temperature is 250-600 degree centigrade;
The thickness of fluorine silex glass film resilient coating is the 50-150 dust.
7. method according to claim 5 is characterized in that, said blocking layer of metal silicide is a silicon nitride; Said metal level is the nickel platinum alloy.
8. method according to claim 7 is characterized in that, the atomic ratio of platinum is 5-15% in the said nickel platinum alloy, and the thickness of nickel platinum alloy layer is the 50-200 dust.
9. method according to claim 5 is characterized in that, the thickness of said silicon nitride barrier is the 150-350 dust.
10. method according to claim 1 is characterized in that, said first time annealing in process temperature less than the temperature of the annealing in process second time.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011101650037A CN102832112A (en) | 2011-06-17 | 2011-06-17 | Method for forming metal silicide |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011101650037A CN102832112A (en) | 2011-06-17 | 2011-06-17 | Method for forming metal silicide |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104465351A (en) * | 2014-11-28 | 2015-03-25 | 上海华力微电子有限公司 | Method for improving metal silicide |
| CN104505342A (en) * | 2014-11-28 | 2015-04-08 | 上海华力微电子有限公司 | Method for improving metal silicides |
| CN110310900A (en) * | 2019-07-22 | 2019-10-08 | 上海华力集成电路制造有限公司 | Nickel metal silicide generates monitoring method |
| CN112462145A (en) * | 2020-11-24 | 2021-03-09 | 上海华力集成电路制造有限公司 | Detection method of nickel silicide heat treatment process |
| WO2022068331A1 (en) * | 2020-09-29 | 2022-04-07 | 长鑫存储技术有限公司 | Method for forming film layer |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6468901B1 (en) * | 2001-05-02 | 2002-10-22 | Sharp Laboratories Of America, Inc. | Nickel silicide including iridium for use in ultra-shallow junctions with high thermal stability and method of manufacturing the same |
| CN101009236A (en) * | 2006-01-24 | 2007-08-01 | 中芯国际集成电路制造(上海)有限公司 | A method for making CDSEM calibration sample |
| KR100835526B1 (en) * | 2006-12-27 | 2008-06-04 | 동부일렉트로닉스 주식회사 | Method for manufacturing a cmos image semsor |
| CN101452963A (en) * | 2007-12-05 | 2009-06-10 | 中国科学院微电子研究所 | Metallic nanocrystalline floating gate non-volatile memory and manufacturing method thereof |
-
2011
- 2011-06-17 CN CN2011101650037A patent/CN102832112A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6468901B1 (en) * | 2001-05-02 | 2002-10-22 | Sharp Laboratories Of America, Inc. | Nickel silicide including iridium for use in ultra-shallow junctions with high thermal stability and method of manufacturing the same |
| CN101009236A (en) * | 2006-01-24 | 2007-08-01 | 中芯国际集成电路制造(上海)有限公司 | A method for making CDSEM calibration sample |
| KR100835526B1 (en) * | 2006-12-27 | 2008-06-04 | 동부일렉트로닉스 주식회사 | Method for manufacturing a cmos image semsor |
| CN101452963A (en) * | 2007-12-05 | 2009-06-10 | 中国科学院微电子研究所 | Metallic nanocrystalline floating gate non-volatile memory and manufacturing method thereof |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104465351A (en) * | 2014-11-28 | 2015-03-25 | 上海华力微电子有限公司 | Method for improving metal silicide |
| CN104505342A (en) * | 2014-11-28 | 2015-04-08 | 上海华力微电子有限公司 | Method for improving metal silicides |
| CN104505342B (en) * | 2014-11-28 | 2017-12-05 | 上海华力微电子有限公司 | A kind of method for improving metal silicide |
| CN110310900A (en) * | 2019-07-22 | 2019-10-08 | 上海华力集成电路制造有限公司 | Nickel metal silicide generates monitoring method |
| CN110310900B (en) * | 2019-07-22 | 2021-12-07 | 上海华力集成电路制造有限公司 | Nickel metal silicide generation monitoring method |
| WO2022068331A1 (en) * | 2020-09-29 | 2022-04-07 | 长鑫存储技术有限公司 | Method for forming film layer |
| CN112462145A (en) * | 2020-11-24 | 2021-03-09 | 上海华力集成电路制造有限公司 | Detection method of nickel silicide heat treatment process |
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Application publication date: 20121219 |