CN102468173A - Method for making transistor - Google Patents
Method for making transistor Download PDFInfo
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- CN102468173A CN102468173A CN2010105481137A CN201010548113A CN102468173A CN 102468173 A CN102468173 A CN 102468173A CN 2010105481137 A CN2010105481137 A CN 2010105481137A CN 201010548113 A CN201010548113 A CN 201010548113A CN 102468173 A CN102468173 A CN 102468173A
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- semiconductor substrate
- oxide layer
- grid structure
- side wall
- manufacture method
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Abstract
The invention proposes a method for making a transistor. The method comprises the following steps of: providing a semiconductor substrate, wherein a grid structure is formed on the semiconductor substrate; forming oxide layers on the surface of the semiconductor substrate and the lateral wall and the top of the grid structure, wherein the oxide layers are made by using a deposition process; forming side wall dielectric layers on the oxide layers; removing the side wall dielectric layer and the oxide layer which are positioned on the semiconductor substrate, and retaining the side wall dielectric layers and the oxide layers which are positioned on the later wall and the top of the grid structure, wherein the side wall dielectric layers and the oxide layers form a side wall structure; and performing ion implantation by taking the grid structure and the side wall structure as masks, and forming a source region and a drain region in the semiconductor substrate at the two sides of the grid structure and the side wall structure. With the adoption of the method, the problem of current leakage of the transistor is solved.
Description
Technical field
The present invention relates to technical field of semiconductors, particularly a kind of transistorized manufacture method.
Background technology
Metal-oxide-semicondutor (MOS) transistor is the most basic device during semiconductor is made, and they are in various integrated circuits, and the doping type during according to main charge carrier and manufacturing is different, is divided into NMOS and PMOS transistor.
Prior art provides a kind of manufacture method of MOS transistor.Please refer to the manufacture method cross-sectional view of Fig. 1 to the MOS transistor of prior art shown in Figure 4.
Please refer to Fig. 1, Semiconductor substrate 100 is provided, in said Semiconductor substrate 100, form isolation structure 101, the Semiconductor substrate 100 between the said isolation structure 101 is an active area.
Then, on the Semiconductor substrate 100 between the said isolation structure 101, form grid oxic horizon 102 and grid 103, said grid oxic horizon 102 constitutes grid structure with grid 103.Said grid oxic horizon 102, it utilizes thermal oxidation technology to make.
Then, please refer to Fig. 2, form the oxide layer 104 that covers said Semiconductor substrate 100 and grid structure, said oxide layer 104 utilizes thermal oxidation technology to make.
Then, please refer to Fig. 3, form the side wall medium layer 105 that covers said oxide layer 104.
Then; Please refer to Fig. 4, carry out etching technics, remove side wall medium layer 105 and oxide layer 104 on the said Semiconductor substrate 100; The oxide layer 104 and side wall medium layer 105 that keep the sidewall of said grid structure, said side wall medium layer 105 forms side wall with oxide layer 104.
At last, be mask with said side wall and grid structure, carry out ion and inject, in said Semiconductor substrate 100, form source region 106 and drain region 107.
, publication number can find more information in being the one Chinese patent application of CN101789447A about prior art.
Find that in reality there is the problem of leakage current in the transistor that existing method is made.
Summary of the invention
The problem that the present invention solves has provided a kind of transistorized manufacture method, and said method has been improved the problem of transistorized leakage current.
For addressing the above problem, the present invention provides a kind of transistorized manufacture method, and said method comprises:
Semiconductor substrate is provided, is formed with grid structure on the said Semiconductor substrate;
Oxide layer is formed on sidewall and top at said semiconductor substrate surface and grid structure, and said oxide layer utilizes depositing operation to make;
On said oxide layer, form side wall medium layer;
Removal is positioned at side wall medium layer and the oxide layer on the said Semiconductor substrate, keeps to be positioned at the sidewall of grid structure and the side wall medium layer and the oxide layer at top, and said side wall medium layer and oxide layer form sidewall structure;
With said grid structure and sidewall structure is mask, carries out ion and injects, and in the Semiconductor substrate of grid structure and sidewall structure both sides, forms source region and drain region.
Alternatively, said depositing operation is atom layer deposition process or chemical vapor deposition method, and said chemical vapor deposition method is high density plasma CVD technology or low-pressure chemical vapor deposition process.
Alternatively, the temperature range of said chemical vapor deposition method is 350～600 degrees centigrade, and time range is 5～600 seconds.
Alternatively, the temperature range of said atom layer deposition process is 100～650 degrees centigrade, and time range is 30～1200 seconds.
Alternatively, said thickness of oxide layer scope is 5～100 dusts.
Alternatively; Said grid structure comprises grid oxic horizon and the polysilicon gate that is positioned at said gate oxide top; Said grid oxic horizon utilizes oxidation technology to make; After forming said grid structure on the said Semiconductor substrate, before the sidewall and top formation oxide layer of said Semiconductor substrate and grid structure, also comprise: the step that said Semiconductor substrate is annealed.
Alternatively, saidly be annealed into the annealing of rapid thermal annealing or boiler tube.
Alternatively, the temperature range of said annealing is: 500～1100 degrees centigrade, the pressure limit of said annealing is 1～780Torr.
Alternatively, said annealing utilizes the mist of nitrogen or inert gas or nitrogen and inert gas to carry out.
Alternatively, said inert gas is one or more in argon gas, helium, the xenon.
Compared with prior art; The present invention has the following advantages: oxide layer is formed on sidewall and top at Semiconductor substrate and grid structure; Said oxide layer utilizes depositing operation to make; Thereby compare with the existing silicon that can consume Semiconductor substrate that utilizes oxidation technology to make oxide layer, the silicon loss (SiliconLoss) that causes Semiconductor substrate; The depositing operation that the present invention makes the oxide layer utilization can not consume the silicon of Semiconductor substrate, thereby has avoided the influence to the silicon of Semiconductor substrate, thereby has improved the problem of transistorized leakage current.
Further optimally, before forming said oxide layer, said semiconductor substrate processing is annealed; Remove the pollutant on the Semiconductor substrate on the one hand; On the other hand, the gate oxide of repairing the manufacturing grid structure is to the damage that said semiconductor substrate surface causes, and makes the smooth surface of Semiconductor substrate; Thereby the carrying out that helps subsequent deposition process improved the oxide layer of said depositing operation formation and the adhesiveness of Semiconductor substrate and grid structure.
Description of drawings
Fig. 1～Fig. 4 is the transistor fabrication method cross-sectional view of prior art;
Fig. 5 is a transistor fabrication method flow sketch map of the present invention;
Fig. 6～Fig. 9 is the transistor fabrication method cross-sectional view of one embodiment of the invention.
Embodiment
There is the problem of leakage current in existing transistor.Discover that through the inventor reason that causes transistor drain current is the silicon loss of Semiconductor substrate, said silicon loss makes semiconductor substrate surface rough and uneven in surface, forms leakage current easily, has influenced the performance of device.
Particularly, please combine Fig. 2, when making said oxide layer 104; Prior art utilizes oxidation technology to make, and said oxidation technology is aerating oxygen under hot environment usually, utilizes the pasc reaction on oxygen and Semiconductor substrate 200 and polysilicon gate 103 surfaces; Form silica, therefore, oxidation technology can consume a part of silicon; Thereby make the silicon on Semiconductor substrate 200 surfaces reduce, and cause Semiconductor substrate 200 surfaces rough and uneven in surface, influenced the performance of device.
In order to address the above problem, the present invention proposes a kind of transistorized manufacture method.Please refer to transistor fabrication method flow sketch map of the present invention shown in Figure 5, said method comprises:
Step S1 provides Semiconductor substrate, is formed with grid structure on the said Semiconductor substrate;
Step S2 forms oxide layer at the sidewall and the top of said semiconductor substrate surface and grid structure, and said oxide layer utilizes depositing operation to make;
Step S3 forms side wall medium layer on said oxide layer;
Step S4, removal is positioned at side wall medium layer and the oxide layer on the said Semiconductor substrate, keeps to be positioned at the sidewall of grid structure and the side wall medium layer and the oxide layer at top, and said side wall medium layer and oxide layer form sidewall structure;
Step S5 is a mask with said grid structure and sidewall structure, carries out ion and injects, and in the Semiconductor substrate of grid structure and sidewall structure both sides, forms source region and drain region.
To combine concrete embodiment that technical scheme of the present invention is carried out detailed explanation below.
For technical scheme of the present invention is described better, please refer to the transistor fabrication method cross-sectional view of the one embodiment of the invention of Fig. 6～shown in Figure 9.
At first, please refer to Fig. 6, Semiconductor substrate 200 is provided, be formed with isolation structure 201 in the said Semiconductor substrate 200, the Semiconductor substrate 200 between the adjacent isolation structure 201 is an active area.
Wherein, said grid structure comprises grid oxic horizon 202 and grid 203.The manufacture method of said gate oxide 202 and grid 203 comprises:
Carry out oxidation technology, on said Semiconductor substrate 200, form silicon oxide layer, said silicon oxide layer thickness range is 10～100 dusts;
On said silicon oxide layer, form polysilicon layer, said polysilicon layer utilizes chemical vapor deposition method to make, and the thickness range of said polysilicon layer is 800～5000 dusts;
The said polysilicon layer of etching forms said grid 203;
The said silicon oxide layer of etching forms grid oxic horizon 202.
Said isolation structure 201 can be fleet plough groove isolation structure (STI) or local field oxidation structure.In the present embodiment, said isolation structure 201 is a fleet plough groove isolation structure.The manufacture method of said fleet plough groove isolation structure is not done detailed explanation as those skilled in the art's known technology at this.
When above-mentioned manufacturing grid oxide layer 202, utilization be oxidation technology, said oxidation technology can consume the silicon of Semiconductor substrate 200, and forms scraggly situation on the surface of Semiconductor substrate 200.As the preferred embodiments of the present invention, after said grid structure forms, the step that said Semiconductor substrate 200 is annealed.The said step fire that moves back on the one hand can repairing semiconductor substrate 200 the surface; Make the smooth surface of Semiconductor substrate 200; The carrying out that helps subsequent technique; Another is convenient, the inorganic pollution that the step of said annealing can be removed Semiconductor substrate 200 surfaces and water vapour etc., thus improve the surperficial cleanliness factor of said Semiconductor substrate 200.
Said annealing can utilize the boiler tube annealing process, also can be rapid thermal anneal process.Because therefore advantages such as rapid thermal anneal process has heating rate and rate of temperature fall is fast, good uniformity, preferably utilize rapid thermal anneal process.As an embodiment, the temperature range of said annealing is: 500～1100 degrees centigrade, the pressure limit of said annealing is 1～780Torr.
In a preferred embodiment of the invention, said annealing utilizes the mist of nitrogen or nitrogen and inert gas to carry out.The mist of said nitrogen or nitrogen and inert gas can be dispersed evenly to heat the surface of said Semiconductor substrate 200, can prevent that Semiconductor substrate 200 is heated inhomogeneous and deforms.Said inert gas can be in helium, argon gas, the xenon one or more.
In reality, because the price of nitrogen is lower, therefore, preferably utilize nitrogen, to practice thrift cost as anneal gas.
Then, please refer to Fig. 7, form oxide layer 204 at the sidewall and the top of said Semiconductor substrate 200 and grid structure, said oxide layer 204 utilizes depositing operation to make.In the present embodiment, said thickness of oxide layer scope is 5～100 dusts.
Because said oxide layer 204 is to utilize depositing operation to form, and therefore, can not consume the silicon of Semiconductor substrate 200, thus can not form on the surface of Semiconductor substrate 200 rough and uneven in surface, thereby can effectively prevent the transistor tracking current.
Said depositing operation can be atom layer deposition process (ALD), chemical vapor deposition method (CVD).Wherein, said chemical vapor deposition method comprises high density plasma CVD technology (PECVD) or low-pressure chemical vapor deposition process (LPCVD).
When said depositing operation was chemical vapor deposition method, its temperature range was 350～600 degrees centigrade, and time range is 5～600 seconds.
In a preferred embodiment of the invention, said oxide layer 204 utilizes atom layer deposition process to make.Because said atom layer deposition process has the advantage that step covers, thereby the oxide layer 204 that forms can be covered in the sidewall of said grid structure and the surface of top and Semiconductor substrate 200 well.
The temperature range of said atom layer deposition process is 100～650 degrees centigrade, and time range is 30～1200 seconds.Because the compactness extent of the temperature of atom layer deposition process and the oxide layer 204 of formation is influential, particularly, the temperature of atom layer deposition process is less than 400 degrees centigrade the time, and the oxide layer 204 of formation is comparatively loose; The temperature of atom layer deposition process is during greater than 400 degrees centigrade, oxide layer 204 compact structures of formation.Therefore, in a preferred embodiment of the invention, the temperature range of said atom layer deposition process is 400～650 degrees centigrade, in the said temperature scope, and the compact structure of the oxide layer 204 of formation.
Then, please refer to Fig. 8, form side wall medium layer 205 on said oxide layer 204 surfaces, the material of said side wall medium layer 205 can be silicon nitride, silicon oxynitride etc.The manufacture method of said side wall medium layer 205 is the method for chemical vapour deposition (CVD).
Then; Please refer to Fig. 9; Removal is positioned at the side wall medium layer 205 and oxide layer 204 on the said Semiconductor substrate 200, keeps the sidewall and the side wall medium layer 205 and oxide layer 204 at top, said side wall medium layer 205 and the oxide layer 204 formation sidewall structures that are positioned at grid structure.
Side wall medium layer 205 on the said Semiconductor substrate 200 utilizes lithographic method to remove with oxide layer 204, and said lithographic method is identical with prior art, as those skilled in the art's known technology, does not do detailed explanation at this.
Then, be mask with said grid structure and sidewall structure, carry out ion and inject, in the Semiconductor substrate 200 of grid structure and sidewall structure both sides, form source region 206 and drain region 207.Said ion is injected to source/leakage ion and injects.The method that said source/leakage ion injects is identical with prior art.
To sum up, transistorized manufacture method provided by the invention is utilized depositing operation to form oxide layer, thereby has been reduced the damage to Semiconductor substrate, has reduced the silicon loss of Semiconductor substrate, thereby has improved transistorized leakage problem.
Though the present invention with preferred embodiment openly as above; But it is not to be used for limiting the present invention; Any those skilled in the art are not breaking away from the spirit and scope of the present invention; Can utilize the method and the technology contents of above-mentioned announcement that technical scheme of the present invention is made possible change and modification, therefore, every content that does not break away from technical scheme of the present invention; To any simple modification, equivalent variations and modification that above embodiment did, all belong to the protection range of technical scheme of the present invention according to technical spirit of the present invention.
Claims (10)
1. a transistorized manufacture method is characterized in that, comprising:
Semiconductor substrate is provided, is formed with grid structure on the said Semiconductor substrate;
Oxide layer is formed on sidewall and top at said semiconductor substrate surface and grid structure, and said oxide layer utilizes depositing operation to make;
On said oxide layer, form side wall medium layer;
Removal is positioned at side wall medium layer and the oxide layer on the said Semiconductor substrate, keeps to be positioned at the sidewall of grid structure and the side wall medium layer and the oxide layer at top, and said side wall medium layer and oxide layer form sidewall structure;
With said grid structure and sidewall structure is mask, carries out ion and injects, and in the Semiconductor substrate of grid structure and sidewall structure both sides, forms source region and drain region.
2. transistorized manufacture method as claimed in claim 1; It is characterized in that; Said depositing operation is atom layer deposition process or chemical vapor deposition method, and said chemical vapor deposition method is high density plasma CVD technology or low-pressure chemical vapor deposition process.
3. transistorized manufacture method as claimed in claim 2 is characterized in that, the temperature range of said chemical vapor deposition method is 350～600 degrees centigrade, and time range is 5～600 seconds.
4. transistorized manufacture method as claimed in claim 2 is characterized in that, the temperature range of said atom layer deposition process is 100～650 degrees centigrade, and time range is 30～1200 seconds.
5. like the described transistorized manufacture method of arbitrary claim in the claim 1～4, it is characterized in that said thickness of oxide layer scope is 5～100 dusts.
6. transistorized manufacture method as claimed in claim 1; It is characterized in that; Said grid structure comprises grid oxic horizon and the grid that is positioned at said gate oxide top, and said grid oxic horizon utilizes oxidation technology to make, after forming said grid structure on the said Semiconductor substrate; Before oxide layer is formed on the sidewall of said Semiconductor substrate and grid structure and top, also comprise: the step that said Semiconductor substrate is annealed.
7. transistorized manufacture method as claimed in claim 6 is characterized in that, saidly is annealed into the annealing of rapid thermal annealing or boiler tube.
8. like claim 6 or 7 described transistorized manufacture methods, it is characterized in that the temperature range of said annealing is: 500～1100 degrees centigrade, the pressure limit of said annealing is 1～780Torr.
9. like claim 6 or 7 described transistorized manufacture methods, it is characterized in that said annealing utilizes the mist of nitrogen or inert gas or nitrogen and inert gas to carry out.
10. transistorized manufacture method as claimed in claim 9 is characterized in that, said inert gas is one or more in argon gas, helium, the xenon.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010105481137A CN102468173A (en) | 2010-11-17 | 2010-11-17 | Method for making transistor |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010105481137A CN102468173A (en) | 2010-11-17 | 2010-11-17 | Method for making transistor |
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| CN102468173A true CN102468173A (en) | 2012-05-23 |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103579338A (en) * | 2012-08-09 | 2014-02-12 | 南亚科技股份有限公司 | Semiconductor and manufacturing method thereof |
| CN105097518A (en) * | 2014-04-30 | 2015-11-25 | 中芯国际集成电路制造(上海)有限公司 | Fin type field effect transistor formation method |
| CN114823738A (en) * | 2022-06-30 | 2022-07-29 | 晶芯成(北京)科技有限公司 | Semiconductor device and manufacturing method thereof |
| CN116053210A (en) * | 2023-03-30 | 2023-05-02 | 合肥新晶集成电路有限公司 | Method for preparing semiconductor structure and semiconductor structure |
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| US20040256671A1 (en) * | 2003-06-17 | 2004-12-23 | Kuo-Tai Huang | Metal-oxide-semiconductor transistor with selective epitaxial growth film |
| US20050215019A1 (en) * | 2004-03-29 | 2005-09-29 | Yu-Ren Wang | Method of manufacturing metal-oxide-semiconductor transistor |
| CN101393862A (en) * | 2007-09-20 | 2009-03-25 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method for gate lateral wall layer and semi-conductor device |
| CN101572230A (en) * | 2008-04-30 | 2009-11-04 | 中芯国际集成电路制造(北京)有限公司 | Method for improving thickness consistency of oxide layer on side wall of grid electrode and method for manufacturing grid electrode |
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2010
- 2010-11-17 CN CN2010105481137A patent/CN102468173A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| US20040256671A1 (en) * | 2003-06-17 | 2004-12-23 | Kuo-Tai Huang | Metal-oxide-semiconductor transistor with selective epitaxial growth film |
| US20050215019A1 (en) * | 2004-03-29 | 2005-09-29 | Yu-Ren Wang | Method of manufacturing metal-oxide-semiconductor transistor |
| CN101393862A (en) * | 2007-09-20 | 2009-03-25 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method for gate lateral wall layer and semi-conductor device |
| CN101572230A (en) * | 2008-04-30 | 2009-11-04 | 中芯国际集成电路制造(北京)有限公司 | Method for improving thickness consistency of oxide layer on side wall of grid electrode and method for manufacturing grid electrode |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103579338A (en) * | 2012-08-09 | 2014-02-12 | 南亚科技股份有限公司 | Semiconductor and manufacturing method thereof |
| CN103579338B (en) * | 2012-08-09 | 2016-09-14 | 南亚科技股份有限公司 | Semiconductor device and manufacture method thereof |
| CN105097518A (en) * | 2014-04-30 | 2015-11-25 | 中芯国际集成电路制造(上海)有限公司 | Fin type field effect transistor formation method |
| CN114823738A (en) * | 2022-06-30 | 2022-07-29 | 晶芯成(北京)科技有限公司 | Semiconductor device and manufacturing method thereof |
| CN114823738B (en) * | 2022-06-30 | 2022-09-30 | 晶芯成(北京)科技有限公司 | Semiconductor device and manufacturing method thereof |
| CN116053210A (en) * | 2023-03-30 | 2023-05-02 | 合肥新晶集成电路有限公司 | Method for preparing semiconductor structure and semiconductor structure |
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Application publication date: 20120523 |