CN103579076A - Method for forming shallow channel isolation region - Google Patents
Method for forming shallow channel isolation region Download PDFInfo
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- CN103579076A CN103579076A CN201210261968.0A CN201210261968A CN103579076A CN 103579076 A CN103579076 A CN 103579076A CN 201210261968 A CN201210261968 A CN 201210261968A CN 103579076 A CN103579076 A CN 103579076A
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- oxide layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
- H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
- H01L21/02337—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour
- H01L21/0234—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour treatment by exposure to a plasma
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Abstract
The invention discloses a method for forming a shallow channel isolation region which is formed before a high dielectric constant gate oxide layer. The method includes the steps that an isolation oxidization layer and a silicon nitride layer are sequentially formed on a semiconductor substrate, the silicon nitride layer, the isolation oxidization layer and the semiconductor substrate are sequentially etched so that a channel is formed in the semiconductor substrate, a liner silicon oxide layer grows on the surface of the inside of the channel, oxides are filled into the channel and are polished to form the shallow channel isolation region, and the silicon nitride layer is removed. When the oxides are filled into the channel, the silicon oxide layer is formed in the atmosphere pressure chemical vapor deposition method, the density of the silicon oxide layer is increased, and the preceding steps are carried out repeatedly. According to the method, the situation that the equivalent oxide thickness of the high dielectric constant gate oxide layer is increased can be avoided.
Description
Technical field
The present invention relates to the manufacturing technology of semiconductor device, particularly a kind of method that forms shallow channel isolation area.
Background technology
In order to control short-channel effect, smaller szie requirement on devices further improves gate electrode electric capacity.This can realize by the thickness of continuous attenuate gate oxide, but the thing followed is the lifting of gate electrode leakage current.When silicon dioxide is as gate oxide, thickness is during lower than 5.0 nanometer, and leakage current just becomes and cannot stand.Solution to the problems described above is used high-k (HK) insulating material to replace silicon dioxide exactly, high dielectric constant insulating material can be hafnium silicate, hafnium silicon oxygen nitrogen compound, hafnium oxide etc., dielectric constant is generally all greater than 15, adopt this material can further improve gate capacitance, gate leak current can be significantly improved again simultaneously.For identical gate oxide thickness, by high dielectric constant insulating material and metal gate electrode collocation, its gate electrode leakage current will reduce several index magnitudes, and solve problem incompatible between high dielectric constant insulating material and polysilicon with metal gate electrode replacement polygate electrodes.
Therefore, high-k gate oxide and metal gate electrode are used to manufacture MOS device.
Prior art is before making high-k gate oxide, and the concrete manufacture method of shallow channel isolation area comprises the steps:
Step 11, in Semiconductor substrate 100 thermal oxide growth isolating oxide layer 101, with protection active area, in the follow-up process of removing silicon nitride layer, avoiding chemistry stains, and as the stress-buffer layer between silicon nitride layer and silicon substrate, described Semiconductor substrate is silicon substrate;
Step 12, at the surface deposition silicon nitride layer 102 of described isolating oxide layer 101; Wherein, the silicon nitride layer that in this step, deposition obtains is the mask material that one deck is firm;
The etching of step 13, shallow trench: etch silicon nitride layer 102, isolating oxide layer 101 and Semiconductor substrate 100 successively, at the interior formation groove of described Semiconductor substrate 100;
The growth of step 14, trench liner silica 103, at the inner superficial growth one deck of groove liner oxidation silicon 103, this liner oxidation silicon 103 is for improving the interfacial characteristics between Semiconductor substrate and the oxide of follow-up filling;
Step 15, trench oxide 104 are filled and polishing, adopt the method for chemical vapour deposition (CVD), and fill oxide in groove, then carries out the polishing of oxide; Wherein, the silicon nitride layer that deposition obtains in step 12 can be protected active area in the process of carrying out this step, serves as the barrier material of polishing, prevents the excessive polishing of oxide;
Step 16, remove described silicon nitride layer 102.
According to foregoing description, step 11 to the structural representation of 15 formation as shown in Figure 1a, the structural representation that step 16 forms is as shown in Figure 1 b.Follow-up active region between shallow channel isolation area forms MOS device.Particularly, at Semiconductor substrate 100 surfaces successively growth interface layer (not shown), high-k gate oxide 105, protective layer (not shown) and polysilicon layer 106, as shown in Fig. 1 c.Wherein, boundary layer as thin as a wafer, is generally silicon oxide layer, or silicon oxynitride layer.High-k gate oxide 105 can be hafnium silicate, hafnium silicon oxygen nitrogen compound or hafnium oxide etc., and dielectric constant is generally all greater than 15.Protective layer can be the lamination of titanium nitride (TiN) or tantalum nitride (TaN) or both combinations.What because final, form is metal gate electrode, and replacement gate can be substituted by metal gate electrode, that is to say that replacement gate is finally non-existent, so the material of grid can have multiplely as an alternative, in the present embodiment, the material of replacement gate is polysilicon.
It should be noted that, prior art is fill oxide in groove, generally adopts the method for aumospheric pressure cvd (APCVD), tetraethoxysilane (TEOS) and ozone (O
3) reaction formation silica, the advantage of this method is the groove for high depth-to-width ratio, there is good covering filling capacity, but the silicon oxide layer that this deposition process obtains, more loose, film is porous relatively, under the environment of high temperature, in film, free oxygen is easy to be diffused in high-k gate oxide or boundary layer, and hafnium element activity in high-k gate oxide is more intense, controlled poor to oxygen, so be easy to make the equivalent oxide thickness (EOT) of high-k gate oxide to become large, EOT is less, mean that MOS device performance is better, therefore how to increase the density of the silicon oxide layer of filling in shallow channel isolation area, prevent that oxygen diffusion wherein from becoming the problem of paying close attention in the industry.
Summary of the invention
In view of this, the invention provides a kind of method that forms shallow channel isolation area, can avoid the equivalent oxide thickness of high-k gate oxide to increase.
Technical scheme of the present invention is achieved in that
Form a method for shallow channel isolation area, described shallow channel isolation area formed before high-k gate oxide, and the method comprises:
In Semiconductor substrate, form successively isolating oxide layer and silicon nitride layer;
Etch silicon nitride layer, isolating oxide layer and Semiconductor substrate form groove in described Semiconductor substrate successively;
At the inner superficial growth one deck of described groove liner oxidation silicon;
In groove, carry out filling and the polishing of oxide, form shallow channel isolation area, and remove described silicon nitride layer;
It is characterized in that, the filling of carrying out oxide in groove adopts aumospheric pressure cvd APCVD form silicon oxide layer and increase the method that silicon oxide layer density combines, and repeatedly loops.
The method that increases silicon oxide layer density comprises: in deposition reaction chamber, pass into nitrogen, or carbon containing class gas, or argon gas, or the combination in any of three kinds of gases.
The time that passes into every kind of gas in deposition reaction chamber is 5～25 seconds.
While passing into gas, deposition reaction chamber power is 50～500 watts.
The flow that passes into every kind of gas in deposition reaction chamber is that 50～1000 standard cubic centimeters are per minute.
Aumospheric pressure cvd adopts tetraethoxysilane and ozone reaction to form silica.
From such scheme, can find out, the filling of shallow channel isolation area of the present invention inner oxide has deposited several times, and after each deposition, all the oxide layer of deposition is increased the processing of film density, like this, can anti-block diffuse in high-k gate oxide and go, improve the performance of semiconductor device.
Accompanying drawing explanation
Fig. 1 a to Fig. 1 c is the structural representation that prior art forms the detailed process of shallow channel isolation area and follow-up active region formation high-k gate oxide between shallow channel isolation area.
Fig. 2 is the schematic flow sheet of shallow channel isolation area of the present invention manufacture method.
Fig. 2 a to 2e is the structural representation that the present invention forms shallow channel isolation area detailed process.
Embodiment
For making object of the present invention, technical scheme and advantage clearer, referring to the accompanying drawing embodiment that develops simultaneously, the present invention is described in further detail.
The present invention is before making high-k gate oxide, and the concrete manufacturing process schematic diagram of shallow channel isolation area refers to Fig. 2 a to Fig. 2 e, and the schematic flow sheet of concrete manufacture method as shown in Figure 2, comprises the steps:
Particularly, thermal oxide growth isolating oxide layer 101 in Semiconductor substrate 100, stains to protect active area to avoid chemistry in the follow-up process of removing silicon nitride layer, and as the stress-buffer layer between silicon nitride layer and silicon substrate; Then at the surface deposition silicon nitride layer 102 of described isolating oxide layer 101; Wherein, the silicon nitride layer that in this step, deposition obtains is the mask material that one deck is firm;
The etching of step 22, shallow trench: etch silicon nitride layer 102, isolating oxide layer 101 and Semiconductor substrate 100 successively, at the interior formation groove of described Semiconductor substrate 100;
The growth of step 23, trench liner silica 103, at the inner superficial growth one deck of groove liner oxidation silicon 103, this liner oxidation silicon 103 is for improving the interfacial characteristics between Semiconductor substrate and the oxide of follow-up filling;
The structural representation forming according to step 21 to step 23 as shown in Figure 2 a.
Wherein, the filling of carrying out oxide in groove adopts aumospheric pressure cvd form silicon oxide layer and increase the method that silicon oxide layer density combines, and repeatedly loops.General cycle-index is not less than 2 times.The method of increase silicon oxide layer density has multiple, can be: in deposition reaction chamber, pass into nitrogen, or carbon containing class gas, or argon gas, or the combination in any of three kinds of gases.Specifically, the combination in any of three kinds of gases refers to and passes into successively various gas, and every kind of gas acts on the oxide surface scheduled time.The embodiment of the present invention be take 2 circulations and is described as example.
Step 241, employing aumospheric pressure cvd method are carried out silicon oxide layer deposition for the first time, form the first silicon oxide layer 201, as shown in Figure 2 b;
In the embodiment of the present invention, the filling thickness of oxide is 6000 dusts altogether, and silicon oxide layer deposit thickness is about 3000 dusts so for the first time.
Step 242, in deposition reaction chamber, pass into nitrogen, then pass into the processing that argon gas increases silicon oxide layer density;
Wherein, the object that passes into nitrogen in deposition reaction chamber is, free oxygen during by silicon oxide layer deposition for the first time, combines with nitrogen, and free oxygen is fixed in Semiconductor substrate, and anti-block diffuses in high-k gate oxide.The object that passes into argon gas is, the method increase by physical bombardment is the density of silicon oxide layer deposited for the first time.Here, flow 50～1000 standard cubic centimeters that pass into nitrogen are per minute, and it is 50～500 watts that reaction chamber power is set, and the time of passing into is 5～25 seconds; After nitrogen and the silicon oxide layer depositing for the first time fully act on, then pass into argon gas, flow 50～1000 standard cubic centimeters that pass into argon gas are per minute, and it is 50～500 watts that reaction chamber power is set, and the time of passing into is 5～25 seconds.
Step 243, employing aumospheric pressure cvd method are carried out silicon oxide layer deposition for the second time, form the second silicon oxide layer 202, as shown in Figure 2 c;
In the embodiment of the present invention, the filling thickness of oxide is 6000 dusts altogether, and silicon oxide layer deposit thickness is also about 3000 dusts so for the second time.
Step 244, in deposition reaction chamber, pass into the processing that argon gas increases silicon oxide layer density;
In like manner, flow 50～1000 standard cubic centimeters that pass into argon gas are per minute, and it is 50～500 watts that reaction chamber power is set, and the time of passing into is 5～25 seconds.
Step 245, the oxide of filling in groove is carried out to polishing, as shown in Figure 2 d.Wherein, the silicon nitride layer that deposition obtains in step 21 can be protected active area in the process of carrying out this step, serves as the barrier material of polishing, prevents the excessive polishing of oxide;
So far, embodiment of the present invention shallow channel isolation area forms.
The filling of above-described embodiment oxide deposits at twice, and after the first filling, adopts successively nitrogen and argon gas to increase the processing of film density, after filling for the second time, adopts argon gas to increase the processing of film density.This is the wherein a kind of mode of lifting just, also has multiple implementation, the present invention includes but be not limited to this.For example, the filling of oxide is divided into above deposition twice, after each filling, can adopt separately nitrogen, or carbon containing class gas, or argon gas is processed.Wherein, carbon containing class gas can be any carbon containing class gas such as methane, ethene, fluoroform, its object is, free oxygen during by the deposition of silicon oxide layer for the first time, combine with this carbon containing class gas, free oxygen is fixed in Semiconductor substrate, and anti-block diffuses in high-k gate oxide.
To sum up, by the present invention, form the method for shallow channel isolation area, increased the packed density of oxide, so do not have in the high-k gate oxide that free oxygen is diffused into follow-up formation and go, thereby avoid the equivalent oxide thickness of high-k gate oxide to increase, improved the performance of semiconductor device.
The foregoing is only preferred embodiment of the present invention, in order to limit the present invention, within the spirit and principles in the present invention not all, any modification of making, be equal to replacement, improvement etc., within all should being included in the scope of protection of the invention.
Claims (6)
1. form a method for shallow channel isolation area, described shallow channel isolation area formed before high-k gate oxide, and the method comprises:
In Semiconductor substrate, form successively isolating oxide layer and silicon nitride layer;
Etch silicon nitride layer, isolating oxide layer and Semiconductor substrate form groove in described Semiconductor substrate successively;
At the inner superficial growth one deck of described groove liner oxidation silicon;
In groove, carry out filling and the polishing of oxide, form shallow channel isolation area, and remove described silicon nitride layer;
It is characterized in that, the filling of carrying out oxide in groove adopts aumospheric pressure cvd APCVD form silicon oxide layer and increase the method that silicon oxide layer density combines, and repeatedly loops.
2. the method for claim 1, is characterized in that, the method that increases silicon oxide layer density comprises: in deposition reaction chamber, pass into nitrogen, or carbon containing class gas, or argon gas, or the combination in any of three kinds of gases.
3. method as claimed in claim 2, is characterized in that, the time that passes into every kind of gas in deposition reaction chamber is 5～25 seconds.
4. method as claimed in claim 3, is characterized in that, while passing into gas, deposition reaction chamber power is 50～500 watts.
5. method as claimed in claim 4, is characterized in that, the flow that passes into every kind of gas in deposition reaction chamber is that 50～1000 standard cubic centimeters are per minute.
6. the method for claim 1, is characterized in that, aumospheric pressure cvd adopts tetraethoxysilane and ozone reaction to form silica.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105551962A (en) * | 2015-12-22 | 2016-05-04 | 上海华虹宏力半导体制造有限公司 | Undoped silica glass film forming method under secondary normal pressure |
| CN105489547B (en) * | 2014-10-02 | 2018-10-02 | 格罗方德半导体公司 | The method for defining the area of isolation of semiconductor structure |
| CN112864007A (en) * | 2019-11-28 | 2021-05-28 | 长鑫存储技术有限公司 | Method for forming semiconductor structure |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070032039A1 (en) * | 2005-08-03 | 2007-02-08 | Ming-Te Chen | Sti process for eliminating silicon nitride liner induced defects |
| US20070077723A1 (en) * | 2005-09-30 | 2007-04-05 | Dongbuanam Semiconductor Inc. | Method of forming shallow trench isolation in a semiconductor device |
| CN101079391A (en) * | 2006-05-26 | 2007-11-28 | 中芯国际集成电路制造(上海)有限公司 | Method for semiconductor part with high clearance filling capability |
| CN102487032A (en) * | 2010-12-02 | 2012-06-06 | 中芯国际集成电路制造(北京)有限公司 | Method for forming shallow-trench isolating structure |
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2012
- 2012-07-26 CN CN201210261968.0A patent/CN103579076B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070032039A1 (en) * | 2005-08-03 | 2007-02-08 | Ming-Te Chen | Sti process for eliminating silicon nitride liner induced defects |
| US20070077723A1 (en) * | 2005-09-30 | 2007-04-05 | Dongbuanam Semiconductor Inc. | Method of forming shallow trench isolation in a semiconductor device |
| CN101079391A (en) * | 2006-05-26 | 2007-11-28 | 中芯国际集成电路制造(上海)有限公司 | Method for semiconductor part with high clearance filling capability |
| CN102487032A (en) * | 2010-12-02 | 2012-06-06 | 中芯国际集成电路制造(北京)有限公司 | Method for forming shallow-trench isolating structure |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105489547B (en) * | 2014-10-02 | 2018-10-02 | 格罗方德半导体公司 | The method for defining the area of isolation of semiconductor structure |
| CN105551962A (en) * | 2015-12-22 | 2016-05-04 | 上海华虹宏力半导体制造有限公司 | Undoped silica glass film forming method under secondary normal pressure |
| CN105551962B (en) * | 2015-12-22 | 2018-10-26 | 上海华虹宏力半导体制造有限公司 | Sub-atmospheric pressure non-impurity-doped silica glass film build method |
| CN112864007A (en) * | 2019-11-28 | 2021-05-28 | 长鑫存储技术有限公司 | Method for forming semiconductor structure |
| CN112864007B (en) * | 2019-11-28 | 2022-04-12 | 长鑫存储技术有限公司 | Method for forming semiconductor structure |
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