CN102005379A - Method for improving reliability of gate oxygen at the corner of trench gate - Google Patents
Method for improving reliability of gate oxygen at the corner of trench gate Download PDFInfo
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- CN102005379A CN102005379A CN2010105183867A CN201010518386A CN102005379A CN 102005379 A CN102005379 A CN 102005379A CN 2010105183867 A CN2010105183867 A CN 2010105183867A CN 201010518386 A CN201010518386 A CN 201010518386A CN 102005379 A CN102005379 A CN 102005379A
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Abstract
A method for improving reliability of gate oxygen at the corner of a trench gate comprises the following steps of: providing a semiconductor substrate; preparing a hard masking film with a silicon nitride film; preparing a trench, using the hard masking film as a masking film, and etching the semiconductor substrate to form a trench; preparing gate oxygen and filling polysilicon; carrying out flattening treatment and removing the hard masking film and polysilicon through a chemical polishing process; carrying out source electrode ion implantation and annealing and performing the annealing process at oxide atmosphere; and depositing a dielectric layer. In the invention, the hard masking film with the hard silicon nitride film is used as the hard masking film of the trench, and annealing treatment is carried out at high temperature at oxide atmosphere after the source electrode ion implantation, and the dielectric layer is deposited on the semiconductor substrate by a low-voltage deposition silicon oxide process, so that the growth speed and formation thickness of the gate oxygen are improved and the reliability of the gate oxygen is improved.
Description
Technical field
The present invention relates to the manufacture method of semiconductor device, relate in particular to a kind of method that improves trench gate drift angle grid oxygen reliability.
Background technology
Traditional metal-oxide semiconductor (MOS) (MOS) transistor, its grid, source electrode and drain electrode are positioned on the same horizontal plane, and its surperficial grid structure exists the big and high problem of power consumption of on state resistance, can't well satisfy the demand of power device.In order to satisfy the demand of high power transistor, trench grate MOS device just arises at the historic moment.Trench grate MOS device has not only been inherited horizontal channel MOS transistor input master and has been resisted advantages such as high, that drive current is little, also has advantages such as high pressure resistant, that operating current is big, power output is high, switching speed is fast.
But in the manufacture process of trench grate MOS device, the manufacturing of its trench gate is particularly important, is determining the reliability of trench grate MOS device.
See also Fig. 7, Figure 7 shows that the structural representation of second trench gate 4 of existing trench grate MOS device.Described second trench gate 4 is formed in second Semiconductor substrate 5.In the forming process of described second trench gate 4, specifically may further comprise the steps: at the stacked successively formation second mat oxide layer 61 of the upper surface of described second Semiconductor substrate 5 and second silicon oxide film 62, and by described second silicon oxide film 62 of etching successively and the described second mat oxide layer 61 to form mask 6; By mask 6, second Semiconductor substrate 5 is carried out etching, to form second groove 40; At described second groove, the 40 inwalls second grid oxygen 41 of growing, and in second groove 40, fill second polysilicon gate 42; Second polysilicon gate 42 that is positioned at second groove 40 is carried out planarization.
See also Fig. 8, Figure 8 shows that the design sketch after second polysilicon gate 42 that is positioned at second groove 40 carries out planarization.Significantly,, easily damage the first grid oxygen 41 of second groove, 40 drift angles, cause the poor reliability of first grid oxygen 41 in the process of second polysilicon gate 42 that is arranged in second groove 40 being carried out planarization.
At the problem that prior art exists, this case designer relies on the industry experience for many years of being engaged in, and the active research improvement is so there has been the present invention to improve the method for trench gate drift angle grid oxygen reliability.
Summary of the invention
The present invention be directed in the prior art, existing trench gate drift angle gate oxide thickness inequality, defectives such as poor reliability provide a kind of method that improves trench gate drift angle grid oxygen reliability.
In order to address the above problem, the invention provides a kind of method that improves trench gate drift angle grid oxygen reliability, wherein, a kind of method that improves trench gate drift angle grid oxygen reliability may further comprise the steps: Semiconductor substrate is provided, and described Semiconductor substrate is a silicon-based substrate; The preparation of hard mask, described hard mask has silicon nitride film, and forms the mat oxide layer between described silicon nitride film and Semiconductor substrate, at the side formation silicon oxide film that differs from the mat oxide layer of described silicon nitride; The preparation of groove utilizes above-mentioned hard mask to be mask, and Semiconductor substrate is carried out etching to form groove; The preparation of grid oxygen and polysilicon are filled, and described grid oxygen is formed on described trench wall, and the polysilicon deposit is filled in the described groove; Planarization is removed hard mask and polysilicon by chemical polishing technology; The source electrode ion injects and annealing, and described annealing process carries out under the oxygen atmosphere; Deposition of dielectric layer, described dielectric layer deposit adopt low pressure silicon oxide deposition technology.Described planarization stops at described silicon nitride film place.
Optionally, the mode of the hard mask of described removal is to remove silicon nitride film again after to the polysilicon planarization.
Optionally, the mode of the hard mask of described removal is until carrying out removing silicon nitride film before the injection of source electrode ion.
Optionally, the removal method of described silicon nitride film is to adopt dense hydrofluoric acid or SPA.
Optionally, described silicon nitride film adopts low pressure deposit mode to generate.
Optionally, described mat oxide layer is by crystal column surface is carried out thermal oxidation technology, makes the semiconductor substrate surface oxidation and forms.
In sum, the present invention has the hard mask of the hard mask of hard silicon nitride film as groove by employing, and inject the back employing at the source electrode ion and under the oxygen atmosphere, carry out The high temperature anneal, on Semiconductor substrate, adopt low pressure silicon oxide deposition technology deposition of dielectric layer simultaneously, not only improve the speed of growth of grid oxygen and formed thickness, promoted the reliability of grid oxygen simultaneously.
Description of drawings
Fig. 1 adopts the present invention to improve the trench gate structure schematic diagram of the method manufacturing of trench gate drift angle grid oxygen reliability;
Fig. 2 is the flow chart that the present invention improves the method for trench gate drift angle grid oxygen reliability;
Fig. 3 adopts the present invention to improve the mask structure schematic diagram of groove of the method manufacturing of trench gate drift angle grid oxygen reliability;
Fig. 4 adopts the present invention to improve the hard mask structure schematic diagram of groove of the method manufacturing of trench gate drift angle grid oxygen reliability;
Fig. 5 adopts the present invention to improve the etching groove figure of groove of the method manufacturing of trench gate drift angle grid oxygen reliability;
Fig. 6 is that the flatening process of groove that adopts the present invention to improve the method manufacturing of trench gate drift angle grid oxygen reliability is handled structural representation;
Fig. 7 is the structural representation of existing trench gate;
Fig. 8 is the design sketch after existing trench gate is handled through flatening process.
Embodiment
By the technology contents, the structural feature that describe the invention in detail, reached purpose and effect, described in detail below in conjunction with embodiment and conjunction with figs..
See also Fig. 1, Figure 1 shows that the structural representation of first trench gate 1 of trench grate MOS device.Described first trench gate 1 is positioned at first Semiconductor substrate 2.Described first trench gate 1 has first groove 10, deposit is formed on the first grid oxygen 11 of first groove, 10 inwalls, and is filled in first polysilicon gate 12 in described first groove 10.Described first Semiconductor substrate 2 is a silicon-based substrate.
See also Fig. 2, and in conjunction with consulting Fig. 1, Fig. 3, Fig. 4, Fig. 5, and Fig. 6, the manufacturing of first trench gate 1 of trench grate MOS device finished.The manufacturing of described first trench gate 1 may further comprise the steps:
Execution in step S11: first Semiconductor substrate 2 is provided, and described first Semiconductor substrate 2 is a silicon-based substrate.
Execution in step S12: on described first Semiconductor substrate 2, make hard mask 3.See also Fig. 3, and Fig. 4, the preparation of described hard mask 3 further comprises:
The first, on described first Semiconductor substrate 2, form the first mat oxide layer 31.The described first mat oxide layer 31 is by crystal column surface being carried out thermal oxidation technology, first Semiconductor substrate, 2 surface oxidations being formed.The described first mat oxide layer 31 can slacken the stress problem that exists between silicon nitride and the silicon.
The second, at the surface deposition one deck silicon nitride film 32 that differs from first Semiconductor substrate 2 of the described first mat oxide layer 31.Described silicon nitride film 32 is one deck hard material, in order in the forming process of first groove 10 as mask.The method of low-pressure chemical vapor phase deposition is adopted in the formation of described silicon nitride film 32.
In the deposition process of silicon nitride film 32, because the diffusion coefficient of gas increases under the low pressure, the mass transport of gaseous reactant and accessory substance is speeded up, thereby increase the reaction speed that forms deposition film.Diffusion coefficient means that greatly mass transport is fast, and inhomogeneous can the elimination in a short period of time that gas molecule distributes evenly distributes whole system space gas molecule, and grow the uniform silicon nitride film 32 of thickness, and have good step coverage energy.
Three, form as the silicon nitride film 32 of mask after, and form first silicon oxide film 33 on the surface that differs from the first mat oxide layer 31 of silicon nitride 32.The method of low-pressure chemical vapor phase deposition is adopted in the formation of described first silicon oxide film 33.After above-mentioned steps is finished, then be positioned at the vertical successively from the bottom to top stacked first mat oxide layer 31 in described first Semiconductor substrate 2 surfaces, silicon nitride film 32, and first silicon oxide film 33.
Four, according to the structure graph of the first predetermined groove 10, first silicon oxide film 33, silicon nitride film 32 and the first mat oxide layer 31 that will be positioned on described first Semiconductor substrate 2 are carried out etching successively, and then form the hard mask 3 of first groove 10.
Execution in step S13: utilize described hard mask 3 to be mask, and first Semiconductor substrate 2 is carried out etching, to form first groove 10.
Please continue to consult Fig. 5, Figure 5 shows that formed structural representation behind over etching with first trench gate 1 of first groove 10.Described first groove 10 is formed in first Semiconductor substrate 2.Described also vertical stacked first silicon oxide film 33, silicon nitride film 32 and the first mat oxide layer 31 in described first groove 10 top layers that be positioned at is etched.
Execution in step S14: remove first silicon oxide film 33, and at the inwall of described first groove 10 growth first grid oxygen 11, and first polysilicon gate 12 is filled in deposit in described first groove 10.
Inwall at described first groove 10 forms first grid oxygen 11, and first polysilicon gate 12 is filled in deposit in described first groove 10.Described first grid oxygen 11 plays the effect of isolation between first polysilicon gate 12 and first Semiconductor substrate 2.
Execution in step S15: first polysilicon gate 12 of filling in first groove 10 is carried out planarization, remove hard mask 3 then, thereby form the first complete trench gate 1.Described planarization is a CMP (Chemical Mechanical Polishing) process.The removal of described hard mask 15 is the removal of silicon nitride film 32.
The present invention adopts has the mask of the hard mask 3 of hard silicon nitride film 32 as first trench gate 1, so when first polysilicon gate 12 in first groove 10 is carried out planarization, the chemical polishing operation just stops at described silicon nitride film 32 places, and can not cross the first grid oxygen 11 that polishing consequently damages first trench gate, 1 drift angle place.After planarization technology finishes, remove described silicon nitride film 32.That is, the operation of described removal silicon nitride film 13 is to carry out after finishing first polysilicon gate, 12 planarization.The method of described removal silicon nitride film 32 is to utilize dense hydrofluoric acid or SPA to remove.
Simultaneously, for better implement the present invention, preferably adopt in the present invention to have certain thickness silicon nitride film 32 as hard mask 3.When the place, side position in first trench gate 1 carries out the injection of source electrode ion, remove silicon nitride film 32.The method of described removal silicon nitride film 32 is to utilize dense hydrofluoric acid or SPA to remove.Described have certain thickness silicon nitride film 32 and just can suppress the thermal source that produces in other manufacturing processes of trench grate MOS device and the source electrode ion is injected the influence that produces.
Execution in step S16: carry out the source electrode ion in the side position of first trench gate 1 and inject and annealing.After finishing the injection of source electrode ion, need carry out The high temperature anneal.In the present invention, described source electrode ion is a n type ion, for example arsenic etc.Simultaneously, described The high temperature anneal is carried out under the oxygen atmosphere.Be specially aerating oxygen in described The high temperature anneal process, make first trench gate 1 in oxygen atmosphere, finish annealing in process.In the oxygen atmosphere, the speed of growth of first grid oxygen 11 and formation thickness will be greatly improved, and its stability significantly gets a promotion.
Execution in step S17: deposit forms dielectric layer (not shown) on described first Semiconductor substrate 2.In the present invention, the generation type of described dielectric layer (not shown) is a low pressure silicon oxide deposition technology.
In sum, the present invention has the hard mask 3 of the hard mask 3 of hard silicon nitride film 32 as first groove 10 by employing, and inject the back employing at the source electrode ion and under the oxygen atmosphere, carry out The high temperature anneal, on first Semiconductor substrate 2, adopt low pressure silicon oxide deposition technology deposition of dielectric layer (not shown) simultaneously, not only improve the speed of growth of first grid oxygen 11 and formed thickness, promoted the reliability of first grid oxygen 11 simultaneously.
Those skilled in the art all should be appreciated that, under the situation that does not break away from the spirit or scope of the present invention, can carry out various modifications and variations to the present invention.Thereby, if when any modification or modification fall in the protection range of appended claims and equivalent, think that the present invention contains these modifications and modification.
Claims (8)
1. a method that improves trench gate drift angle grid oxygen reliability is characterized in that, the method for described raising trench gate drift angle grid oxygen reliability may further comprise the steps:
Semiconductor substrate is provided, and described Semiconductor substrate is a silicon-based substrate;
The preparation of hard mask, described hard mask has silicon nitride film, and forms the mat oxide layer between described silicon nitride film and Semiconductor substrate, at the side formation silicon oxide film that differs from the mat oxide layer of described silicon nitride;
The preparation of groove utilizes above-mentioned hard mask to be mask, and Semiconductor substrate is carried out etching to form groove;
The preparation of grid oxygen and polysilicon are filled, and described grid oxygen is formed on described trench wall, and the polysilicon deposit is filled in the described groove;
Planarization is removed hard mask and polysilicon by chemical polishing technology;
The source electrode ion injects and annealing, and described annealing process carries out under the oxygen atmosphere;
Deposition of dielectric layer, described dielectric layer deposit adopt low pressure silicon oxide deposition technology.
2. the method for raising trench gate drift angle grid oxygen reliability as claimed in claim 1 is characterized in that, the mode of the hard mask of described removal is to remove silicon nitride film again after to the polysilicon planarization.
3. the method for raising trench gate drift angle grid oxygen reliability as claimed in claim 2 is characterized in that, the removal method of described silicon nitride film is to adopt dense hydrofluoric acid or SPA.
4. the method for raising trench gate drift angle grid oxygen reliability as claimed in claim 1 is characterized in that, the mode of the hard mask of described removal is until carrying out removing silicon nitride film before the injection of source electrode ion.
5. the method for raising trench gate drift angle grid oxygen reliability as claimed in claim 4 is characterized in that, the removal method of described silicon nitride film is to adopt dense hydrofluoric acid or SPA.
6. the method for raising trench gate drift angle grid oxygen reliability as claimed in claim 1 is characterized in that, described silicon nitride film adopts low pressure deposit mode to generate.
7. the method for raising trench gate drift angle grid oxygen reliability as claimed in claim 1 is characterized in that, described mat oxide layer is by crystal column surface is carried out thermal oxidation technology, makes the semiconductor substrate surface oxidation and forms.
8. the method for raising trench gate drift angle grid oxygen reliability as claimed in claim 1 is characterized in that described planarization stops at described silicon nitride film place.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201010518386.7A CN102005379B (en) | 2010-10-25 | 2010-10-25 | Improve the method for reliability of apex gate oxide of trench gate |
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| CN201010518386.7A CN102005379B (en) | 2010-10-25 | 2010-10-25 | Improve the method for reliability of apex gate oxide of trench gate |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102184868A (en) * | 2011-04-25 | 2011-09-14 | 上海宏力半导体制造有限公司 | Method for improving reliability of apex gate oxide of trench gate |
| CN103035500A (en) * | 2012-06-04 | 2013-04-10 | 上海华虹Nec电子有限公司 | Formation method of trench gate |
| CN112103185A (en) * | 2020-09-22 | 2020-12-18 | 深圳市芯电元科技有限公司 | Manufacturing method and structure of trench MOSFET |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6642124B1 (en) * | 1999-11-08 | 2003-11-04 | Oki Electric Industry Co., Ltd. | Semiconductor device and manufacturing method thereof |
| EP1528599A2 (en) * | 2003-10-28 | 2005-05-04 | Dongbu Electronics Co., Ltd. | Method for fabricating a semiconductor transistor device |
| CN1726585A (en) * | 2002-12-14 | 2006-01-25 | 皇家飞利浦电子股份有限公司 | Method of manufacturing a trench-gate semiconductor device |
| US20060276001A1 (en) * | 2005-06-06 | 2006-12-07 | Elpida Memory Inc. | Method for manufacturing a semiconductor device having a STI structure |
| CN101645457A (en) * | 2008-08-08 | 2010-02-10 | 万国半导体股份有限公司 | Super-self-aligned trench-dmos structure and method |
| CN101859705A (en) * | 2009-01-29 | 2010-10-13 | 万国半导体有限公司 | High density trench mosfet with single mask predetermined gate trench and contact trench |
-
2010
- 2010-10-25 CN CN201010518386.7A patent/CN102005379B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6642124B1 (en) * | 1999-11-08 | 2003-11-04 | Oki Electric Industry Co., Ltd. | Semiconductor device and manufacturing method thereof |
| CN1726585A (en) * | 2002-12-14 | 2006-01-25 | 皇家飞利浦电子股份有限公司 | Method of manufacturing a trench-gate semiconductor device |
| EP1528599A2 (en) * | 2003-10-28 | 2005-05-04 | Dongbu Electronics Co., Ltd. | Method for fabricating a semiconductor transistor device |
| US20060276001A1 (en) * | 2005-06-06 | 2006-12-07 | Elpida Memory Inc. | Method for manufacturing a semiconductor device having a STI structure |
| CN101645457A (en) * | 2008-08-08 | 2010-02-10 | 万国半导体股份有限公司 | Super-self-aligned trench-dmos structure and method |
| CN101859705A (en) * | 2009-01-29 | 2010-10-13 | 万国半导体有限公司 | High density trench mosfet with single mask predetermined gate trench and contact trench |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102184868A (en) * | 2011-04-25 | 2011-09-14 | 上海宏力半导体制造有限公司 | Method for improving reliability of apex gate oxide of trench gate |
| CN102184868B (en) * | 2011-04-25 | 2016-03-02 | 上海华虹宏力半导体制造有限公司 | Improve the method for reliability of apex gate oxide of trench gate |
| CN103035500A (en) * | 2012-06-04 | 2013-04-10 | 上海华虹Nec电子有限公司 | Formation method of trench gate |
| CN103035500B (en) * | 2012-06-04 | 2015-06-03 | 上海华虹宏力半导体制造有限公司 | Formation method of trench gate |
| CN112103185A (en) * | 2020-09-22 | 2020-12-18 | 深圳市芯电元科技有限公司 | Manufacturing method and structure of trench MOSFET |
| CN112103185B (en) * | 2020-09-22 | 2022-01-11 | 深圳市芯电元科技有限公司 | Manufacturing method and structure of trench MOSFET |
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Owner name: SHANGHAI HUAHONG GRACE SEMICONDUCTOR MANUFACTURING Free format text: FORMER OWNER: HONGLI SEMICONDUCTOR MANUFACTURE CO LTD, SHANGHAI Effective date: 20140515 |
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Effective date of registration: 20140515 Address after: 201203 Shanghai Zhangjiang hi tech park Zuchongzhi Road No. 1399 Applicant after: Shanghai Huahong Grace Semiconductor Manufacturing Corporation Address before: 201203 Shanghai Guo Shou Jing Road, Pudong New Area Zhangjiang hi tech Park No. 818 Applicant before: Hongli Semiconductor Manufacture Co., Ltd., Shanghai |
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