CN102005379B - Improve the method for reliability of apex gate oxide of trench gate - Google Patents
Improve the method for reliability of apex gate oxide of trench gate Download PDFInfo
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- CN102005379B CN102005379B CN201010518386.7A CN201010518386A CN102005379B CN 102005379 B CN102005379 B CN 102005379B CN 201010518386 A CN201010518386 A CN 201010518386A CN 102005379 B CN102005379 B CN 102005379B
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Abstract
Improve a method for reliability of apex gate oxide of trench gate, comprising: Semiconductor substrate is provided; The preparation of hard mask, described hard mask has silicon nitride film; The preparation of groove, utilizes above-mentioned hard mask to be mask, etches to form groove to Semiconductor substrate; The preparation of grid oxygen and polysilicon are filled; Planarization, removes hard mask and polysilicon by surface with chemical polishing technology; Source ion injects and annealing, and described annealing process carries out under oxygen atmosphere; Deposition of dielectric layer.The present invention is by adopting the hard mask with hard silicon nitride film as the hard mask of groove, and employing carries out the high temperature anneal under oxygen atmosphere after source ion injects, adopt depositing silica at low pressure technique deposition of dielectric layer on a semiconductor substrate simultaneously, not only improve the speed of growth of grid oxygen and form thickness, improving the reliability of grid oxygen simultaneously.
Description
Technical field
The present invention relates to the manufacture method of semiconductor device, particularly relate to a kind of method improving reliability of apex gate oxide of trench gate.
Background technology
Traditional metal-oxide semiconductor (MOS) (MOS) transistor, its grid, source electrode and drain electrode are positioned in same level, and its surperficial grid structure also exists the problem that on state resistance is large and power consumption is high, well cannot meet the demand of power device.In order to meet the demand of high power transistor, trench grate MOS device just arises at the historic moment.Trench grate MOS device not only inherits the advantages such as the main anti-height of horizontal channel MOS transistor input, drive current are little, also has the advantages such as high pressure resistant, operating current is large, power output is high, switching speed is fast.
But in the manufacture process of trench grate MOS device, the manufacture of its trench gate is particularly important, decides the reliability of trench grate MOS device.
Refer to Fig. 7, Figure 7 shows that the structural representation of the second trench gate 4 of existing trench grate MOS device.Described second trench gate 4 is formed in the second Semiconductor substrate 5.In the forming process of described second trench gate 4, specifically comprise the following steps: at upper surface stacked formation second mat oxide layer 61 and second silicon oxide film 62 successively of described second Semiconductor substrate 5, and by etching described second silicon oxide film 62 and described second mat oxide layer 61 successively to form mask 6; By mask 6, the second Semiconductor substrate 5 is etched, to form the second groove 40; At described second groove 40 inwall growth second gate oxygen 41, and fill the second polysilicon gate 42 in the second groove 40; Planarization is carried out to the second polysilicon gate 42 being positioned at the second groove 40.
Refer to Fig. 8, Figure 8 shows that the second polysilicon gate 42 being positioned at the second groove 40 carry out planarization after design sketch.Significantly, carrying out the process of planarization to the second polysilicon gate 42 being arranged in the second groove 40, easily damage the first grid oxygen 41 of the second groove 40 drift angle, cause the poor reliability of first grid oxygen 41.
For prior art Problems existing, this case designer is by means of being engaged in the industry experience for many years, and active research improves, so there has been the present invention to improve the method for reliability of apex gate oxide of trench gate.
Summary of the invention
The present invention be directed in prior art, existing trench gate drift angle gate oxide thickness is uneven, and the defects such as poor reliability, provide a kind of method improving reliability of apex gate oxide of trench gate.
In order to solve the problem, the invention provides a kind of method improving reliability of apex gate oxide of trench gate, wherein, a kind of method improving reliability of apex gate oxide of trench gate, comprises the following steps: provide Semiconductor substrate, and described Semiconductor substrate is silicon-based substrate; The preparation of hard mask, described hard mask has silicon nitride film, and forms mat oxide layer between described silicon nitride film and Semiconductor substrate, forms silicon oxide film in the side differing from mat oxide layer of described silicon nitride; The preparation of groove, utilizes above-mentioned hard mask to be mask, etches to form groove to Semiconductor substrate; The preparation of grid oxygen and polysilicon are filled, and described grid oxygen is formed in described trench wall, and polysilicon deposition is filled in described groove; Planarization, removes hard mask and polysilicon by surface with chemical polishing technology; Source ion injects and annealing, and described annealing process carries out under oxygen atmosphere; Deposition of dielectric layer, described dielectric layer deposit adopts depositing silica at low pressure technique.Described planarization stops at described silicon nitride film place.
Optionally, the mode of the hard mask of described removal removes silicon nitride film again after to polysilicon planarization.
Optionally, the mode of the hard mask of described removal is until remove silicon nitride film before carrying out source ion injection.
Optionally, the minimizing technology of described silicon nitride film adopts dense hydrofluoric acid or SPA.
Optionally, described silicon nitride film adopts low pressure deposit mode to generate.
Optionally, described mat oxide layer is by carrying out thermal oxidation technology to crystal column surface, makes semiconductor substrate surface be oxidized and be formed.
In sum, the present invention is by adopting the hard mask with hard silicon nitride film as the hard mask of groove, and employing carries out the high temperature anneal under oxygen atmosphere after source ion injects, adopt depositing silica at low pressure technique deposition of dielectric layer on a semiconductor substrate simultaneously, not only improve the speed of growth of grid oxygen and form thickness, improving the reliability of grid oxygen simultaneously.
Accompanying drawing explanation
Fig. 1 is the trench gate structure schematic diagram manufactured by method adopting the present invention to improve reliability of apex gate oxide of trench gate;
Fig. 2 is the flow chart that the present invention improves the method for reliability of apex gate oxide of trench gate;
Fig. 3 is the mask structure schematic diagram adopting the present invention to improve the groove manufactured by method of reliability of apex gate oxide of trench gate;
Fig. 4 is the hard mask structure schematic diagram adopting the present invention to improve the groove manufactured by method of reliability of apex gate oxide of trench gate;
Fig. 5 is the etching groove figure adopting the present invention to improve the groove manufactured by method of reliability of apex gate oxide of trench gate;
Fig. 6 is the flatening process process structural representation adopting the present invention to improve the groove manufactured by method of reliability of apex gate oxide of trench gate;
Fig. 7 is the structural representation of existing trench gate;
Fig. 8 is the design sketch of existing trench gate after flatening process process.
Embodiment
By describe in detail the invention technology contents, structural feature, reached object and effect, coordinate accompanying drawing to be described in detail below in conjunction with embodiment.
Refer to Fig. 1, Figure 1 shows that the structural representation of the first trench gate 1 of trench grate MOS device.Described first trench gate 1 is positioned at the first Semiconductor substrate 2.The first grid oxygen 11 that described first trench gate 1 has the first groove 10, deposit is formed in the first groove 10 inwall, and be filled in the first polysilicon gate 12 in described first groove 10.Described first Semiconductor substrate 2 is silicon-based substrate.
Refer to Fig. 2, and Fig. 1, Fig. 3, Fig. 4, Fig. 5 are consulted in combination, and Fig. 6, complete the manufacture of the first trench gate 1 of trench grate MOS device.The manufacture of described first trench gate 1 comprises the following steps:
Perform step S11: provide the first Semiconductor substrate 2, described first Semiconductor substrate 2 is silicon-based substrate.
Perform step S12: in described first Semiconductor substrate 2, manufacture hard mask 3.Refer to Fig. 3, and Fig. 4, the preparation of described hard mask 3 comprises further:
The first, in described first Semiconductor substrate 2, the first mat oxide layer 31 is formed.Described first mat oxide layer 31 is by carrying out thermal oxidation technology to crystal column surface, and the first Semiconductor substrate 2 surface oxidation is formed.Described first mat oxide layer 31 can slacken the stress problem existed between silicon nitride and silicon.
The second, at the surface deposition one deck silicon nitride film 32 differing from the first Semiconductor substrate 2 of described first mat oxide layer 31.Described silicon nitride film 32 is one deck hard material, in order in the forming process of the first groove 10 as mask.The method being formed by low-pressure chemical vapor phase deposition of described silicon nitride film 32.
In the deposition process of silicon nitride film 32, because the diffusion coefficient of gas under low pressure increases, the mass transport velocity of gaseous reactant and accessory substance is accelerated, thus increase the reaction speed forming deposition film.Diffusion coefficient means that greatly mass transport is fast, and uneven can the elimination in a short period of time of gas molecule distribution, makes whole system space gases molecule be uniformly distributed, and grow the uniform silicon nitride film 32 of thickness, and have good Step Coverage performance.
Three, as after silicon nitride film 32 formation of mask, and the first silicon oxide film 33 is formed on the surface differing from the first mat oxide layer 31 of silicon nitride 32.The method being formed by low-pressure chemical vapor phase deposition of described first silicon oxide film 33.After above-mentioned steps is finished, be then positioned at described first Semiconductor substrate 2 surface longitudinally stacked first mat oxide layer 31, silicon nitride film 32 successively from the bottom to top, and the first silicon oxide film 33.
Four, according to the structure graph of the first predetermined groove 10, the first silicon oxide film 33 be positioned in described first Semiconductor substrate 2, silicon nitride film 32 and the first mat oxide layer 31 are etched successively, and then form the hard mask 3 of the first groove 10.
Perform step S13: utilize described hard mask 3 to be mask, and the first Semiconductor substrate 2 is etched, to form the first groove 10.
Please continue to refer to Fig. 5, Figure 5 shows that the structural representation with the first trench gate 1 of the first groove 10 formed after over etching.Described first groove 10 is formed in the first Semiconductor substrate 2.Describedly be positioned at described first groove 10 top layer and longitudinally stacked the first silicon oxide film 33, silicon nitride film 32 and the first mat oxide layer 31 is etched.
Perform step S14: remove the first silicon oxide film 33, and grow first grid oxygen 11 at the inwall of described first groove 10, and the first polysilicon gate 12 is filled in deposit in described first groove 10.
Form first grid oxygen 11 at the inwall of described first groove 10, and the first polysilicon gate 12 is filled in deposit in described first groove 10.Described first grid oxygen 11, between the first polysilicon gate 12 and the first Semiconductor substrate 2, plays the effect of isolation.
Perform step S15: planarization is carried out to first polysilicon gate 12 of filling in the first groove 10, then removes hard mask 3, thus form the first complete trench gate 1.Described planarization is CMP (Chemical Mechanical Polishing) process.The removal of described hard mask 15 is the removal of silicon nitride film 32.
The present invention adopts the hard mask 3 with hard silicon nitride film 32 as the mask of the first trench gate 1, so when carrying out planarization to the first polysilicon gate 12 in the first groove 10, chemical polishing operation just stops at described silicon nitride film 32 place, and can not cross the first grid oxygen 11 at polishing so that damage the first trench gate 1 drift angle place.After planarization technique terminates, remove described silicon nitride film 32.That is, the operation of described removal silicon nitride film 13 carries out completing after to the first polysilicon gate 12 planarization.The method of described removal silicon nitride film 32 utilizes dense hydrofluoric acid or SPA to remove.
Meanwhile, in order to better implement the present invention, preferably adopting in the present invention and there is certain thickness silicon nitride film 32 as hard mask 3.Until when carrying out source ion injection at position, the side place of the first trench gate 1, remove silicon nitride film 32.The method of described removal silicon nitride film 32 utilizes dense hydrofluoric acid or SPA to remove.Described have the thermal source that certain thickness silicon nitride film 32 just can suppress to produce in other manufacturing processes of trench grate MOS device and source ion injected to the impact produced.
Perform step S16: carry out source ion in the position, side of the first trench gate 1 and inject and annealing.After completing source ion injection, need to carry out the high temperature anneal.In the present invention, described source ion is N-shaped ion, such as arsenic etc.Meanwhile, described the high temperature anneal is carried out under oxygen atmosphere.Be specially and pass into oxygen in described the high temperature anneal process, make the first trench gate 1 complete annealing in process in oxygen atmosphere.In oxygen atmosphere, the speed of growth and the formation thickness of first grid oxygen 11 will be greatly improved, and its stability significantly gets a promotion.
Perform step S17: deposit forms dielectric layer (not shown) in described first Semiconductor substrate 2.In the present invention, the generation type of described dielectric layer (not shown) is depositing silica at low pressure technique.
In sum, the present invention is by adopting the hard mask 3 with hard silicon nitride film 32 as the hard mask 3 of the first groove 10, and employing carries out the high temperature anneal under oxygen atmosphere after source ion injects, in the first Semiconductor substrate 2, adopt depositing silica at low pressure technique deposition of dielectric layer (not shown) simultaneously, not only improve the speed of growth of first grid oxygen 11 and form thickness, improving the reliability of first grid oxygen 11 simultaneously.
Those skilled in the art all should be appreciated that, without departing from the spirit or scope of the present invention, can carry out various modifications and variations to the present invention.Thus, if when any amendment or modification fall in the protection range of appended claims and equivalent, think that these amendment and modification are contained in the present invention.
Claims (8)
1. improve a method for reliability of apex gate oxide of trench gate, it is characterized in that, the method for described raising reliability of apex gate oxide of trench gate comprises the following steps:
There is provided Semiconductor substrate, described Semiconductor substrate is silicon-based substrate;
The preparation of hard mask, described hard mask has silicon nitride film, described silicon nitride is one deck hard material, in order in the forming process of the first groove as mask, described silicon nitride film has certain thickness and source ion is injected to the impact produced to suppress the thermal source produced in other manufacturing processes of trench grate MOS device, and mat oxide layer is formed between described silicon nitride film and Semiconductor substrate, form silicon oxide film in the side differing from mat oxide layer of described silicon nitride;
The preparation of groove, utilizes above-mentioned hard mask to be mask, etches to form groove to Semiconductor substrate;
The preparation of grid oxygen and polysilicon are filled, and described grid oxygen is formed in described trench wall, and polysilicon deposition is filled in described groove;
Planarization, removes hard mask and polysilicon by surface with chemical polishing technology;
Source ion injects and annealing, and described annealing process carries out under oxygen atmosphere;
Deposition of dielectric layer, described dielectric layer deposit adopts depositing silica at low pressure technique.
2. the method improving reliability of apex gate oxide of trench gate as claimed in claim 1, it is characterized in that, the mode of the hard mask of described removal removes silicon nitride film again after to polysilicon planarization.
3. the method improving reliability of apex gate oxide of trench gate as claimed in claim 2, is characterized in that, the minimizing technology of described silicon nitride film adopts dense hydrofluoric acid or SPA.
4. the method improving reliability of apex gate oxide of trench gate as claimed in claim 1, it is characterized in that, the mode of the hard mask of described removal is until remove silicon nitride film before carrying out source ion injection.
5. the method improving reliability of apex gate oxide of trench gate as claimed in claim 4, is characterized in that, the minimizing technology of described silicon nitride film adopts dense hydrofluoric acid or SPA.
6. the method improving reliability of apex gate oxide of trench gate as claimed in claim 1, is characterized in that, described silicon nitride film adopts low pressure deposit mode to generate.
7. the method improving reliability of apex gate oxide of trench gate as claimed in claim 1, it is characterized in that, described mat oxide layer is by carrying out thermal oxidation technology to crystal column surface, makes semiconductor substrate surface be oxidized and be formed.
8. the method improving reliability of apex gate oxide of trench gate as claimed in claim 1, it is characterized in that, described planarization stops at described silicon nitride film place.
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| CN201010518386.7A CN102005379B (en) | 2010-10-25 | 2010-10-25 | Improve the method for reliability of apex gate oxide of trench gate |
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| CN201010518386.7A CN102005379B (en) | 2010-10-25 | 2010-10-25 | Improve the method for reliability of apex gate oxide of trench gate |
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| CN102005379A CN102005379A (en) | 2011-04-06 |
| CN102005379B true CN102005379B (en) | 2015-08-19 |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102184868B (en) * | 2011-04-25 | 2016-03-02 | 上海华虹宏力半导体制造有限公司 | Improve the method for reliability of apex gate oxide of trench gate |
| CN103035500B (en) * | 2012-06-04 | 2015-06-03 | 上海华虹宏力半导体制造有限公司 | Formation method of trench gate |
| CN112103185B (en) * | 2020-09-22 | 2022-01-11 | 深圳市芯电元科技有限公司 | Manufacturing method and structure of trench MOSFET |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6642124B1 (en) * | 1999-11-08 | 2003-11-04 | Oki Electric Industry Co., Ltd. | Semiconductor device and manufacturing method thereof |
| EP1528599A2 (en) * | 2003-10-28 | 2005-05-04 | Dongbu Electronics Co., Ltd. | Method for fabricating a semiconductor transistor device |
| CN1726585A (en) * | 2002-12-14 | 2006-01-25 | 皇家飞利浦电子股份有限公司 | Method of manufacturing a trench-gate semiconductor device |
| CN101645457A (en) * | 2008-08-08 | 2010-02-10 | 万国半导体股份有限公司 | Super-self-aligned trench-dmos structure and method |
| CN101859705A (en) * | 2009-01-29 | 2010-10-13 | 万国半导体有限公司 | High density trench mosfet with single mask pre-defined gate and contact trenches |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| JP4221420B2 (en) * | 2005-06-06 | 2009-02-12 | エルピーダメモリ株式会社 | Manufacturing method of semiconductor device |
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6642124B1 (en) * | 1999-11-08 | 2003-11-04 | Oki Electric Industry Co., Ltd. | Semiconductor device and manufacturing method thereof |
| CN1726585A (en) * | 2002-12-14 | 2006-01-25 | 皇家飞利浦电子股份有限公司 | Method of manufacturing a trench-gate semiconductor device |
| EP1528599A2 (en) * | 2003-10-28 | 2005-05-04 | Dongbu Electronics Co., Ltd. | Method for fabricating a semiconductor transistor device |
| CN101645457A (en) * | 2008-08-08 | 2010-02-10 | 万国半导体股份有限公司 | Super-self-aligned trench-dmos structure and method |
| CN101859705A (en) * | 2009-01-29 | 2010-10-13 | 万国半导体有限公司 | High density trench mosfet with single mask pre-defined gate and contact trenches |
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