CN103855098A - Method for forming storage unit of flash memory - Google Patents
Method for forming storage unit of flash memory Download PDFInfo
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- CN103855098A CN103855098A CN201210513903.0A CN201210513903A CN103855098A CN 103855098 A CN103855098 A CN 103855098A CN 201210513903 A CN201210513903 A CN 201210513903A CN 103855098 A CN103855098 A CN 103855098A
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- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
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Abstract
A method for forming a storage unit of a flash memory comprises the steps that a semiconductor substrate is provided, wherein a plurality of shallow trench isolation structures are arranged in the semiconductor substrate, the surface, between every two adjacent shallow trench isolation structures, of the semiconductor substrate is provided with a second dielectric layer and a floating gate layer on the surface of the second dielectric layer, the side walls and the top surfaces of the shallow trench isolation structures and the side walls and the top surfaces of the floating gate layers are provided with first dielectric layers, and a trench is formed between the first dielectric layers of the surfaces of every two adjacent floating gate layers; control layers with which the trenches are filled on the surfaces of the first dielectric layers are formed; the thermal annealing process is carried out after the control gate layers are formed; the control gate layers higher than the surfaces of the first dielectric layer are removed after the thermal annealing process. The performance of the formed storage unit of the flash memory is improved, and the programming rate is improved.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, relate in particular to a kind of formation method of memory cell of flash memory.
Background technology
In existing integrated circuit, memory device has become a kind of important devices.In current memory device, the development of flash memory (Flash Memory) is particularly rapid.The main feature of flash memory is can keep for a long time canned data in the situation that not powering up; And have that integrated level is high, access speed is fast, be easy to wipe and the advantage such as rewriting, thereby be widely used in multinomial fields such as microcomputer, automation controls.
In prior art, the forming process of the memory cell of flash memory as shown in Figure 1 to Figure 3, comprising:
Please refer to Fig. 1, the Semiconductor substrate 100 with some fleet plough groove isolation structures 101 is provided, Semiconductor substrate 100 surfaces between described adjacent fleet plough groove isolation structure 101 have silicon oxide layer 102; Form floating gate layer 103 on described silicon oxide layer 102 surfaces.
Please refer to Fig. 2, at described floating gate layer 103 and fleet plough groove isolation structure 101 surface coverage dielectric layers 104; At described dielectric layer 104 surface coverage control grid layers 105, the material of described control grid layer 105 is polysilicon.
Please refer to Fig. 3, control grid layer 105 is until expose described dielectric layer 104 surfaces described in planarization; Form electric interconnection structure 106 at described dielectric layer 104 and control grid layer 105 surfaces.
But, the memory cell poor-performing of the flash memory that prior art forms, program speed is lower.
The structure of more flush memory devices or the related data of formation method please refer to the U.S. patent documents that publication number is US2008/0108193.
Summary of the invention
The problem that the present invention solves is to provide a kind of formation method of memory cell of flash memory, improves the performance of the memory cell of the flash memory forming, and improves program rate.
For addressing the above problem, the invention provides a kind of formation method of memory cell of flash memory, comprise: Semiconductor substrate is provided, in described Semiconductor substrate, there are some fleet plough groove isolation structures, semiconductor substrate surface tool second medium layer between described adjacent fleet plough groove isolation structure and the floating gate layer on second medium layer surface, the sidewall of described fleet plough groove isolation structure and floating gate layer and top surface have first medium layer, between the first medium layer on described adjacent floating gate layer surface, have groove; Form the control grid layer of filling full described groove on described first medium layer surface; After forming described control grid layer, carry out thermal anneal process; After described thermal anneal process, remove the control grid layer higher than described first medium layer surface.
Optionally, the gas of described thermal anneal process comprises one or both mixing in nitrogen dioxide and nitric oxide.
Optionally, the gas of described thermal anneal process also comprises hydrogen.
Optionally, the temperature of described thermal anneal process is 700 degrees Celsius ~ 950 degrees Celsius, and the time is 5 minutes ~ 60 minutes, and flow is 0.05 standard Liter Per Minute ~ 5 standard Liter Per Minute, and air pressure is 0.08 holder ~ 10 holder.
Optionally, the material of described control grid layer is silicon.
Optionally, the formation technique of described control grid layer is chemical vapor deposition method: temperature is 480 ~ 550 degrees Celsius, and reacting gas comprises SiH
4and Si
2h
6in one or both, flow is 0.1 standard Liter Per Minute ~ 5 standard Liter Per Minute, air pressure is 0.08 holder ~ 10 holder.
Optionally, in described control grid layer, there is doping ion.
Optionally, described doping ion is doped into described control grid layer by in-situ doped technique.
Optionally, described doping ion is phosphorus or arsenic, and doping content is 1E19 atom per square centimeter ~ 5E20 atom per square centimeter.
Optionally, the vertical wide ratio of described groove is for being greater than 3.
Optionally, the material of described second medium layer is silica.
Optionally, the composite construction that described first medium layer is silica-silicon-nitride and silicon oxide or the composite construction of silicon-nitride and silicon oxide-silicon-nitride and silicon oxide silicon nitride.
Optionally, the material of described floating gate layer is polysilicon.
Optionally, described removal is CMP (Chemical Mechanical Polishing) process higher than the technique of the control grid layer of described first medium layer.
Optionally, after the control grid layer of removing higher than described first medium layer, form electric interconnection structure at described first medium layer and control grid layer surface.
Compared with prior art, technical scheme of the present invention has the following advantages:
Form first medium layer on floating gate layer surface, and there is groove between the first medium layer on adjacent floating gate layer surface; After described first medium layer surface forms the control grid layer of filling full described groove, carry out thermal anneal process; Described thermal anneal process can make the lattice of described control grid layer rearrange, thereby eliminates the space of control grid layer that is positioned at described groove, and it is even described in making, to state the material of control grid layer; First, it is vertical wide when excessive when the groove between the first medium layer on described adjacent floating gate layer surface that described thermal anneal process has been avoided, and makes to have in formed control grid layer the problem in space, and then improved the program rate of the memory cell of the flash memory forming; Secondly, the material of the control grid layer after thermal annealing is more even, thereby makes the memory cell performance of formed flash memory more stable.
Further, the gas of described thermal anneal process is that one or both in nitrogen dioxide and nitric oxide mix, and temperature is 700 degrees Celsius ~ 950 degrees Celsius, and air pressure is 0.08 holder ~ 10 holder; The oxygen content gas of described thermal anneal process is lower, has avoided making described control grid layer to be oxidized in thermal anneal process; Meanwhile, described nitrogen dioxide or nitric oxide can promote described control grid layer to carry out the permutatation of lattice, are conducive to eliminate space; Secondly, the temperature of described thermal annealing is lower, and air pressure is lower, can further avoid described control grid layer to be oxidized in the technique of thermal annealing, makes the good quality of formed control grid layer.
Accompanying drawing explanation
Fig. 1 to Fig. 3 is the cross-sectional view of the forming process of the memory cell of the flash memory of prior art;
Fig. 4 to Fig. 8 is the cross-sectional view in the forming process of memory cell of the flash memory described in embodiments of the invention.
Embodiment
As stated in the Background Art, the memory cell poor-performing of the flash memory that prior art forms, program speed is lower.
The present inventor finds through research, and in order to meet the integrated demand of integrated circuit and semiconductor device, the characteristic size of the memory cell of flash memory reduces continuing.Please continue to refer to Fig. 2, due to reducing of the size of semiconductor device, also corresponding reducing of the distance between adjacent floating gate layer 103; Meanwhile, the performance of flash memory cell in order to guarantee, the thickness of described floating gate layer 103 can not too reduce, to guarantee that described floating gate layer 103 has enough charge storage.But the distance between adjacent floating gate layer 103 reduces, and the thickness of described floating gate layer 103 is when constant, can cause the vertical wide than excessive of the groove that forms between adjacent floating gate layer 103; Even after described floating gate layer 103 and fleet plough groove isolation structure 101 surface formation dielectric layers 104, the groove between the dielectric layer 104 on adjacent floating gate layer 103 surfaces still has larger vertical wide ratio; When adopting depositing operation during at the surperficial formation control grid of described dielectric layer 104 layer 105, described in there is excessive vertical wide ratio groove easily make polycrystalline silicon material be difficult to fill, then make to form space in the control grid layer 105 in described groove.Because charge carrier cannot be passed through in described gap, thereby cause the program rate of the memory cell of formed flash memory to decline.
Further study through the present inventor, form first medium layer on floating gate layer surface, and after the formation control grid layer of described first medium layer surface, carry out thermal anneal process, the lattice of described control grid layer is rearranged, thereby eliminate the space in the control grid layer forming in the groove between the first medium layer on adjacent floating gate layer surface, and it is even described in making, to state the material of control grid layer; Avoid because the groove between the first medium layer on described adjacent floating gate layer surface is vertical wide than the excessive problem that makes to have in formed control grid layer space, and then improved the program rate of the memory cell of the flash memory forming; And the material of control grid layer after thermal annealing is more even, thereby make the memory cell performance of formed flash memory more stable.
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, below in conjunction with accompanying drawing, the specific embodiment of the present invention is described in detail.
As shown in Fig. 4 to Fig. 8, it is the cross-sectional view in the forming process of memory cell of the flash memory described in embodiments of the invention.
Please refer to Fig. 4, Semiconductor substrate 200 is provided, in described Semiconductor substrate 200, have some fleet plough groove isolation structures 201, Semiconductor substrate 200 surfaces between described adjacent fleet plough groove isolation structure 201 have second medium layer 202, and described second medium layer 202 surface have floating gate layer 203.
Described Semiconductor substrate 200 is used to subsequent technique that workbench is provided; Described Semiconductor substrate 300 is silicon substrate, silicon-Germanium substrate, silicon carbide substrates, silicon-on-insulator (SOI) substrate, germanium on insulator (GOI) substrate, glass substrate or III-V compounds of group substrate (such as silicon nitride or GaAs etc.).
The material of described fleet plough groove isolation structure 201 is silica, forms technique and is well known to those skilled in the art, and therefore not to repeat here; Between described adjacent fleet plough groove isolation structure 201, be used to form the memory cell of single flash memory.
The material of described second medium layer 202 is silica, and formation technique is thermal oxidation technology, or adopts the etching technics after depositing operation and depositing operation to form; Described second medium layer 202 is for the tunnel oxide of the memory cell as flash memory, charge carrier can be realized the migration between Semiconductor substrate 200 and floating gate layer 203 by second medium layer 202 described in tunnelling, thereby reaches the object of wiping, storing or programming.
The material of described floating gate layer 203 is polysilicon, and described floating gate layer 203 is formed by the etching technics after depositing operation and depositing operation; Described floating gate layer 203 can capture or lose electric charge executing under biased state, thereby makes the memory cell of flash memory reach the object of wiping, storing or programming.
In one embodiment, the formation technique of described fleet plough groove isolation structure 201, second medium layer 202 and floating gate layer 203 is: at Semiconductor substrate 200 surface deposition second medium films; At described second medium film surface deposition floating boom film; Floating boom film and second medium film described in etched portions, form some discrete second medium layers 202 and floating gate layer 203 on described Semiconductor substrate 200 surfaces; Take described second medium layer 202 and floating gate layer 203 as mask, adopt Semiconductor substrate described in the dry etch process etching of anisotropic, the interior formation groove of Semiconductor substrate 200 between adjacent second medium layer 202 and floating gate layer 203; In described groove, fill full insulating material, form fleet plough groove isolation structure 201.
In another embodiment, the formation technique of described fleet plough groove isolation structure 201, second medium layer 202 and floating gate layer 203 is: in Semiconductor substrate, form some groove isolation constructions 201; Adopt thermal oxidation technology or depositing operation to form second medium film at described semiconductor substrate surface; Form floating boom film at described second medium film surface; Floating boom film and second medium film described in etched portions, until expose described fleet plough groove isolation structure, form second medium layer 202 and floating gate layer 203 on described Semiconductor substrate 200 surfaces.
Please refer to Fig. 5, at described fleet plough groove isolation structure 201, Semiconductor substrate 200, floating gate layer 203 and second medium layer 202 surface coverage first medium layer 204, between the first medium layer 204 on described adjacent floating gate layer 203 surfaces, there is groove 205.
The composite construction that described first medium layer 204 is silica-silicon-nitride and silicon oxide or the composite construction of silicon-nitride and silicon oxide-silicon-nitride and silicon oxide silicon nitride; The formation technique of described first medium layer is depositing operation, preferably chemical vapor deposition method; Described first medium layer 204 is for isolating the control grid layer of described floating gate layer 203 and follow-up formation.
Because the dielectric constant of silicon nitride is higher than silica, therefore, in the time that silicon nitride and silica have identical electrical thickness, the physical thickness of silicon nitride is thicker than silica; And then when in the identical situation of electrical thickness, because the physical thickness of silicon nitride is thicker, therefore the electric isolating effect of silicon nitride is better; Especially integrated along with integrated circuit or semiconductor device, the size of the memory cell of the flash memory of required formation continues to dwindle, and pure silica material cannot meet the electric isolation requirement between floating gate layer 203 and the control grid layer of follow-up formation; Therefore, need to form the first medium layer 204 of the composite construction of silica-silicon-nitride and silicon oxide, to strengthen the electricity isolation between floating gate layer 203 and control grid layer.
In the present embodiment, the composite construction that described first medium layer 204 is silica-silicon-nitride and silicon oxide or the composite construction of silicon-nitride and silicon oxide-silicon-nitride and silicon oxide silicon nitride; Wherein, described silicon nitride can not increase the electrical thickness of first medium layer 204 in the case of guaranteeing, increases the physical thickness of described first medium layer 204, produces electric leakage to prevent charge carrier from diffusion occurring between floating gate layer 203 and control gate; Meanwhile, because electrical thickness does not change, can guarantee that the parameter such as electric field strength or operating voltage in the memory cell of formed flash memory can meet process requirements; In addition, the silica that is positioned at described silicon nitride upper surface or lower surface can avoid the thickness of described first medium layer 204 blocked up, makes the thickness of described first medium layer 204 in the scope of technique license; Therefore,, in the time of the composite construction of described first medium layer 204 composite construction that is silica-silicon-nitride and silicon oxide or silicon-nitride and silicon oxide-silicon-nitride and silicon oxide silicon nitride, the performance of the memory cell of the flash memory forming is more stable.
In addition, in the present embodiment, because described second medium layer 202 and floating gate layer 204 are formed at Semiconductor substrate 200 surfaces between adjacent fleet plough groove isolation structure, therefore adjacent floating gate layer 204, second medium layer 202 form opening with fleet plough groove isolation structure 201; Again because the thickness of formed first medium layer 204 is limited, unsuitable blocked up, even if therefore, after described fleet plough groove isolation structure 201, floating gate layer 203 and second medium layer 202 surface coverage first medium layer 204, between the first medium layer 204 between adjacent floating gate layer 203, surface still forms groove 205; The width dimensions of described groove 205 is subject to the distance limit between adjacent floating gate layer 203, and the degree of depth of described groove 205 is subject to the thickness limits of described floating gate layer 203; But, along with the size of semiconductor device is constantly dwindled, the distance between adjacent floating gate layer 203 also constantly reduces, but the thickness of described floating gate layer 203 can not correspondingly reduce, to guarantee that described floating gate layer 203 has enough charge storage, makes formed flush memory device have good performance; Therefore, cause the vertical wide than excessive of described groove 205, in the scope that is greater than 3; Described groove 205 vertical wide compared conference and caused follow-uply in the time of the interior filling control grid layer 206 of described groove 205, formed space in the control grid layer in described groove, made formed control grid layer quality bad, the performance of the flush memory device that impact forms.
Please refer to Fig. 6, form and fill full described groove 205(as shown in Figure 5 on described first medium layer 204 surface) control grid layer 206.
The material of described control grid layer 206 is silicon; The formation technique of described control grid layer 206 is chemical vapor deposition method, and technological parameter comprises: temperature is 480 ~ 550 degrees Celsius, and reacting gas comprises SiH
4and Si
2h
6in one or both mix, flow is 0.1 standard Liter Per Minute ~ 5 standard Liter Per Minute, air pressure is 0.08 holder ~ 10 holder.
Due to the size reduction along with flush memory device, cause the vertical wide than excessive of described groove 205, in the time adopting described chemical vapor deposition method to form the control grid layer 206 of filling full described groove 205 on described first medium layer 204 surface, easily cause and be positioned at the material that described groove 205 is difficult to fill described control grid layer 206, cause the control grid layer 206 being formed in described groove 205 to produce space 210, then cause formed flush memory device performance bad.
In one embodiment, in described control grid layer 206, there is doping ion, the ion adulterating is doped in described control grid layer 206 by in-situ doped technique or ion implantation technology, and the ion concentration of adulterating is 1E19 atom per square centimeter ~ 5E20 atom per square centimeter; Preferably, described doping ion adulterates by in-situ doped technique, the ion that can adulterate in formation control grid layer 206, the few processing step of letter; Dopant is preferably N-type ion, comprises phosphorus or arsenic, and described N-type ion can promote the migration of electronics in control grid layer 206, thereby improves the program rate of the flush memory device that forms.
Please refer to Fig. 7, after forming described control grid layer 206, carry out thermal anneal process.
Due to adopt chemical vapor deposition method be formed at groove 205(as shown in Figure 5) in the interior easy generation space 210(of control grid layer 206 as shown in Figure 6), therefore need to remove described space 210 by described thermal anneal process, to improve the quality of described control grid layer 206, improve the program rate of the flush memory device forming.
The gas of described thermal anneal process comprises one or both mixing in nitrogen dioxide and nitric oxide; The temperature of described thermal anneal process is 700 degrees Celsius ~ 950 degrees Celsius, and the time is 5 minutes ~ 60 minutes, and flow is 0.05 standard Liter Per Minute ~ 5 standard Liter Per Minute, and air pressure is 0.08 holder ~ 10 holder.
Described thermal anneal process is by making the crystal lattice rearrangement row of described control grid layer 206, to remove the space 210 in described control grid layer 206; The present inventor is through research discovery, and oxygen, nitrogen dioxide or nitric oxide all can promote that the lattice of the silicon materials of described control gate 206 rearranges, and reaches the object of removing space 210; But oxygen, in thermal anneal process process, easily causes the oxidation of silicon materials and forms silica, causes control grid layer 206 to insulate, and cannot be used for flush memory device; And described nitrogen dioxide or nitric oxide production oxygen content are lower, in making the silicon materials crystal lattice rearrangement row of described control grid layer 206, can not cause the oxidation of described control grid layer 206, can reach the object of removing space 210, can not pollute again described control grid layer 206.
Secondly, the temperature of described thermal annealing is 700 degrees Celsius ~ 950 degrees Celsius, and air pressure is 0.08 holder ~ 10 holder, and its temperature and air pressure are all lower, can further be suppressed at the oxidation in thermal anneal process process; In the space of removing in described control gate ability 206, avoid described control grid layer 206 to be polluted, thereby made the function admirable of formed flush memory device.
In another embodiment, the gas of described thermal anneal process also comprises hydrogen, can further promote the permutatation of lattice, and for disperseing thermal annealing gas, makes the effect of thermal anneal process more abundant.
Please refer to Fig. 8, after described thermal anneal process, remove the control grid layer 206 higher than described first medium layer 204 surface, until expose described first medium layer 204.
Described removal is CMP (Chemical Mechanical Polishing) process higher than the technique of the control grid layer 206 of first medium layer 204, and polishing is until expose described first medium layer 204; After the control grid layer 206 of removing higher than described first medium layer 204, form electric interconnection structure (not shown) at described first medium layer 204 and control grid layer 206 surfaces; In the present embodiment, the material of described electric interconnection structure is polysilicon.
It should be noted that, forming before described electric interconnection structure, the both sides that do not cover described first medium layer 204 and control grid layer 206 at described floating gate layer 203 and second medium layer 202 form side wall (not shown); Take described first medium layer 204 and side wall as mask, at Semiconductor substrate 200 interior formation source region and the drain region (not shown) of described floating gate layer 206 both sides, and form metal silicide layer (not shown) in described source region and surface, drain region; Afterwards, form the conductive plunger (not shown) of the metal silicide layer, floating gate layer 203 and the Semiconductor substrate 200 that connect described source region and surface, drain region.The described electric interconnection structure that is formed at described first medium layer 204 and control grid layer 206 surfaces not only can be electrically connected described control grid layer, can also be electrically connected with described conductive plunger, applies bias voltage with the flush memory device of realizing being formed.
In the formation method of the memory cell of the flash memory of the present embodiment, after first medium layer 204 surface form the control grid layer 206 of filling full described groove 205, adopt thermal anneal process to remove the space 210 in described control grid layer 206, thereby improve the quality of the control grid layer forming, the program rate of the memory cell of the flash memory being formed to improve; And the gas of described thermal anneal process comprises nitrogen dioxide or nitric oxide, its oxygen content is low, has avoided described control grid layer 206 to be oxidized in the process of thermal annealing and contaminated; In addition, temperature and the air pressure of described thermal anneal process are lower, have further suppressed the oxidation of described control grid layer 206 in thermal anneal process process, can further improve the quality of the control grid layer forming.
In sum, form first medium layer on floating gate layer surface, and there is groove between the first medium layer on adjacent floating gate layer surface; After described first medium layer surface forms the control grid layer of filling full described groove, carry out thermal anneal process; Described thermal anneal process can make the lattice of described control grid layer rearrange, thereby eliminates the space of control grid layer that is positioned at described groove, and it is even described in making, to state the material of control grid layer; First, it is vertical wide when excessive when the groove between the first medium layer on described adjacent floating gate layer surface that described thermal anneal process has been avoided, and makes to have in formed control grid layer the problem in space, and then improved the program rate of the memory cell of the flash memory forming; Secondly, the material of the control grid layer after thermal annealing is more even, thereby makes the memory cell performance of formed flash memory more stable.
Further, the gas of described thermal anneal process is that one or both in nitrogen dioxide and nitric oxide mix, and temperature is 700 degrees Celsius ~ 950 degrees Celsius, and air pressure is 0.08 holder ~ 10 holder; The oxygen content gas of described thermal anneal process is lower, has avoided making described control grid layer to be oxidized in thermal anneal process; Meanwhile, described nitrogen dioxide or nitric oxide can promote described control grid layer to carry out the permutatation of lattice, are conducive to eliminate space; Secondly, the temperature of described thermal annealing is lower, and air pressure is lower, can further avoid described control grid layer to be oxidized in the technique of thermal annealing, makes the good quality of formed control grid layer.
Although the present invention with preferred embodiment openly as above; but it is not for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can utilize method and the technology contents of above-mentioned announcement to make possible variation and modification to technical solution of the present invention; therefore; every content that does not depart from technical solution of the present invention; any simple modification, equivalent variations and the modification above embodiment done according to technical spirit of the present invention, all belong to the protection range of technical solution of the present invention.
Claims (15)
1. a formation method for the memory cell of flash memory, is characterized in that, comprising:
Semiconductor substrate is provided, in described Semiconductor substrate, there are some fleet plough groove isolation structures, semiconductor substrate surface tool second medium layer between described adjacent fleet plough groove isolation structure and the floating gate layer on second medium layer surface, the sidewall of described fleet plough groove isolation structure and floating gate layer and top surface have first medium layer, between the first medium layer on described adjacent floating gate layer surface, have groove;
Form the control grid layer of filling full described groove on described first medium layer surface;
After forming described control grid layer, carry out thermal anneal process;
After described thermal anneal process, remove the control grid layer higher than described first medium layer surface.
2. the formation method of the memory cell of flash memory as claimed in claim 1, is characterized in that, the gas of described thermal anneal process comprises one or both mixing in nitrogen dioxide and nitric oxide.
3. the formation method of the memory cell of flash memory as claimed in claim 1, is characterized in that, the gas of described thermal anneal process also comprises hydrogen.
4. the formation method of the memory cell of flash memory as claimed in claim 1, it is characterized in that, the temperature of described thermal anneal process is 700 degrees Celsius ~ 950 degrees Celsius, and the time is 5 minutes ~ 60 minutes, flow is 0.05 standard Liter Per Minute ~ 5 standard Liter Per Minute, and air pressure is 0.08 holder ~ 10 holder.
5. the formation method of the memory cell of flash memory as claimed in claim 1, is characterized in that, the material of described control grid layer is silicon.
6. the formation method of the memory cell of flash memory as claimed in claim 5, is characterized in that, the formation technique of described control grid layer is chemical vapor deposition method: temperature is 480 ~ 550 degrees Celsius, and reacting gas comprises SiH
4and Si
2h
6in one or both, flow is 0.1 standard Liter Per Minute ~ 5 standard Liter Per Minute, air pressure is 0.08 holder ~ 10 holder.
7. the formation method of the memory cell of flash memory as claimed in claim 5, is characterized in that in described control grid layer, having doping ion.
8. the formation method of the memory cell of flash memory as claimed in claim 7, is characterized in that, described doping ion is doped into described control grid layer by in-situ doped technique.
9. the formation method of the memory cell of flash memory as claimed in claim 7, is characterized in that, described doping ion is phosphorus or arsenic, and doping content is 1E19 atom per square centimeter ~ 5E20 atom per square centimeter.
10. the formation method of the memory cell of flash memory as claimed in claim 1, is characterized in that, the vertical wide ratio of described groove is for being greater than 3.
The 11. formation methods of the memory cell of flash memory as claimed in claim 1, is characterized in that, the material of described second medium layer is silica.
The 12. formation methods of the memory cell of flash memory as claimed in claim 1, is characterized in that the composite construction of the composite construction that described first medium layer is silica-silicon-nitride and silicon oxide or silicon-nitride and silicon oxide-silicon-nitride and silicon oxide silicon nitride.
The 13. formation methods of the memory cell of flash memory as claimed in claim 1, is characterized in that, the material of described floating gate layer is polysilicon.
The 14. formation methods of the memory cell of flash memory as claimed in claim 1, is characterized in that, described removal is CMP (Chemical Mechanical Polishing) process higher than the technique of the control grid layer of described first medium layer.
The 15. formation methods of the memory cell of flash memory as claimed in claim 1, is characterized in that, after the control grid layer of removing higher than described first medium layer, form electric interconnection structure at described first medium layer and control grid layer surface.
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| CN104733433B (en) * | 2015-03-24 | 2019-06-25 | 上海新储集成电路有限公司 | A kind of structure and method for realizing local interlinkage |
| CN111968982A (en) * | 2020-10-20 | 2020-11-20 | 晶芯成(北京)科技有限公司 | Nor flash memory structure and manufacturing method thereof |
| CN111968982B (en) * | 2020-10-20 | 2021-01-01 | 晶芯成(北京)科技有限公司 | Nor flash memory structure and manufacturing method thereof |
| CN112908856A (en) * | 2021-03-09 | 2021-06-04 | 上海华虹宏力半导体制造有限公司 | Preparation method of flash memory device |
| CN112908856B (en) * | 2021-03-09 | 2024-05-14 | 上海华虹宏力半导体制造有限公司 | Method for manufacturing flash memory device |
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