CN103000534A - Manufacture method of groove-type P-type metal oxide semiconductor power transistor - Google Patents
Manufacture method of groove-type P-type metal oxide semiconductor power transistor Download PDFInfo
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- CN103000534A CN103000534A CN2012105769143A CN201210576914A CN103000534A CN 103000534 A CN103000534 A CN 103000534A CN 2012105769143 A CN2012105769143 A CN 2012105769143A CN 201210576914 A CN201210576914 A CN 201210576914A CN 103000534 A CN103000534 A CN 103000534A
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Abstract
A manufacture method of a groove-type P-type metal oxide semiconductor power transistor includes a lamination forming step that an epitaxial layer, a silicon oxide layer, a silicon nitride layer and a hard mask layer are sequentially formed on a substrate, a groove etching step that a pattern of the hard mask layer is formed and the hard mask layer with the formed pattern is utilized to form a groove in an lamination layer of the silicon nitride layer, the silicon oxide layer and the epitaxial layer, a hard mask removing step that the hard mask layer is removed by wet etching, a sacrifice oxidizing layer forming step that a sacrifice oxidizing layer is formed on the lateral wall and at the bottom in the groove, a sacrifice oxidizing layer removing step that the sacrifice oxidizing layer is removed from the lateral wall and the bottom in the groove, a grid oxidizing layer forming step that a grid oxidizing layer is formed on the lateral wall and at the bottom in the groove, a polycrystalline silicon sedimenting step that a polycrystalline silicon layer is respectively sedimented on the surface of the silicon nitride layer and in the groove and a polycrystalline silicon etching and grinding step that the polycrystalline silicon layer is etched and subjected to chemical mechanical grinding only with polycrystalline silicon retained in the groove.
Description
Technical field
The present invention relates to field of semiconductor manufacture, more particularly, the present invention relates to a kind of plough groove type P-type mos power crystal pipe manufacturing method.
Background technology
Groove-shaped metal oxide semiconductor transistor (trench MOS) is as a kind of novel vertical structure device, be to grow up on the basis of VDMOS (vertical double diffusion Metal-Oxide Semiconductor field-effect transistor), both all belong to high cellular density device.But this structure is compared with the former many feature performance benefits are arranged: such as lower conducting resistance, low grid leak charge density, thereby low conducting and switching loss and fast switching speed are arranged.Because the raceway groove of groove-shaped metal-oxide semiconductor (MOS) is vertical, so can further improve its gully density, reduce chip size simultaneously.
Fig. 1 is the cross-sectional view of conventional groove type metal oxide semiconductor power transistor.As shown in Figure 1, conventional groove type metal oxide semiconductor power transistor comprise Semiconductor substrate 100, be arranged on drain region 101 on the Semiconductor substrate 100,101 drift regions 102 that form, the well region 103 that forms in the drift region and the source region 104 that forms at well region 103 in the drain region.Wherein, as shown in Figure 1, grid structure comprises the grid oxic horizon 106 that is formed on the trenched side-wall and the grid polycrystalline silicon 105 of having filled groove.
Take the groove-shaped metal-oxide semiconductor (MOS) power transistor of P type as example, highly doped P type substrate is adopted in drain region 101.And epitaxial growth thereon has the P type doping ion of low concentration as drift region 102.Well region 103 can be injected with N-type doping ion.Source region 104 can be injected with P type doping ion.
Fig. 2 to Fig. 7 schematically shows the plough groove type P-type mos power crystal pipe manufacturing method according to prior art.As shown in the figure, on the heavily doped substrate 1 of P type, form successively the lightly doped epitaxial loayer 2 of P type and hard mask layer 3 (for example silicon dioxide layer), as shown in Figure 2; Form the pattern of hard mask layer 3 and utilize the hard mask layer 3 that forms pattern in epitaxial loayer 2, to form groove, as shown in Figure 3; Wet etching is removed hard mask layer 3, and forms sacrificial oxide layer on the surface of epitaxial loayer 2 and groove thereof; Wet etching is removed sacrificial oxide layer, forms grid oxic horizon 4 on the surface of epitaxial loayer and groove thereof, as shown in Figure 4; Form the polysilicon layer 5 that the P type mixes at grid oxic horizon 4, described polysilicon layer 5 has been filled groove, as shown in Figure 5; Polysilicon layer 5 is carried out etching, as shown in Figure 6; Only stay polysilicon in the groove thereby polysilicon layer 5 is carried out cmp, and keep the part gate oxide of epi-layer surface, as shown in Figure 7.
But there is a defective in Fig. 2 to prior art shown in Figure 7, that is, when polysilicon layer 5 was carried out cmp, the grinding rate of the polysilicon layer 5 that the P type mixes was greater than the polysilicon of N-type doping; If grid oxic horizon 4 too thin (for example 250A), usually then grind can the effects on surface gate oxide and surperficial gate oxide under the epitaxial loayer injury, thereby cause the electric leakage of grid source, the zone easier generation of this situation in the middle of wafer; Enough just above-mentioned damage can not appear when thick (for example 450A) at grid oxic horizon 4 only.
Therefore, hope can provide a kind of technical scheme that can prevent still that when grid oxic horizon is thinner above-mentioned damage from occurring.
Summary of the invention
Technical problem to be solved by this invention is for having defects in the prior art, a kind of plough groove type P-type mos power crystal pipe manufacturing method that can still can prevent from damaging appearance when grid oxic horizon is thinner being provided.
In order to realize above-mentioned technical purpose, according to a first aspect of the invention, a kind of plough groove type P-type mos power crystal pipe manufacturing method is provided, and it comprises: lamination forms step, is used for forming successively on substrate epitaxial loayer, silicon dioxide layer, silicon nitride layer and hard mask layer; The groove etch step is used to form the pattern of hard mask layer and utilizes the hard mask layer that forms pattern to form groove in the lamination of silicon nitride layer, silicon dioxide layer and epitaxial loayer; Hard mask is removed step, is used for removing hard mask layer by wet etching; Sacrificial oxide layer forms and removes step, and the sidewall and the bottom that are used in groove form, and remove sacrificial oxide layer by wet etching; Grid oxic horizon forms step, and grid oxic horizon is formed on the sidewall and the bottom that are used in groove; The polysilicon deposition step is used for deposit spathic silicon layer on the surface of silicon nitride layer and in the groove; Polysilicon layer etching and grinding steps are used for polysilicon layer is carried out etching, only stay polysilicon in the groove thereby then polysilicon layer is carried out cmp.
Preferably, polysilicon layer is that the P type mixes.
Preferably, substrate is that the P type is heavily doped.
Preferably, epitaxial loayer is that the P type is lightly doped.
Preferably, hard mask layer is silicon dioxide.
In the plough groove type P-type mos power crystal pipe manufacturing method according to the embodiment of the invention, silicon nitride layer 40 can guarantee that the silicon dioxide layer 30 on surface keeps thickness constant at removal hard mask layer and sacrificial oxide layer in the wet etching process; In carrying out chemical mechanical planarization process; because the silicon nitride layer 40 on surface can be done thinlyyer; so will be easy to be polished; grinding is parked on the thicker silicon dioxide layer 30 in surface (shown in the arrow of Figure 15); thereby effectively protect the epitaxial loayer below it; prevent the too fast epitaxial loayer injury to thinner grid oxic horizon below of grinding rate of P type polysilicon, prevented the electric leakage of grid source.
Description of drawings
By reference to the accompanying drawings, and by with reference to following detailed description, will more easily to the present invention more complete understanding be arranged and more easily understand its advantage of following and feature, wherein:
Fig. 1 schematically shows the structure of groove-shaped metal-oxide semiconductor (MOS) power transistor.
Fig. 2 to Fig. 7 schematically shows the step according to the plough groove type P-type mos power crystal pipe manufacturing method of prior art.
The lamination that Fig. 8 schematically shows according to the plough groove type P-type mos power crystal pipe manufacturing method of the embodiment of the invention forms step.
Fig. 9 schematically shows the groove etch step according to the plough groove type P-type mos power crystal pipe manufacturing method of the embodiment of the invention.
Figure 10 schematically shows according to the hard mask of the plough groove type P-type mos power crystal pipe manufacturing method of the embodiment of the invention and removes step.
The sacrificial oxide layer that Figure 11 schematically shows according to the plough groove type P-type mos power crystal pipe manufacturing method of the embodiment of the invention forms step.
Figure 12 schematically shows according to the sacrificial oxide layer of the plough groove type P-type mos power crystal pipe manufacturing method of the embodiment of the invention and removes step.
The grid oxic horizon that Figure 13 schematically shows according to the plough groove type P-type mos power crystal pipe manufacturing method of the embodiment of the invention forms step.
Figure 14 schematically shows the polysilicon deposition step according to the plough groove type P-type mos power crystal pipe manufacturing method of the embodiment of the invention.
Figure 15 schematically shows etching polysilicon and the grinding steps according to the plough groove type P-type mos power crystal pipe manufacturing method of the embodiment of the invention.
Need to prove that accompanying drawing is used for explanation the present invention, and unrestricted the present invention.Notice that the accompanying drawing of expression structure may not be to draw in proportion.And in the accompanying drawing, identical or similar element indicates identical or similar label.
Embodiment
In order to make content of the present invention more clear and understandable, below in conjunction with specific embodiments and the drawings content of the present invention is described in detail.
Fig. 8 to Figure 14 schematically shows the plough groove type P-type mos power crystal pipe manufacturing method according to the embodiment of the invention.
, comprise according to the plough groove type P-type mos power crystal pipe manufacturing method of the embodiment of the invention to shown in Figure 14 such as Fig. 8:
Lamination forms step, is used for forming successively the lightly doped epitaxial loayer 20 of P type, silicon dioxide layer 30, silicon nitride layer 40 and hard mask layer 50 (for example silicon dioxide) on the heavily doped substrate 10 of P type, as shown in Figure 8; Wherein silicon dioxide layer 30 thickness are thicker, about 350-500A; The thinner thickness of silicon nitride layer 40 is about 40-100A.
The groove etch step is used to form the pattern of hard mask layer 50 and utilizes the hard mask layer 50 that forms pattern to form groove in the lamination of silicon nitride layer 40, silicon dioxide layer 30 and the lightly doped epitaxial loayer 20 of P type, as shown in Figure 9;
Hard mask is removed step, is used for removing hard mask layer 50 by wet etching, wherein might form the recess of etching on the sidewall of the silicon dioxide layer in groove 30, as shown in figure 10;
The formation of sacrificial oxide layer and removal step, sacrificial oxide layer 80 is formed on the sidewall and the bottom that are used in groove, as shown in figure 11, and removes sacrificial oxide layer 80 with wet etching, wherein also can form the recess of etching on the sidewall of the silicon dioxide layer in groove 30, as shown in figure 12.
Grid oxic horizon forms step, and grid oxic horizon 70 is formed on the sidewall and the bottom that are used in groove, as shown in figure 13;
The polysilicon deposition step is used for the polysilicon layer 60 that deposition P type mixes on the surface of silicon nitride layer 40 and in the groove, as shown in figure 14.
After this, can carry out etching to polysilicon layer 60, thus then to polysilicon layer 60 carry out cmp only stay in the groove to polysilicon.But, unlike the prior art, in the plough groove type P-type mos power crystal pipe manufacturing method according to the embodiment of the invention, silicon nitride layer 40 can guarantee that the silicon dioxide layer 30 on surface keeps thickness constant in the wet etching process of removing hard mask layer and sacrificial oxide layer; In carrying out chemical mechanical planarization process; because the silicon nitride layer 40 on surface can be done thinlyyer; so will be easy to be polished; grinding is parked on the thicker silicon dioxide layer 30 in surface (shown in the arrow of Figure 15); thereby effectively protect the epitaxial loayer below it; the grinding rate that has prevented P type polysilicon is too fast, to the epitaxial loayer injury of thinner grid oxic horizon below, thereby prevents the electric leakage of grid source.
Be understandable that although the present invention with the preferred embodiment disclosure as above, yet above-described embodiment is not to limit the present invention.For any those of ordinary skill in the art, do not breaking away from the technical solution of the present invention scope situation, all can utilize the technology contents of above-mentioned announcement that technical solution of the present invention is made many possible changes and modification, or be revised as the equivalent embodiment of equivalent variations.Therefore, every content that does not break away from technical solution of the present invention according to any simple modification, equivalent variations and the modification that technical spirit of the present invention is done above embodiment, all still belongs in the scope of technical solution of the present invention protection.
Claims (5)
1. plough groove type P-type mos power crystal pipe manufacturing method is characterized in that comprising:
Lamination forms step, is used for forming successively on substrate epitaxial loayer, silicon dioxide layer, silicon nitride layer and hard mask layer;
The groove etch step is used to form the pattern of hard mask layer and utilizes the hard mask layer that forms pattern to form groove in the lamination of silicon nitride layer, silicon dioxide layer and epitaxial loayer;
Hard mask is removed step, is used for removing hard mask layer by wet etching;
Sacrificial oxide layer forms step, and sacrificial oxide layer is formed on the sidewall and the bottom that are used in groove;
The removal step of sacrificial oxide layer, sacrificial oxide layer is removed in the sidewall and the bottom that are used in groove;
Grid oxic horizon forms step, and grid oxic horizon is formed on the sidewall and the bottom that are used in groove;
The polysilicon deposition step is used for deposit spathic silicon layer on the surface of silicon nitride layer and in the groove;
Polysilicon layer etching and grinding steps are used for polysilicon layer is carried out etching, only stay polysilicon in the groove thereby then polysilicon layer is carried out cmp.
2. plough groove type P-type mos power crystal pipe manufacturing method according to claim 1 is characterized in that, polysilicon layer is that the P type mixes.
3. plough groove type P-type mos power crystal pipe manufacturing method according to claim 1 and 2 is characterized in that substrate is that the P type is heavily doped.
4. plough groove type P-type mos power crystal pipe manufacturing method according to claim 1 and 2 is characterized in that epitaxial loayer is that the P type is lightly doped.
5. plough groove type P-type mos power crystal pipe manufacturing method according to claim 1 and 2 is characterized in that hard mask layer is silicon dioxide.
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| CN201210576914.3A CN103000534B (en) | 2012-12-26 | 2012-12-26 | Groove-type P-type metal oxide semiconductor power transistor manufacture method |
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| CN201210576914.3A CN103000534B (en) | 2012-12-26 | 2012-12-26 | Groove-type P-type metal oxide semiconductor power transistor manufacture method |
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Cited By (6)
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| CN104752160A (en) * | 2013-12-31 | 2015-07-01 | 苏州同冠微电子有限公司 | Method for etching groove through common polycrystal etching device |
| CN107919271A (en) * | 2017-11-06 | 2018-04-17 | 上海华虹宏力半导体制造有限公司 | The fill method of groove extension |
| CN107946175A (en) * | 2017-11-06 | 2018-04-20 | 上海华虹宏力半导体制造有限公司 | The fill method of groove extension |
| CN110060919A (en) * | 2018-01-18 | 2019-07-26 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor devices and forming method thereof |
| CN111933527A (en) * | 2019-05-13 | 2020-11-13 | 上海先进半导体制造股份有限公司 | Trench IGBT and manufacturing method thereof |
| CN112447507A (en) * | 2019-08-30 | 2021-03-05 | 株洲中车时代半导体有限公司 | GOI test sample wafer manufacturing method for improving trench gate breakdown characteristics |
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| CN102270583A (en) * | 2011-08-26 | 2011-12-07 | 上海宏力半导体制造有限公司 | Trench MOS (Metal Oxide Semiconductor) and forming method thereof |
| CN102280402A (en) * | 2010-06-12 | 2011-12-14 | 上海华虹Nec电子有限公司 | Method for etching and filling deep groove |
| CN102290344A (en) * | 2011-09-01 | 2011-12-21 | 上海宏力半导体制造有限公司 | Trench type MOS (metal oxide semiconductor) tube manufacturing process |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN104752160A (en) * | 2013-12-31 | 2015-07-01 | 苏州同冠微电子有限公司 | Method for etching groove through common polycrystal etching device |
| CN107919271A (en) * | 2017-11-06 | 2018-04-17 | 上海华虹宏力半导体制造有限公司 | The fill method of groove extension |
| CN107946175A (en) * | 2017-11-06 | 2018-04-20 | 上海华虹宏力半导体制造有限公司 | The fill method of groove extension |
| CN107919271B (en) * | 2017-11-06 | 2020-04-14 | 上海华虹宏力半导体制造有限公司 | Filling method for groove epitaxy |
| CN107946175B (en) * | 2017-11-06 | 2020-08-11 | 上海华虹宏力半导体制造有限公司 | Filling method for groove epitaxy |
| CN110060919A (en) * | 2018-01-18 | 2019-07-26 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor devices and forming method thereof |
| CN110060919B (en) * | 2018-01-18 | 2021-08-06 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and method of forming the same |
| CN111933527A (en) * | 2019-05-13 | 2020-11-13 | 上海先进半导体制造股份有限公司 | Trench IGBT and manufacturing method thereof |
| CN112447507A (en) * | 2019-08-30 | 2021-03-05 | 株洲中车时代半导体有限公司 | GOI test sample wafer manufacturing method for improving trench gate breakdown characteristics |
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| CN103000534B (en) | 2017-06-09 |
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