CN103000534B - Groove-type P-type metal oxide semiconductor power transistor manufacture method - Google Patents
Groove-type P-type metal oxide semiconductor power transistor manufacture method Download PDFInfo
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- CN103000534B CN103000534B CN201210576914.3A CN201210576914A CN103000534B CN 103000534 B CN103000534 B CN 103000534B CN 201210576914 A CN201210576914 A CN 201210576914A CN 103000534 B CN103000534 B CN 103000534B
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Abstract
A kind of groove-type P-type metal oxide semiconductor power transistor manufacture method includes：Lamination forming step, sequentially forms epitaxial layer, silicon dioxide layer, silicon nitride layer and hard mask layer on substrate；Recess etch step, forms the pattern of hard mask layer and forms groove in the lamination of silicon nitride layer, silicon dioxide layer and epitaxial layer using the hard mask layer for forming pattern；Hard mask removal step, hard mask layer is removed by wet etching；Sacrificial oxide layer forming step, side wall and bottom in groove form sacrificial oxide layer；Sacrificial oxide layer removal step, side wall and bottom the removal sacrificial oxide layer in groove；Grid oxic horizon forming step, side wall and bottom in groove form grid oxic horizon；Polysiiicon deposition steps, deposit polycrystalline silicon layer on the surface of silicon nitride layer and in groove；Polysilicon layer is etched and grinding steps, and polysilicon layer is performed etching, and cmp is then carried out to polysilicon layer so as to the polysilicon only left in groove.
Description
Technical field
The present invention relates to field of semiconductor manufacture, it is more particularly related to a kind of plough groove type p-type metal oxide
Semiconductor power transistor manufacture method.
Background technology
Trench metal-oxide semiconductor transistor (trench MOS) as a kind of novel vertical structure device, be
Grow up on the basis of VDMOS (vertical double diffused metal-oxide semiconductor field effect transistor), both belong to height
Cellular density device.But the structure has many feature performance benefits compared with the former：As lower conducting resistance, low gate-drain charge are close
Degree, so as to there is low conducting and switching loss and fast switching speed.Simultaneously because the ditch of trench metal-oxide semiconductor
Road is vertical, therefore can further improve its gully density, reduces chip size.
Fig. 1 is the cross-sectional view of conventional groove type metal oxide semiconductor power transistor.As shown in figure 1, traditional ditch
Groove profile metal-oxide semiconductor (MOS) power transistor includes Semiconductor substrate 100, setting drain region on a semiconductor substrate 100
101st, the drift region 102 for being formed on drain region 101, the well region 103 formed on drift region and the source region formed on well region 103
104.Wherein, as shown in figure 1, grid structure includes the grid oxic horizon 106 being formed on trenched side-wall and is filled with groove
Grid polycrystalline silicon 105.
By taking p-type trench metal-oxide semiconductor power transistor as an example, drain region 101 uses highly doped P type substrate.
And epitaxial growth thereon has the p-type Doped ions of low concentration as drift region 102.Well region 103 can be injected with n-type doping from
Son.Source region 104 can be injected with p-type Doped ions.
Fig. 2 to Fig. 7 schematically shows the groove-type P-type metal oxide semiconductor power crystal according to prior art
Pipe manufacturing method.As illustrated, sequentially forming epitaxial layer 2 and hard mask that p-type is lightly doped on the substrate 1 of p-type heavy doping
3 (such as silicon dioxide layer) of layer, as shown in Figure 2；Form the pattern of hard mask layer 3 and existed using the hard mask layer 3 for forming pattern
Groove is formed in epitaxial layer 2, as shown in Figure 3；Wet etching removes hard mask layer 3, and in epitaxial layer 2 and its surface shape of groove
Into sacrificial oxide layer；Wet etching removes sacrificial oxide layer, forms grid oxic horizon 4 on the surface of epitaxial layer and its groove, such as
Shown in Fig. 4；The polysilicon layer 5 of p-type doping is formed on grid oxic horizon 4, the polysilicon layer 5 is filled with groove, such as Fig. 5 institutes
Show；Polysilicon layer 5 is performed etching, as shown in Figure 6；Cmp is carried out to polysilicon layer 5 so as to only leave groove
In polysilicon, and retain the part gate oxide of epi-layer surface, as shown in Figure 7.
But, there is a defect in the prior art shown in Fig. 2 to Fig. 7, i.e. chemical machinery is being carried out to polysilicon layer 5
During grinding, the polysilicon of the grinding rate more than n-type doping of the polysilicon layer 5 of p-type doping；If the too thin (example of grid oxic horizon 4
Such as 250A), then to grind usually cause the epitaxial layer under surface gate oxide and surface gate oxide and damage, so as to cause
Grid source and drain electricity, this situation in the wafer between region be easier occur；It is only sufficiently thick (such as 450A) in grid oxic horizon 4
When be not in just above-mentioned damage.
Accordingly, it is desirable to be able to provide a kind of technical side for being remained to when grid oxic horizon is relatively thin and preventing above-mentioned damage from occurring
Case.
The content of the invention
The technical problems to be solved by the invention are directed to and there is drawbacks described above in the prior art, there is provided one kind can be in grid
Pole oxide layer remains to prevent from damaging the groove-type P-type metal oxide semiconductor power transistor manufacture method for occurring when relatively thin.
In order to realize above-mentioned technical purpose, according to the first aspect of the invention, there is provided a kind of plough groove type p-type metal oxidation
Thing semiconductor power transistor manufacture method, it includes：Lamination forming step, for sequentially forming epitaxial layer, two on substrate
Silicon oxide layer, silicon nitride layer and hard mask layer；Recess etch step, for forming the pattern of hard mask layer and utilizing formation figure
The hard mask layer of case forms groove in the lamination of silicon nitride layer, silicon dioxide layer and epitaxial layer；Hard mask removal step, is used for
Hard mask layer is removed by wet etching；Sacrificial oxide layer is formed and removal step, for side wall and bottom shape in groove
Into, and sacrificial oxide layer is removed by wet etching；Grid oxic horizon forming step, for side wall and bottom shape in groove
Into grid oxic horizon；Polysiiicon deposition steps, for deposit polycrystalline silicon layer on the surface of silicon nitride layer and in groove；Polycrystalline
Silicon layer etch and grinding steps, for being performed etching to polysilicon layer, then polysilicon layer is carried out cmp so as to
Only leave the polysilicon in groove.
Preferably, polysilicon layer is p-type doping.
Preferably, substrate is p-type heavy doping.
Preferably, epitaxial layer is that p-type is lightly doped.
Preferably, hard mask layer is silica.
In groove-type P-type metal oxide semiconductor power transistor manufacture method according to embodiments of the present invention, nitrogen
SiClx layer 40 ensure that the silicon dioxide layer 30 on surface in removal hard mask layer and sacrificial oxide layer during wet etching
Keep thickness constant；In chemical mechanical planarization process is carried out, due to the silicon nitride layer 40 on surface can be made it is relatively thin, so will
It is easy to be milled away, grinding is parked in the thicker silicon dioxide layer 30 in surface (as shown in the arrow of Figure 15), so that effectively
Protection epitaxial layer below, it is therefore prevented that the too fast extension to below relatively thin grid oxic horizon of grinding rate of p-type polysilicon
Layer causes to damage, and prevents grid source and drain electricity.
Brief description of the drawings
With reference to accompanying drawing, and by reference to following detailed description, it will more easily have more complete understanding to the present invention
And its adjoint advantages and features is more easily understood, wherein：
Fig. 1 schematically shows the structure of trench metal-oxide semiconductor power transistor.
Fig. 2 to Fig. 7 schematically shows the groove-type P-type metal oxide semiconductor power crystal according to prior art
The step of pipe manufacturing method.
Fig. 8 schematically shows groove-type P-type metal oxide semiconductor power crystal according to embodiments of the present invention
The lamination forming step of pipe manufacturing method.
Fig. 9 schematically shows groove-type P-type metal oxide semiconductor power crystal according to embodiments of the present invention
The recess etch step of pipe manufacturing method.
Figure 10 schematically shows groove-type P-type metal oxide semiconductor power crystal according to embodiments of the present invention
The hard mask removal step of pipe manufacturing method.
Figure 11 schematically shows groove-type P-type metal oxide semiconductor power crystal according to embodiments of the present invention
The sacrificial oxide layer forming step of pipe manufacturing method.
Figure 12 schematically shows groove-type P-type metal oxide semiconductor power crystal according to embodiments of the present invention
The sacrificial oxide layer removal step of pipe manufacturing method.
Figure 13 schematically shows groove-type P-type metal oxide semiconductor power crystal according to embodiments of the present invention
The grid oxic horizon forming step of pipe manufacturing method.
Figure 14 schematically shows groove-type P-type metal oxide semiconductor power crystal according to embodiments of the present invention
The polysiiicon deposition steps of pipe manufacturing method.
Figure 15 schematically shows groove-type P-type metal oxide semiconductor power crystal according to embodiments of the present invention
The etching polysilicon and grinding steps of pipe manufacturing method.
It should be noted that accompanying drawing is used to illustrate the present invention, it is not intended to limit the present invention.Note, represent that the accompanying drawing of structure can
Can be not necessarily drawn to scale.Also, in accompanying drawing, same or similar element indicates same or similar label.
Specific embodiment
In order that present disclosure is more clear and understandable, with reference to specific embodiments and the drawings to of the invention interior
Appearance is described in detail.
Fig. 8 to Figure 14 schematically shows groove-type P-type metal oxide semiconductor work(according to embodiments of the present invention
Rate transistor fabrication process.
As shown in Fig. 8 to Figure 14, groove-type P-type metal oxide semiconductor power transistor according to embodiments of the present invention
Manufacture method includes：
Lamination forming step, for sequentially forming the epitaxial layer 20, two that p-type is lightly doped on the substrate 10 of p-type heavy doping
Silicon oxide layer 30, silicon nitride layer 40 and hard mask layer 50 (such as silica), as shown in Figure 8；Wherein silicon dioxide layer 30
Thickness is thicker, in 350-500A or so；The thinner thickness of silicon nitride layer 40, in 40-100A or so.
Recess etch step, for forming the pattern of hard mask layer 50 and utilizing the hard mask layer 50 for forming pattern in nitridation
Groove is formed in the lamination of the epitaxial layer 20 that silicon layer 40, silicon dioxide layer 30 and p-type are lightly doped, as shown in Figure 9；
Hard mask removal step, for removing hard mask layer 50 by wet etching, wherein the silica in groove
It is possible to be formed the recess of etching on the side wall of layer 30, as shown in Figure 10；
The formation of sacrificial oxide layer and removal step, sacrificial oxide layer 80 is formed for the side wall in groove and bottom,
As shown in figure 11, and with wet etching sacrificial oxide layer 80 is removed, wherein on the side wall of silicon dioxide layer 30 in groove
The recess of etching can be formed, as shown in figure 12.
Grid oxic horizon forming step, forms grid oxic horizon 70, such as Figure 13 institutes for the side wall in groove and bottom
Show；
Polysiiicon deposition steps, the polysilicon for depositing p-type doping on the surface of silicon nitride layer 40 and in groove
Layer 60, as shown in figure 14.
Hereafter, polysilicon layer 60 can be performed etching, cmp is then carried out to polysilicon layer 60 so as to only
Only leave in groove to polysilicon.But, unlike the prior art, in plough groove type p-type metal according to embodiments of the present invention
In oxide semiconductor power transistor fabrication process, silicon nitride layer 40 ensure that the silicon dioxide layer 30 on surface is hard in removal
Keep thickness constant during the wet etching of mask layer and sacrificial oxide layer；In chemical mechanical planarization process is carried out, due to
The silicon nitride layer 40 on surface can be made relatively thin, so will be easy to be milled away, grinding is parked in the thicker silica in surface
On layer 30 (as shown in the arrow of Figure 15), so as to be effectively protected epitaxial layer below, it is therefore prevented that the grinding speed of p-type polysilicon
Spend soon, the epitaxial layer below relatively thin grid oxic horizon is caused to damage, so as to prevent grid source and drain electricity.
Although it is understood that the present invention is disclosed as above with preferred embodiment, but above-described embodiment and being not used to
Limit the present invention.For any those of ordinary skill in the art, in the case where technical solution of the present invention ambit is not departed from,
Many possible variations and modification are all made to technical solution of the present invention using the technology contents of the disclosure above, or is revised as
With the Equivalent embodiments of change.Therefore, every content without departing from technical solution of the present invention, according to technical spirit pair of the invention
Any simple modification, equivalent variation and modification made for any of the above embodiments, still fall within the scope of technical solution of the present invention protection
It is interior.
Claims (5)
1. a kind of groove-type P-type metal oxide semiconductor power transistor manufacture method, it is characterised in that including：
Lamination forming step, for sequentially forming epitaxial layer, silicon dioxide layer, silicon nitride layer and hard mask layer on substrate；
Recess etch step, for forming the pattern of hard mask layer and using the hard mask layer for forming pattern in silicon nitride layer, two
Groove is formed in the lamination of silicon oxide layer and epitaxial layer；
Hard mask removal step, for removing hard mask layer by wet etching；
Sacrificial oxide layer forming step, sacrificial oxide layer is formed for the side wall in groove and bottom；
The removal step of sacrificial oxide layer, for the side wall in groove and bottom removal sacrificial oxide layer；
Grid oxic horizon forming step, grid oxic horizon is formed for the side wall in groove and bottom；
Polysiiicon deposition steps, for deposit polycrystalline silicon layer on the surface of silicon nitride layer and in groove；
Polysilicon layer is etched and grinding steps, for being performed etching to polysilicon layer, then carries out chemical machinery to polysilicon layer
Grinding is so as to only leave the polysilicon in groove；Grinding stops at silicon dioxide layer.
2. groove-type P-type metal oxide semiconductor power transistor manufacture method according to claim 1, its feature exists
In polysilicon layer is p-type doping.
3. groove-type P-type metal oxide semiconductor power transistor manufacture method according to claim 1 and 2, it is special
Levy and be, substrate is p-type heavy doping.
4. groove-type P-type metal oxide semiconductor power transistor manufacture method according to claim 1 and 2, it is special
Levy and be, epitaxial layer is that p-type is lightly doped.
5. groove-type P-type metal oxide semiconductor power transistor manufacture method according to claim 1 and 2, it is special
Levy and be, hard mask layer is silica.
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| CN104752160A (en) * | 2013-12-31 | 2015-07-01 | 苏州同冠微电子有限公司 | Method for etching groove through common polycrystal etching device |
| CN107919271B (en) * | 2017-11-06 | 2020-04-14 | 上海华虹宏力半导体制造有限公司 | Filling method for groove epitaxy |
| CN107946175B (en) * | 2017-11-06 | 2020-08-11 | 上海华虹宏力半导体制造有限公司 | Filling method for groove epitaxy |
| CN110060919B (en) * | 2018-01-18 | 2021-08-06 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and method of forming the same |
| CN111933527A (en) * | 2019-05-13 | 2020-11-13 | 上海先进半导体制造股份有限公司 | Trench IGBT and manufacturing method thereof |
| CN112447507B (en) * | 2019-08-30 | 2024-06-18 | 株洲中车时代半导体有限公司 | GOI test sample wafer manufacturing method for improving breakdown characteristics of trench gate |
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| US7868394B2 (en) * | 2005-08-09 | 2011-01-11 | United Microelectronics Corp. | Metal-oxide-semiconductor transistor and method of manufacturing the same |
| CN101488521A (en) * | 2008-01-16 | 2009-07-22 | 力士科技股份有限公司 | Trench type MOS transistor structure and manufacturing process thereof |
| CN102263030B (en) * | 2010-05-25 | 2013-04-10 | 北大方正集团有限公司 | Method for manufacturing groove-type power device |
| CN102280402A (en) * | 2010-06-12 | 2011-12-14 | 上海华虹Nec电子有限公司 | Method for etching and filling deep groove |
| CN102270583A (en) * | 2011-08-26 | 2011-12-07 | 上海宏力半导体制造有限公司 | Trench MOS (Metal Oxide Semiconductor) and forming method thereof |
| CN102290344A (en) * | 2011-09-01 | 2011-12-21 | 上海宏力半导体制造有限公司 | Trench type MOS (metal oxide semiconductor) tube manufacturing process |
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