CN104752160A - Method for etching groove through common polycrystal etching device - Google Patents
Method for etching groove through common polycrystal etching device Download PDFInfo
- Publication number
- CN104752160A CN104752160A CN201310750598.1A CN201310750598A CN104752160A CN 104752160 A CN104752160 A CN 104752160A CN 201310750598 A CN201310750598 A CN 201310750598A CN 104752160 A CN104752160 A CN 104752160A
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- CN
- China
- Prior art keywords
- etching
- groove
- hard mask
- sacrificial oxidation
- oxide layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
Abstract
The invention relates to a method for etching a groove through a common polycrystal etching device. The method comprises the steps of (1) performing sacrificial oxidation and depositing a hard mask; (2) photoetching and etching the hard mask; (3) etching the groove and removing photoresist; (4) removing the hard mask and a sacrificial oxidation layer; (5) thermally repairing, and developing the sacrificial oxidation layer; (5) removing the sacrificial oxidation layer, and cleaning; (7) developing gate oxide. According to the method, the step of thermally repairing, and developing the sacrificial oxidation layer is added after the step of removing the hard mask and the sacrificial oxidation layer and is sued for repairing the damage generated in etching; the sacrificial oxidation is performed for smoothening the top and bottom appearances of the groove, and thus the thickness and uniformity of the subsequent gate oxide can be improved. With the adoption of the method, the groove with good appearance, smooth sidewall and smooth non-edge bottom part can be etched through the common polycrystal etching device; the quality and uniformity of the gate oxide can be further ensured; the stability of the product can be greatly improved.
Description
Technical field
The present invention relates to a kind of field of semiconductor manufacture, in particular, the present invention relates to the method utilizing conventional equipment etching groove.
Background technology
In fabrication of semiconductor device, need under many circumstances to etch groove structure, the quality of groove pattern, the round and smooth degree of its top and bottom determine gate oxide growth thickness and uniformity in subsequent technique, but professional etching groove machine is less.
In existing a kind of groove etching method, the concrete steps of etching comprise: step 1 is oxidized and generates sacrificial oxide layer and hard mask, and step 2 photoetching also etches hard mask, and step 3 removes photoresist then etching groove, step 4 is removed hard mask and is sacrificed oxidation, and step 5 is cleaned and grown grid oxygen.This process needs to be configured with C
4f
8professional etching apparatus carry out etching groove to ensure the uniformity of groove pattern and subsequent gate oxygen.The gas that conventional trench etching apparatus configures is mainly Cl
2, HBr, cannot form good polymer, forms the protection of effective sidewall, and then ensures the pattern of groove and the uniformity of subsequent gate oxygen.
Summary of the invention
An object of the present invention solves common polycrystalline etching in above-mentioned prior art to be unworthy of setting high carbon content gas; good polymer cannot be formed during etching groove; form the protection of effective sidewall; a kind of method utilizing common polycrystalline etching apparatus etching groove is provided, the groove that pattern is excellent can be etched.
Another object of the present invention is, when adopting common etching apparatus in solution prior art, groove top and bottom can not reach round and smooth neat looks, provide a kind of method utilizing common polycrystalline etching apparatus etching groove.
One of technical scheme realizing the object of the invention is: (1) sacrifices oxidation and hard mask deposit; (2) photoetching and hard mask etching; (3) etching groove and photoresist are removed; (4) hard mask and sacrificial oxide layer is removed; (5) gate oxide growth.
Another technical scheme realizing the object of the invention is: a kind of method utilizing common polycrystalline etching apparatus etching groove, it is characterized in that comprising the steps: that (1) sacrifices oxidation and hard mask deposit; (2) photoetching and hard mask etching; (3) etching groove and photoresist are removed; (4) hard mask and sacrificial oxide layer is removed; (5) carry out hot repair to answer and sacrificial oxide layer growth; (6) sacrificial oxide layer is removed, is cleaned; (7) gate oxide growth.
The above-mentioned method utilizing common polycrystalline etching apparatus etching groove, described method realizes on common poly etching apparatus, and the gas of this etching apparatus configuration is Cl2 and HBr.
A kind of semiconductor device, have groove, described groove adopts aforementioned lithographic method to make.
One of the present invention program does not carry out photoresist removal after hard mask etching, because the main combination relying on hydrogen bromide and photoresist of polycrystal etching equipment etching process sidewall protection.Therefore the polymer that the photoresist retaining hard mask top is protected for the formation of sidewall, thus form more straight groove pattern.
Another program of the present invention provide groove top and bottom slip processing method remove hard mask with sacrifice be oxidized after to increase hot repair multiple and grow the step of sacrificial oxide layer, this step is mainly used for the damage of repairing etching process generation, and utilize sacrifice oxidation round and smooth process is carried out at groove top and bottom pattern, make the thickness of subsequent gate oxygen and uniformity better.
The quality of groove pattern, the round and smooth degree of its top and bottom determine gate oxide growth thickness and uniformity in subsequent technique.
Owing to have employed according to groove etching method of the present invention, therefore, it will be appreciated by persons skilled in the art that semiconductor device of the present invention can have the Advantageous achievement achieved by groove etching method of the present invention equally.
The present invention has positive effect: (1) this method does not carry out photoresist removal after hard mask etching, but retain the photoresist at hard mask top, rely on the combination of hydrogen bromide and photoresist to form the polymer of sidewall protection, thus form more straight groove pattern; (2) this method increases the multiple step with growing sacrificial oxide layer of hot repair after removing hard mask and sacrificial oxide layer, for repairing the damage that etching process produces, and utilize sacrifice oxidation round and smooth process is carried out at groove top and bottom pattern, make the thickness of subsequent gate oxygen and uniformity better; (3) using this method, that common polycrystalline silicon etching equipment can be utilized to etch pattern is excellent, the smooth and round and smooth groove without corner angle in bottom of sidewall, further the quality of guarantee grid oxygen and uniformity, and during product, stability is greatly improved.
Accompanying drawing explanation
In order to make content of the present invention more easily be clearly understood, below according to specific embodiment also by reference to the accompanying drawings, the present invention is further detailed explanation, wherein
Fig. 1 is that the good top of groove pattern that obtains according to the method for the embodiment of the present invention 1 and bottom are round and smooth.
Embodiment
(embodiment 1)
(1) step 1: sacrifice oxidation and hard mask deposit.
Sacrifice oxidation
hard mask uses LP-TEOS deposit
carry out 850 DEG C of densifications.
(2) step 2: photoetching and hard mask etching.
Carry out the etching of photoetching and hard mask, this place etching guarantees that silicon loses
and angle is more than 85 °
(3) step 3: etching groove and photoresist are removed.
Carry out etching groove and use common polycrystalline silicon etching equipment, recipe mainly arranges between project setting district: Power:150 ~ 600W, Cl2:30 ~ 80SCCM, HBr:20 ~ 60SCCM, Pressure:150 ~ 500mt.This place uses multi-step etching to form rounder and more smooth bottom etching, the amount of HBr is increased, Cl after etching depth reaches
2amount reduce, add a small amount of He-O
2(the O of 10% ~ 30%
2content).
(4) step 4: remove hard mask and sacrificial oxide layer.
Remove hard mask and be first 50:1HF10 DIP second, to remove the polymer produced in etching groove process, remove hard mask and sacrificial oxide layer mainly uses BOE.Sacrifice oxidation 1150 DEG C of dry oxygen
lower oxide thickness has lower CD bias.
(5) step 5: carry out hot repair and answer and sacrifice oxidation growth.
Sacrifice oxidation 1150 DEG C of hot repairs and grow dry oxygen again simultaneously
as the lower oxide thickness of sacrifice oxidation, there is lower CD bias.
(6) step 6: sacrificial oxide layer removes cleaning and gate oxide growth.
Sacrifice the HF that oxidation uses 20:1, use the RCA cleaning process of standard to complete the front cleaning of grid oxygen, and carried out gate oxidation in 1 hour.Gate oxide thickness is determined according to product performance.
(embodiment 2)
(1) step 1: sacrifice oxidation and hard mask deposit.
Sacrifice oxidation
hard mask uses LP-TEOS deposit
carry out 850 DEG C of densifications.
(2) step 2: photoetching and hard mask etching.
Carry out the etching of photoetching and hard mask, this place etching guarantees that silicon loses
and angle is more than 85 °
(3) step 3: etching groove and photoresist are removed.
Carry out etching groove and use common polycrystalline silicon etching equipment, recipe mainly arranges between project setting district: Power:250 ~ 600W, Cl2:40 ~ 80SCCM, HBr:30 ~ 60SCCM, Pressure:200 ~ 500mt.This place carries out a step etching, the amount of HBr is increased, Cl after etching depth reaches
2amount reduce, add a small amount of He-O
2(the O of 10% ~ 30%
2content).
(4) step 4: remove hard mask and sacrificial oxide layer.
Remove hard mask and be first 50:1HF10 DIP second, to remove the polymer produced in etching groove process, remove hard mask and sacrificial oxide layer mainly uses BOE.Sacrifice oxidation 1150 DEG C of dry oxygen
lower oxide thickness has lower CD bias.
(5) step 6: sacrificial oxide layer removes cleaning and gate oxide growth.
Sacrifice the HF that oxidation uses 20:1, use the RCA cleaning process of standard to complete the front cleaning of grid oxygen, and carried out gate oxidation in 1 hour.Gate oxide thickness is determined according to product performance.
Above-described specific embodiment; object of the present invention, technical scheme and beneficial effect are further described; be understood that; the foregoing is only specific embodiments of the invention; be not limited to the present invention; within the spirit and principles in the present invention all, any amendment made, equivalent replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (4)
1. utilize a method for common polycrystalline etching apparatus etching groove, it is characterized in that comprising the steps: that (1) sacrifices oxidation and hard mask deposit; (2) photoetching and hard mask etching; (3) etching groove and photoresist are removed; (4) hard mask and sacrificial oxide layer is removed; (5) gate oxide growth.
2. the method utilizing common polycrystalline etching apparatus etching groove according to claim 1, is characterized in that: increase (5) afterwards in step (4) and carry out the multiple and sacrificial oxide layer growth of hot repair and (6) sacrificial oxide layer is removed, cleaning.
3. the method utilizing common polycrystalline etching apparatus etching groove according to claim 1 and 2, is characterized in that: described method realizes on common poly etching apparatus, and the gas of this etching apparatus configuration is Cl2 and HBr.
4. a semiconductor device, described semiconductor device has groove, it is characterized in that: described groove adopts the lithographic method as described in claim 1 or 2 or 3 to make.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310750598.1A CN104752160A (en) | 2013-12-31 | 2013-12-31 | Method for etching groove through common polycrystal etching device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310750598.1A CN104752160A (en) | 2013-12-31 | 2013-12-31 | Method for etching groove through common polycrystal etching device |
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| Publication Number | Publication Date |
|---|---|
| CN104752160A true CN104752160A (en) | 2015-07-01 |
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ID=53591681
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|---|---|---|---|
| CN201310750598.1A Pending CN104752160A (en) | 2013-12-31 | 2013-12-31 | Method for etching groove through common polycrystal etching device |
Country Status (1)
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|---|---|
| CN (1) | CN104752160A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115332061A (en) * | 2022-10-13 | 2022-11-11 | 合肥晶合集成电路股份有限公司 | Manufacturing method of grid structure |
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| US5920787A (en) * | 1997-01-16 | 1999-07-06 | Vlsi Technology, Inc. | Soft edge induced local oxidation of silicon |
| CN101777493A (en) * | 2010-01-28 | 2010-07-14 | 上海宏力半导体制造有限公司 | Hard mask layer etching method |
| CN102087989A (en) * | 2009-12-02 | 2011-06-08 | 无锡华润上华半导体有限公司 | Method for manufacturing shallow groove isolation structure |
| CN102184885A (en) * | 2011-04-08 | 2011-09-14 | 上海先进半导体制造股份有限公司 | Groove isolating structure and manufacturing method thereof |
| CN102194678A (en) * | 2010-03-11 | 2011-09-21 | 中芯国际集成电路制造(上海)有限公司 | Method for etching grid |
| CN102222636A (en) * | 2010-04-14 | 2011-10-19 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method of shallow trench isolation |
| CN102361007A (en) * | 2011-11-02 | 2012-02-22 | 上海宏力半导体制造有限公司 | Method for etching groove and semiconductor device |
| CN102867774A (en) * | 2011-07-06 | 2013-01-09 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing shallow trench isolation |
| CN103000534A (en) * | 2012-12-26 | 2013-03-27 | 上海宏力半导体制造有限公司 | Manufacture method of groove-type P-type metal oxide semiconductor power transistor |
| CN103021925A (en) * | 2012-12-21 | 2013-04-03 | 上海宏力半导体制造有限公司 | STI (shallow trench isolation) manufacturing process, trench etching method and photoresist processing method |
| CN103187354A (en) * | 2011-12-30 | 2013-07-03 | 中芯国际集成电路制造(上海)有限公司 | Forming method of locally oxidized silicon isolation |
-
2013
- 2013-12-31 CN CN201310750598.1A patent/CN104752160A/en active Pending
Patent Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5920787A (en) * | 1997-01-16 | 1999-07-06 | Vlsi Technology, Inc. | Soft edge induced local oxidation of silicon |
| CN102087989A (en) * | 2009-12-02 | 2011-06-08 | 无锡华润上华半导体有限公司 | Method for manufacturing shallow groove isolation structure |
| CN101777493A (en) * | 2010-01-28 | 2010-07-14 | 上海宏力半导体制造有限公司 | Hard mask layer etching method |
| CN102194678A (en) * | 2010-03-11 | 2011-09-21 | 中芯国际集成电路制造(上海)有限公司 | Method for etching grid |
| CN102222636A (en) * | 2010-04-14 | 2011-10-19 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method of shallow trench isolation |
| CN102184885A (en) * | 2011-04-08 | 2011-09-14 | 上海先进半导体制造股份有限公司 | Groove isolating structure and manufacturing method thereof |
| CN102867774A (en) * | 2011-07-06 | 2013-01-09 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing shallow trench isolation |
| CN102361007A (en) * | 2011-11-02 | 2012-02-22 | 上海宏力半导体制造有限公司 | Method for etching groove and semiconductor device |
| CN103187354A (en) * | 2011-12-30 | 2013-07-03 | 中芯国际集成电路制造(上海)有限公司 | Forming method of locally oxidized silicon isolation |
| CN103021925A (en) * | 2012-12-21 | 2013-04-03 | 上海宏力半导体制造有限公司 | STI (shallow trench isolation) manufacturing process, trench etching method and photoresist processing method |
| CN103000534A (en) * | 2012-12-26 | 2013-03-27 | 上海宏力半导体制造有限公司 | Manufacture method of groove-type P-type metal oxide semiconductor power transistor |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115332061A (en) * | 2022-10-13 | 2022-11-11 | 合肥晶合集成电路股份有限公司 | Manufacturing method of grid structure |
| CN115332061B (en) * | 2022-10-13 | 2022-12-16 | 合肥晶合集成电路股份有限公司 | Manufacturing method of grid structure |
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Application publication date: 20150701 |