CN102184885A - Groove isolating structure and manufacturing method thereof - Google Patents
Groove isolating structure and manufacturing method thereof Download PDFInfo
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- CN102184885A CN102184885A CN2011100872552A CN201110087255A CN102184885A CN 102184885 A CN102184885 A CN 102184885A CN 2011100872552 A CN2011100872552 A CN 2011100872552A CN 201110087255 A CN201110087255 A CN 201110087255A CN 102184885 A CN102184885 A CN 102184885A
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Abstract
The invention provides a manufacturing method of a groove isolating structure, comprising the steps of: providing a semiconductor substrate and forming an buried layer and a first epitaxial layer with opposite types to the semiconductor substrate in sequence on the semiconductor substrate; forming a masking layer on the first epitaxial layer as a hard mask for etching a groove; coating a photoresist on the masking layer in a spinning manner, photoetching, developing and exposing positions on which grooves need to be etched; etching the masking layer, the first epitaxial layer, the buried layer and the semiconductor substrate in sequence, forming an isolating groove which extends into the semiconductor substrate straightly; carrying out heat treatment on a wafer, and repairing the crystal defects originally introduced in the process of etching the groove; removing an oxidation layer growing in the groove during heat treatment by a wet method; and depositing a second epitaxial layer in the groove which has the same type with the semiconductor substrate and is connected with the semiconductor substrate after completely filling the groove. Correspondingly, the invention also provides the groove isolating structure. In the manufacturing method, the electric isolation among devices with different working voltages is finished by utilizing the horizontal sizes of smaller chips.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, specifically, the present invention relates to a kind of groove isolation construction and preparation method thereof.
Background technology
Along with the develop rapidly of semiconductor fine process technology, the integrated level and the complexity of integrated circuit (IC) are more and more higher.Latest developments BCD (Bipolar, CMOS, DMOS) technology faster particularly, the logical circuit (Logic IC) and the higher power device (Power Device) of operating voltage of integrated low-voltage, low-power consumption in same chip make that the electric isolation between the device of different operating voltage becomes more important.
Fig. 1 is the cross-sectional view of a kind of traditional PN junction isolation technology of generally using in the prior art.As shown in the figure, be formed with N type epitaxial loayer 101 on P type semiconductor substrate 100, be formed with base stage 102, collector electrode 103 and the emitter 104 of bipolar transistor respectively on this N type epitaxial loayer 101, wherein emitter 104 is formed in the zone of base stage 102.Also be provided with a dark P trap 105 respectively in the left and right sides of above-mentioned bipolar transistor, the degree of depth of described dark P trap 105 extends to P type semiconductor substrate 100 always, is used for the circuit devcie electric isolation of this bipolar transistor and other different operating voltages is come.In different practical applications, two or more a plurality of dark P trap 105 can also be set respectively in the left and right sides of above-mentioned bipolar transistor, further obtain better electric isolation effect.
In above-mentioned isolation technology, need carry out long heat treatment process dark P trap 105 and P type semiconductor substrate 100 are ganged up up and down, otherwise can not carry out electric isolation.In addition, this traditional PN junction isolation technology also can take bigger chip horizontal area, the size of shared chip horizontal area depends on the demand of isolation voltage, and isolation voltage is big more, and then to be used to isolate required chip horizontal area also big more, increased manufacturing cost.
And Fig. 2 is cross-sectional view that silicon dioxide layer filling groove technology realizes smart-power IC (Smart Power IC) lateral isolation of passing through based on SOI (Silicon On Isolation, silicon-on-insulator) technology in the prior art.As shown in the figure, on silicon substrate 200, be formed with silicon dioxide insulating layer 201, on this insulating barrier 201, be formed with silicon top layer 202 by for example epitaxy again.Then, two grooves 203 of etching respectively in silicon top layer 202, the bottom of this groove 203 directly contacts with insulating barrier 201, so the device of smart-power IC just can be produced on the insulating barrier 201, the zone between two grooves 203 has suffered.
But the cost of SOI technology itself is relatively expensive, and also there are some shortcomings in the SOI technology, and such as for the higher switching device of operating voltage, the influence of back of the body matrix effect is bigger.If thicken the silicon dioxide insulating layer of SOI in order to reduce back of the body matrix effect, then can influence the radiating effect of power device again, thereby cause the inefficacy of power device.
Thereby developing smart-power IC rapidly now needs isolation technology more suitably to finish electric isolation between the device of different operating voltage.
Summary of the invention
Technical problem to be solved by this invention provides a kind of groove isolation construction and preparation method thereof, can utilize less chip lateral dimension, finish the electric isolation between the device of different operating voltage, concrete technology is also fairly simple, has reduced production cost effectively.
In order to solve the problems of the technologies described above, the invention provides a kind of manufacture method of groove isolation construction, comprise step:
Semiconductor substrate is provided, is formed with the buried regions and first epitaxial loayer on it successively with described Semiconductor substrate type opposite;
On described first epitaxial loayer, form certain thickness mask layer, as the hard mask of etching groove;
The position that needs etching groove is exposed in spin coating photoresist, photoetching and development on described mask layer;
The described mask layer of etching, first epitaxial loayer, buried regions and Semiconductor substrate form isolated groove successively, and described groove extends in the described Semiconductor substrate always;
Whole wafer is heat-treated the crystal defect of in the etching groove process, introducing before repairing;
Remove the oxide layer of in described groove, growing in the above-mentioned heat treatment process with the wet etching method;
Deposit second epitaxial loayer in described groove, its type with described Semiconductor substrate is identical, is connected with described Semiconductor substrate behind the described groove of the described second epitaxial loayer complete filling.
Alternatively, the described Semiconductor substrate and second epitaxial loayer are the P type, and the described buried regions and first epitaxial loayer are the N type.
Alternatively, the described Semiconductor substrate and second epitaxial loayer are the N type, and the described buried regions and first epitaxial loayer are the P type.
Alternatively, described Semiconductor substrate is a silicon substrate.
Alternatively, described mask layer is silicon dioxide or silicon nitride.
Correspondingly, the present invention also provides a kind of groove isolation construction, comprise that successively seeing through mask layer, first epitaxial loayer and buried regions extends to isolated groove in the Semiconductor substrate, the type opposite of described first epitaxial loayer and buried regions and described Semiconductor substrate, be deposited with second epitaxial loayer in the described groove, its type with described Semiconductor substrate is identical, is connected with described Semiconductor substrate behind the described groove of the described second epitaxial loayer complete filling.
Alternatively, the described Semiconductor substrate and second epitaxial loayer are the P type, and the described buried regions and first epitaxial loayer are the N type.
Alternatively, the described Semiconductor substrate and second epitaxial loayer are the N type, and the described buried regions and first epitaxial loayer are the P type.
Alternatively, described Semiconductor substrate is a silicon substrate.
Alternatively, described mask layer is silicon dioxide or silicon nitride.
Compared with prior art, the present invention has the following advantages:
The present invention utilizes less chip lateral dimension, just can finish the electric isolation between the device of different operating voltage, has increased substantially the integrated level of device.Its concrete technology is also fairly simple, and is compatible fully with existing C MOS technology, reduced production cost effectively.
Description of drawings
The above and other features of the present invention, character and advantage will become more obvious by the description below in conjunction with drawings and Examples, wherein:
Fig. 1 is the cross-sectional view of a kind of traditional PN junction isolation technology of generally using in the prior art;
Fig. 2 is cross-sectional view that silicon dioxide layer filling groove technology realizes the smart-power IC lateral isolation of passing through based on SOI technology in the prior art;
Fig. 3 is the flow chart of manufacture method of the groove isolation construction of one embodiment of the invention;
Fig. 4 to Fig. 8 is the cross-sectional view of manufacturing process of the groove isolation construction of one embodiment of the invention.
Embodiment
The invention will be further described below in conjunction with specific embodiments and the drawings, but should not limit protection scope of the present invention with this.
Fig. 3 is the flow chart of manufacture method of the groove isolation construction of one embodiment of the invention.As shown in the figure, this manufacture method originates in step S301.This method can comprise: execution in step S301, Semiconductor substrate is provided, and be formed with the buried regions and first epitaxial loayer on it successively with the Semiconductor substrate type opposite;
Execution in step S302 forms certain thickness mask layer, as the hard mask of etching groove on first epitaxial loayer;
Execution in step S303, the position that needs etching groove is exposed in spin coating photoresist, photoetching and development on mask layer;
Execution in step S304, etch mask layer, first epitaxial loayer, buried regions and Semiconductor substrate form isolated groove successively, and groove extends in the Semiconductor substrate always;
Execution in step S305 heat-treats whole wafer, the crystal defect of introducing in the etching groove process before repairing;
Execution in step S306 removes the oxide layer of growing in the above-mentioned heat treatment process in groove with the wet etching method;
Execution in step S307, deposit second epitaxial loayer in groove, its type with Semiconductor substrate is identical, is connected with Semiconductor substrate behind the second epitaxial loayer complete filling groove.
Fig. 4 to Fig. 8 is the cross-sectional view of manufacturing process of the groove isolation construction of one embodiment of the invention.
As shown in Figure 4, provide Semiconductor substrate 400, be formed with the buried regions 401 and first epitaxial loayer 402 on it successively with Semiconductor substrate 400 type opposite.In the present embodiment, Semiconductor substrate 400 can be the P type, and this moment, the buried regions 401 and first epitaxial loayer 402 were the N type; Perhaps Semiconductor substrate 400 can be the N type, and this moment, the buried regions 401 and first epitaxial loayer 402 were the P type.This Semiconductor substrate 400 then be specifically as follows silicon substrate.
As shown in Figure 5, form certain thickness mask layer 403 on first epitaxial loayer 402, as the hard mask of etching groove, this mask layer 403 can be silicon dioxide or silicon nitride.
As shown in Figure 6, the position that needs etching groove is exposed in spin coating photoresist 404, photoetching and development on mask layer 403.Above-mentioned spin coating photoresist, photoetching and the technology of developing can adopt prior art known in those skilled in the art, do not repeat them here.
As shown in Figure 7, etch mask layer 403, first epitaxial loayer 402, buried regions 401 and Semiconductor substrate 400 form isolated groove 405 successively, and groove 405 extends in the Semiconductor substrate 400 always.Above-mentioned etching groove process can adopt the dry etching method, takes different etching gas at different etching media.
After the intact groove 405 of etching, also need to remove photoresist 404 and wafer is done suitable cleaning, but above-mentioned steps all belongs to step known in those skilled in the art, does not repeat them here equally for the sake of brevity with ashing method.
Then whole wafer is heat-treated, for example rapid thermal annealing (RTA) is repaired the crystal defect of introducing before in the etching groove process.Then remove the oxide layer of growing in the above-mentioned heat treatment process with the wet etching method in groove 405 again, above-mentioned oxide layer can be accompanied by the wafer heat treatment process and produce, and can influence follow-up groove deposit effect.
As shown in Figure 8, deposit second epitaxial loayer 406 in groove 405, its type with Semiconductor substrate 400 is identical, and promptly when the type of Semiconductor substrate 400 was the P type, second epitaxial loayer 406 also was the P type, and this moment, the buried regions 401 and first epitaxial loayer 402 were the N type; When the type of Semiconductor substrate 400 was the N type, second epitaxial loayer 406 also was the N type, and this moment, the buried regions 401 and first epitaxial loayer 402 were the P type.Second epitaxial loayer, 406 complete filling grooves, 405 backs are connected with Semiconductor substrate 400, so far finish the manufacturing process of the groove isolation construction of present embodiment, the device of smart-power IC just can be produced on the buried regions 401, the zone 407 under the mask layer 403, between two groove isolation constructions has suffered.
In addition, as shown in Figure 8, the groove isolation construction of one embodiment of the invention can comprise that successively seeing through mask layer 403, first epitaxial loayer 402 and buried regions 401 extends to isolated groove 405 in the Semiconductor substrate 400, the type opposite of first epitaxial loayer 402 and buried regions 401 and Semiconductor substrate 400, be deposited with second epitaxial loayer 406 in the groove 405, its type with Semiconductor substrate 400 is identical, and second epitaxial loayer, 406 complete filling grooves, 405 backs are connected with Semiconductor substrate 400.
In the present embodiment, the Semiconductor substrate 400 and second epitaxial loayer 406 can be the P type, and this moment, the buried regions 401 and first epitaxial loayer 402 were the N type; Perhaps the Semiconductor substrate 400 and second epitaxial loayer 406 can be the N type, and this moment, the buried regions 401 and first epitaxial loayer 402 were the P type.And this Semiconductor substrate 400 be specifically as follows silicon substrate, 403 of mask layers can be silicon dioxide or silicon nitride.
The present invention utilizes less chip lateral dimension, just can finish the electric isolation between the device of different operating voltage, has increased substantially the integrated level of device.Its concrete technology is also fairly simple, and is compatible fully with existing C MOS technology, reduced production cost effectively.
Though the present invention with preferred embodiment openly as above; but it is not to be used for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can make possible change and modification, so protection scope of the present invention should be as the criterion with the scope that claim of the present invention was defined.
Claims (10)
1. the manufacture method of a groove isolation construction comprises step:
Semiconductor substrate is provided, is formed with the buried regions and first epitaxial loayer on it successively with described Semiconductor substrate type opposite;
On described first epitaxial loayer, form certain thickness mask layer, as the hard mask of etching groove;
The position that needs etching groove is exposed in spin coating photoresist, photoetching and development on described mask layer;
The described mask layer of etching, first epitaxial loayer, buried regions and Semiconductor substrate form isolated groove successively, and described groove extends in the described Semiconductor substrate always;
Whole wafer is heat-treated the crystal defect of in the etching groove process, introducing before repairing;
Remove the oxide layer of in described groove, growing in the above-mentioned heat treatment process with the wet etching method;
Deposit second epitaxial loayer in described groove, its type with described Semiconductor substrate is identical, is connected with described Semiconductor substrate behind the described groove of the described second epitaxial loayer complete filling.
2. manufacture method according to claim 1 is characterized in that, the described Semiconductor substrate and second epitaxial loayer are the P type, and the described buried regions and first epitaxial loayer are the N type.
3. manufacture method according to claim 1 is characterized in that, the described Semiconductor substrate and second epitaxial loayer are the N type, and the described buried regions and first epitaxial loayer are the P type.
4. according to each described manufacture method in the claim 1 to 3, it is characterized in that described Semiconductor substrate is a silicon substrate.
5. manufacture method according to claim 4 is characterized in that, described mask layer is silicon dioxide or silicon nitride.
6. groove isolation construction, comprise that successively seeing through mask layer, first epitaxial loayer and buried regions extends to isolated groove in the Semiconductor substrate, the type opposite of described first epitaxial loayer and buried regions and described Semiconductor substrate, be deposited with second epitaxial loayer in the described groove, its type with described Semiconductor substrate is identical, is connected with described Semiconductor substrate behind the described groove of the described second epitaxial loayer complete filling.
7. groove isolation construction according to claim 6 is characterized in that, the described Semiconductor substrate and second epitaxial loayer are the P type, and the described buried regions and first epitaxial loayer are the N type.
8. groove isolation construction according to claim 6 is characterized in that, the described Semiconductor substrate and second epitaxial loayer are the N type, and the described buried regions and first epitaxial loayer are the P type.
9. according to each described groove isolation construction in the claim 6 to 8, it is characterized in that described Semiconductor substrate is a silicon substrate.
10. groove isolation construction according to claim 9 is characterized in that, described mask layer is silicon dioxide or silicon nitride.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN2011100872552A CN102184885A (en) | 2011-04-08 | 2011-04-08 | Groove isolating structure and manufacturing method thereof |
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| Application Number | Priority Date | Filing Date | Title |
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| CN2011100872552A CN102184885A (en) | 2011-04-08 | 2011-04-08 | Groove isolating structure and manufacturing method thereof |
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| CN102184885A true CN102184885A (en) | 2011-09-14 |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102315154A (en) * | 2011-09-30 | 2012-01-11 | 上海宏力半导体制造有限公司 | Silicon-on-insulator structure and manufacturing method thereof as well as semiconductor device |
| CN103839975A (en) * | 2012-11-26 | 2014-06-04 | 上海华虹宏力半导体制造有限公司 | Low-depth connection groove and manufacture method |
| CN104752160A (en) * | 2013-12-31 | 2015-07-01 | 苏州同冠微电子有限公司 | Method for etching groove through common polycrystal etching device |
| CN105826331A (en) * | 2015-01-04 | 2016-08-03 | 格科微电子（上海）有限公司 | Method of manufacturing back-illuminated image sensor adopting back-illuminated deep trench isolation |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01319969A (en) * | 1988-06-21 | 1989-12-26 | Matsushita Electric Ind Co Ltd | Manufacture of semiconductor device |
-
2011
- 2011-04-08 CN CN2011100872552A patent/CN102184885A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01319969A (en) * | 1988-06-21 | 1989-12-26 | Matsushita Electric Ind Co Ltd | Manufacture of semiconductor device |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102315154A (en) * | 2011-09-30 | 2012-01-11 | 上海宏力半导体制造有限公司 | Silicon-on-insulator structure and manufacturing method thereof as well as semiconductor device |
| CN103839975A (en) * | 2012-11-26 | 2014-06-04 | 上海华虹宏力半导体制造有限公司 | Low-depth connection groove and manufacture method |
| CN104752160A (en) * | 2013-12-31 | 2015-07-01 | 苏州同冠微电子有限公司 | Method for etching groove through common polycrystal etching device |
| CN105826331A (en) * | 2015-01-04 | 2016-08-03 | 格科微电子（上海）有限公司 | Method of manufacturing back-illuminated image sensor adopting back-illuminated deep trench isolation |
| CN105826331B (en) * | 2015-01-04 | 2020-06-02 | 格科微电子（上海）有限公司 | Method for manufacturing back side illumination type image sensor adopting back side deep groove isolation |
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Application publication date: 20110914 |