CN104425251A - Manufacturing method of reverse conduction FS IGBT (field stop insulated gate bipolar transistor) - Google Patents
Manufacturing method of reverse conduction FS IGBT (field stop insulated gate bipolar transistor) Download PDFInfo
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- CN104425251A CN104425251A CN201310389765.4A CN201310389765A CN104425251A CN 104425251 A CN104425251 A CN 104425251A CN 201310389765 A CN201310389765 A CN 201310389765A CN 104425251 A CN104425251 A CN 104425251A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 30
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 71
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 71
- 239000010703 silicon Substances 0.000 claims abstract description 71
- 238000000034 method Methods 0.000 claims abstract description 58
- 239000000758 substrate Substances 0.000 claims abstract description 53
- 238000005516 engineering process Methods 0.000 claims abstract description 11
- 239000002184 metal Substances 0.000 claims abstract description 9
- 238000001259 photo etching Methods 0.000 claims abstract description 7
- 230000015572 biosynthetic process Effects 0.000 claims description 9
- 238000000407 epitaxy Methods 0.000 claims description 7
- 238000002425 crystallisation Methods 0.000 claims description 4
- 230000008025 crystallization Effects 0.000 claims description 4
- 230000008020 evaporation Effects 0.000 claims description 3
- 238000001704 evaporation Methods 0.000 claims description 3
- 238000004544 sputter deposition Methods 0.000 claims description 3
- 239000000126 substance Substances 0.000 claims description 2
- 238000005530 etching Methods 0.000 abstract description 3
- 238000002360 preparation method Methods 0.000 description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- 239000013078 crystal Substances 0.000 description 3
- 238000002347 injection Methods 0.000 description 3
- 239000007924 injection Substances 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 239000011888 foil Substances 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/083—Anode or cathode regions of thyristors or gated bipolar-mode devices
- H01L29/0834—Anode regions of thyristors or gated bipolar-mode devices, e.g. supplementary regions surrounding anode regions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
- H01L29/66333—Vertical insulated gate bipolar transistors
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Abstract
The invention discloses a manufacturing method of a reverse conduction FS IGBT (field stop insulated gate bipolar transistor). The manufacturing method comprises the following steps of providing a P type silicon substrate; performing photoetching and etching to form a plurality of groove structures at one surface of the substrate; filling N type silicon into the grooves, and forming a back PN alternating structure at the surface of the substrate; preparing an N type field stop layer at the N type silicon filling surface of the substrate by an epitaxial technology; preparing an N type drift area on the field stop layer by the epitaxial technology; adopting an IGBT face technology to prepare an IGBT face structure; thinning the substrate to the back PN alternating structure; forming a back metal electrode at the surface, away from the field stop layer, of the back PN alternating structure. The manufacturing method has the advantage that the back PN alternating structure is directly manufactured on the substrate before the face technology, an FS layer and the drift area are prepared by the epitaxial method, a wafer after epitaxial treatment has the same thickness as the conventional circulating wafer, and then the conventional face technology is performed, so compared with the existing conventional technology, the special wafer circulating equipment is not needed, and the cost is reduced.
Description
Technical field
The present invention relates to the manufacture method of semiconductor device, particularly relate to the manufacture method of a kind of reverse-conducting field cut-off type insulated gate bipolar transistor.
Background technology
Insulated gate bipolar transistor (IGBT) generally adopts the mode of reverse parallel connection fly-wheel diode to use.But this mode wastes package area on the one hand, on the other hand due to the existence of the ghost effects such as stray inductance, parallel connection adds additional power consumption.Therefore, technology IGBT and diode being integrated in same chip comes into one's own day by day.
Reverse-conducting field cut-off type (Field Stop, FS) IGBT is a kind of switching device being usually used in the power consumption equipments such as electromagnetic oven, and owing to improving the passage of non equilibrium carrier, its tail currents is optimized, device does not need fly-wheel diode in parallel again simultaneously, reduces cost.
The preparation difficult point of reverse-conducting FS IGBT is that back side N+buffer layer (i.e. Field Stop layer) and back side P/N hand over the preparation every structure, a kind of traditional preparation method first utilizes injection (or pre-expansion)+high temperature to push away after trap prepares back side N+buffer layer to hand over every structure by dual surface lithography overleaf structure being produced P/N, structure does Facad structure technique after completing again overleaf, for below low pressure IGBT(1700V) Facad structure preparation before just need Wafer Thinning to less than 200 μm, this will ask production line to have thin slice to lead to line ability, therefore special thin slice flow-through device and double-sided exposure equipment is needed.
Summary of the invention
Based on this, special thin slice circulation, process equipment is needed in order to solve traditional reverse-conducting field cut-off type insulated gate bipolar transistor, cause needing additionally to buy more production equipment, improve the problem of production cost, be necessary to provide the manufacture method that a kind of and existing conventional production equipment is compatible, do not need the reverse-conducting field cut-off type insulated gate bipolar transistor of thin slice flow-through device.
A manufacture method for reverse-conducting field cut-off type insulated gate bipolar transistor, comprises the following steps: the silicon substrate providing the first doping type; Multiple groove structure is formed by photoetching and the one side that is etched in described silicon substrate; In described groove, fill the silicon of the second doping type, hand over every structure at the formation back side, the surface PN of described silicon substrate; Described second doping type is electrically contrary with the first doping type; The field cutoff layer of N-type is prepared on the surface being filled with the silicon of the second doping type at silicon substrate by epitaxy technique; On the cutoff layer of described field, extension prepares the drift region of N-type; Comprise the silicon substrate of described first doping type, PN friendship every structure, field cutoff layer and the silicon chip gross thickness of drift region and the consistency of thickness of the conventional silicon chip that circulates; Insulated gate bipolar transistor front technique is adopted to prepare insulated gate bipolar transistor Facad structure in described drift region He on drift region; Described silicon substrate is thinned to described back side PN to hand over every structure place; The surface formation back metal electrode deviating from described field cutoff layer every structure is handed at described back side PN.
Wherein in an embodiment, described silicon of filling the second doping type in groove, hand over after the step of structure at the formation back side, the surface PN of described silicon substrate, also comprise and the step of carrying out chemical mechanical planarization every the surface of structure is handed over to described back side PN.
Wherein in an embodiment, the step of field cutoff layer of N-type is prepared on the described surface being filled with the silicon of the second doping type at silicon substrate by epitaxy technique before, the silicon of temperature to described second doping type of filling also comprising employing more than 800 degrees Celsius carries out the step of single crystallization process.
Wherein in an embodiment, the described thickness of silicon substrate in the step of the silicon substrate of the first doping type that provides is 100 ~ 650 microns, the thickness of described field cutoff layer is 2 ~ 100 microns, and on described cutoff layer on the scene, extension prepares the thickness of drift region in the step of the drift region of N-type is 10 ~ 650 microns.
Wherein in an embodiment, the doping content of described field cutoff layer is 4*10
13~ 1*10
16/ cubic centimetre.
Wherein in an embodiment, the described resistivity of silicon substrate in the step of the silicon substrate of the first doping type that provides is 0.001 ~ 100 ohm of * centimetre, described resistivity of filling the silicon of second doping type of filling in the step of the silicon of the second doping type in groove is 0.01 ~ 50 ohm of * centimetre, the step midfield cutoff layer of the field cutoff layer of N-type is prepared on the described surface being filled with the silicon of the second doping type at silicon substrate resistivity by epitaxy technique is 5 ~ 100 ohm of * centimetre, on described cutoff layer on the scene, extension prepares the resistivity of drift region in the step of the drift region of N-type is 5 ~ 500 ohm of * centimetre.
Wherein in an embodiment, describedly formed in the step of multiple groove structure by photoetching and the one side that is etched in described silicon substrate, the degree of depth of groove is 0.5 ~ 50 micron.
Wherein in an embodiment, described PN overleaf hands over the step deviating from the surface formation back metal electrode of described field cutoff layer every structure, is adopt sputtering or evaporation technology to prepare described back metal electrode.
Wherein in an embodiment, described front technique is the front technique of planar gate insulated gate bipolar transistor, and described reverse-conducting field cut-off type insulated gate bipolar transistor is planar gate insulated gate bipolar transistor.
Wherein in an embodiment, described front technique is the front technique of trench-gate insulated gate bipolar transistor, and described reverse-conducting field cut-off type insulated gate bipolar transistor is trench-gate insulated gate bipolar transistor.
The manufacture method of above-mentioned reverse-conducting field cut-off type insulated gate bipolar transistor, before the technique of front, on substrate, directly make back side PN hand over every structure, therefore can adopting conventional lithographic, etching, chemical vapor deposition (or extension) equipment availability, handing over every structure to form back side PN without the need to using sided exposure machine.Prepared by the N-type Buffer layer needed for FS structure and the drift region extensional mode of IGBT, without the need to the energetic ion injection device using Implantation Energy can reach more than 1 million electro-volt.Delay wafer thickness outward identical with the routine disk that circulate, then carry out conventional front technique, therefore compatible with existing common process, technique simply, without the need to dedicated foil flow-through device, greatly reduce process costs.
Accompanying drawing explanation
Fig. 1 is the flow chart of the manufacture method of reverse-conducting field cut-off type insulated gate bipolar transistor in an embodiment;
Fig. 2 A ~ Fig. 2 H is in an embodiment of the manufacture method of reverse-conducting field of the present invention cut-off type insulated gate bipolar transistor, the generalized section of reverse-conducting FS IGBT in preparation process;
Fig. 3 A ~ Fig. 3 H is in another embodiment of manufacture method of reverse-conducting field of the present invention cut-off type insulated gate bipolar transistor, the generalized section of reverse-conducting FS IGBT in preparation process.
Embodiment
For enabling object of the present invention, feature and advantage more become apparent, and are described in detail the specific embodiment of the present invention below in conjunction with accompanying drawing.
Fig. 1 is that in an embodiment, Fig. 1 is the flow chart of the manufacture method of reverse-conducting field cut-off type insulated gate bipolar transistor in an embodiment, comprises the following steps:
S110, provides the silicon substrate of the first doping type.
Please refer to Fig. 2 A, in the present embodiment, the first doping type is P type, and the second doping type is N-type; The resistivity of P type substrate 10 is 0.001 ~ 100 Ω * cm.Because the part-structure of P type substrate 10 as the P+ emitter region, the back side of reverse-conducting FS IGBT, therefore can have corresponding requirement to its resistivity simultaneously.
S120, forms multiple groove structure by photoetching and the one side that is etched in silicon substrate.
Please refer to Fig. 2 B, photoetching goes out groove 11 in P type substrate 10 surface etch after forming corrosion window under the sheltering of photoresist 13.In the present embodiment, the degree of depth of groove 11 is 0.5 ~ 50 micron.
S130, fills the silicon of the second doping type in groove, hands over every structure at the formation back side, the surface PN of silicon substrate.
Please refer to Fig. 2 C, in the present embodiment, the second doping type is N-type.The N-type silicon of filling forms back side N-type conductive channel 12, therefore P type substrate 10 forms back side PN together with N-type conductive channel 12 hands over every structure on its surface.In the present embodiment, the resistivity of the N-type silicon of filling is 0.01 ~ 50 Ω * cm.
S140, the field cutoff layer of N-type is prepared on the surface being filled with N-type silicon at silicon substrate by epitaxy technique.
Please refer to Fig. 2 D, extension prepares N buffer layer as field cutoff layer 22.In the present embodiment, the doping content of field cutoff layer 22 is 4*10
13~ 1*10
16/ cm
3, resistivity is 5-100 Ω * cm.
S150, on cutoff layer on the scene, extension prepares the drift region of N-type.
Please refer to Fig. 2 E, in the present embodiment, the thickness of drift region 20 is 10 ~ 650 microns, and resistivity is 5 ~ 500 Ω * cm.After step S150 completes, comprise P type substrate 10, back side PN hands over the gross thickness every the silicon chip of structure, field cutoff layer 22 and drift region 20 consistent with the conventional silicon chip that circulates.The thickness of conventional circulation silicon chip is known silicon chip (wafer) the common thickness in manufacture, transmission of those skilled in the art, and being 625 microns for 6 inches of wafer, is 725 microns for 8 inches of wafer.
That is, should pre-designed P type substrate 10, field cutoff layer 22 and drift region 20 thickness, after step S150 is completed, the thickness of silicon chip is conventional circulation silicon wafer thickness.In the present embodiment, the thickness of the P type substrate 10 that step S110 provides is 100 ~ 650 microns, and the thickness of the field cutoff layer 22 prepared in step S140 is 2 ~ 100 microns, and the thickness of the drift region 20 of preparing in step S150 is 10 ~ 650 microns.
S160, adopts insulated gate bipolar transistor front technique to prepare insulated gate bipolar transistor Facad structure.
In the present embodiment, reverse-conducting FS IGBT is planar gate (Planar) IGBT, can prepare its Facad structure, repeat no more herein by the front technique of the known planar gate IGBT of those skilled in the art.With reference to Fig. 2 F, after step S160 completes, device comprises the P type tagma 24 in drift region 20, the emitter 25 of the N-type in P type tagma 24, the gate oxide 26 on surface, drift region 20, the polysilicon gate 27 on gate oxide 26 surface, the medium of oxides layer 28 of covering gate oxide layer 26 and polysilicon gate 27, and respectively from pad (pad) the E(emitter that emitter 25 and polysilicon gate 27 are drawn) and pad G(grid).
Understandable, in other embodiments, reverse-conducting FS IGBT also can be trench-gate (Trench) IGBT, can prepare its Facad structure by the front technique of the known trench-gate IGBT of those skilled in the art.
S170, is thinned to back side PN and hands over every structure place by silicon substrate.
Fig. 2 G is the generalized section of device after step S170 completes, and P type substrate 10 is worn away.
S180, PN hands over and forms back metal electrode every body structure surface overleaf.
With reference to Fig. 2 H, in the present embodiment, be obtain back metal electrode 19 by sputtering or the evaporation technology one side that PN friendship deviates from a cutoff layer 22 every structure overleaf.
The manufacture method of above-mentioned reverse-conducting field cut-off type insulated gate bipolar transistor, directly made back side PN and hands over every structure before the technique of front on substrate.Therefore conventional lithographic, etching, chemical vapor deposition (or extension) equipment availability can be adopted, and without the need to using sided exposure machine to hand over every structure to form back side PN.Prepared by the N-type Buffer layer needed for FS structure and the drift region extensional mode of IGBT, without the need to the energetic ion injection device using Implantation Energy can reach more than 1 million electro-volt.Delay wafer thickness outward identical with the routine disk that circulate, then carry out conventional front technique, therefore compatible with existing common process, technique simply, without the need to dedicated foil flow-through device, greatly reduce process costs.
Wherein in an embodiment, also comprise after filling N-type silicon in step S130 and the step that chemical-mechanical planarization (CMP) processes is carried out to the surface being filled with N-type silicon.
The N-type silicon of filling in step S130 can be monocrystalline silicon, polysilicon or amorphous silicon.Wherein in an embodiment, also comprise the step of with the high temperature of more than 800 degrees Celsius, the N-type silicon of filling being carried out to single crystallization process.This is because outer its crystal orientation of silicon materials extended is determined by substrate surface crystal orientation, single crystallization can guarantee the crystal orientation of the field cutoff layer 22 that epitaxial growth goes out and drift region 20.
Understandable, in another embodiment, also can be the first doping type be N-type, the second doping type be P type.Fig. 3 A ~ Fig. 3 H is the generalized section of reverse-conducting FS IGBT in preparation process in this embodiment.The main distinction of itself and previous embodiment is that substrate is N-type substrate 30, and what fill in groove 11 in step s 130, which is P-type silicon.The resistivity of N-type substrate 30 is 0.01 ~ 50 Ω * cm.
The above embodiment only have expressed several execution mode of the present invention, and it describes comparatively concrete and detailed, but therefore can not be interpreted as the restriction to the scope of the claims of the present invention.It should be pointed out that for the person of ordinary skill of the art, without departing from the inventive concept of the premise, can also make some distortion and improvement, these all belong to protection scope of the present invention.Therefore, the protection range of patent of the present invention should be as the criterion with claims.
Claims (10)
1. a manufacture method for reverse-conducting field cut-off type insulated gate bipolar transistor, comprises the following steps:
The silicon substrate of the first doping type is provided;
Multiple groove structure is formed by photoetching and the one side that is etched in described silicon substrate;
In described groove, fill the silicon of the second doping type, hand over every structure at the formation back side, the surface PN of described silicon substrate; Described second doping type is electrically contrary with the first doping type;
The field cutoff layer of N-type is prepared on the surface being filled with the silicon of the second doping type at silicon substrate by epitaxy technique;
On the cutoff layer of described field, extension prepares the drift region of N-type; Comprise the silicon substrate of described first doping type, PN friendship every structure, field cutoff layer and the silicon chip gross thickness of drift region and the consistency of thickness of the conventional silicon chip that circulates;
Insulated gate bipolar transistor front technique is adopted to prepare insulated gate bipolar transistor Facad structure in described drift region He on drift region;
Described silicon substrate is thinned to described back side PN to hand over every structure place;
The surface formation back metal electrode deviating from described field cutoff layer every structure is handed at described back side PN.
2. the manufacture method of reverse-conducting field according to claim 1 cut-off type insulated gate bipolar transistor, it is characterized in that, described silicon of filling the second doping type in groove, hand over after the step of structure at the formation back side, the surface PN of described silicon substrate, also comprise and the step of carrying out chemical mechanical planarization every the surface of structure is handed over to described back side PN.
3. the manufacture method of reverse-conducting field according to claim 1 cut-off type insulated gate bipolar transistor, it is characterized in that, the step of field cutoff layer of N-type is prepared on the described surface being filled with the silicon of the second doping type at silicon substrate by epitaxy technique before, the silicon of temperature to described second doping type of filling also comprising employing more than 800 degrees Celsius carries out the step of single crystallization process.
4. the manufacture method of reverse-conducting field according to claim 1 cut-off type insulated gate bipolar transistor, it is characterized in that, the described thickness of silicon substrate in the step of the silicon substrate of the first doping type that provides is 100 ~ 650 microns, the thickness of described field cutoff layer is 2 ~ 100 microns, and on described cutoff layer on the scene, extension prepares the thickness of drift region in the step of the drift region of N-type is 10 ~ 650 microns.
5. the manufacture method of reverse-conducting field according to claim 4 cut-off type insulated gate bipolar transistor, is characterized in that, the doping content of described field cutoff layer is 4*10
13~ 1*10
16/ cubic centimetre.
6. the manufacture method of reverse-conducting field according to claim 1 cut-off type insulated gate bipolar transistor, it is characterized in that, the described resistivity of silicon substrate in the step of the silicon substrate of the first doping type that provides is 0.001 ~ 100 ohm of * centimetre, described resistivity of filling the silicon of second doping type of filling in the step of the silicon of the second doping type in groove is 0.01 ~ 50 ohm of * centimetre, the step midfield cutoff layer of the field cutoff layer of N-type is prepared on the described surface being filled with the silicon of the second doping type at silicon substrate resistivity by epitaxy technique is 5 ~ 100 ohm of * centimetre, on described cutoff layer on the scene, extension prepares the resistivity of drift region in the step of the drift region of N-type is 5 ~ 500 ohm of * centimetre.
7. the manufacture method of reverse-conducting field according to claim 1 cut-off type insulated gate bipolar transistor, it is characterized in that, describedly formed in the step of multiple groove structure by photoetching and the one side that is etched in described silicon substrate, the degree of depth of groove is 0.5 ~ 50 micron.
8. the manufacture method of reverse-conducting field according to claim 1 cut-off type insulated gate bipolar transistor, it is characterized in that, described PN overleaf hands over the step deviating from the surface formation back metal electrode of described field cutoff layer every structure, is adopt sputtering or evaporation technology to prepare described back metal electrode.
9. according to the manufacture method of the reverse-conducting field cut-off type insulated gate bipolar transistor in claim 1-8 described in any one, it is characterized in that, described front technique is the front technique of planar gate insulated gate bipolar transistor, and described reverse-conducting field cut-off type insulated gate bipolar transistor is planar gate insulated gate bipolar transistor.
10. according to the manufacture method of the reverse-conducting field cut-off type insulated gate bipolar transistor in claim 1-8 described in any one, it is characterized in that, described front technique is the front technique of trench-gate insulated gate bipolar transistor, and described reverse-conducting field cut-off type insulated gate bipolar transistor is trench-gate insulated gate bipolar transistor.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310389765.4A CN104425251A (en) | 2013-08-30 | 2013-08-30 | Manufacturing method of reverse conduction FS IGBT (field stop insulated gate bipolar transistor) |
| PCT/CN2014/084878 WO2015027850A1 (en) | 2013-08-30 | 2014-08-21 | Method for manufacturing reverse-conducting field-stop insulated-gate bipolar transistor |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310389765.4A CN104425251A (en) | 2013-08-30 | 2013-08-30 | Manufacturing method of reverse conduction FS IGBT (field stop insulated gate bipolar transistor) |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110473913A (en) * | 2019-09-11 | 2019-11-19 | 厦门芯达茂微电子有限公司 | A kind of reverse-conducting field cut-off type IGBT and preparation method thereof |
| CN111415984A (en) * | 2020-04-03 | 2020-07-14 | 南京芯长征科技有限公司 | Manufacturing method of reverse conducting IGBT device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN117712122B (en) * | 2024-02-08 | 2024-04-26 | 深圳天狼芯半导体有限公司 | Silicon carbide IGBT structure, manufacturing method and electronic equipment |
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- 2014-08-21 WO PCT/CN2014/084878 patent/WO2015027850A1/en active Application Filing
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110473913A (en) * | 2019-09-11 | 2019-11-19 | 厦门芯达茂微电子有限公司 | A kind of reverse-conducting field cut-off type IGBT and preparation method thereof |
| CN111415984A (en) * | 2020-04-03 | 2020-07-14 | 南京芯长征科技有限公司 | Manufacturing method of reverse conducting IGBT device |
| CN111415984B (en) * | 2020-04-03 | 2022-11-25 | 江苏芯长征微电子集团股份有限公司 | Manufacturing method of reverse conducting IGBT device |
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| WO2015027850A1 (en) | 2015-03-05 |
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